TW428136B - Method and system for validating application graphical display output - Google Patents

Method and system for validating application graphical display output

Info

Publication number
TW428136B
TW428136B TW087114203A TW87114203A TW428136B TW 428136 B TW428136 B TW 428136B TW 087114203 A TW087114203 A TW 087114203A TW 87114203 A TW87114203 A TW 87114203A TW 428136 B TW428136 B TW 428136B
Authority
TW
Taiwan
Prior art keywords
display output
graphical display
frames
operating systems
software application
Prior art date
Application number
TW087114203A
Other languages
Chinese (zh)
Inventor
James L Tayler
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW428136B publication Critical patent/TW428136B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3668—Testing of software
    • G06F11/3696—Methods or tools to render software testable
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3668—Testing of software
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)
  • Stored Programmes (AREA)

Abstract

A method of validating that a graphical display output of a given software application is consistent across respective operating systems. The method begins by capturing successive graphical display output frames at a given execution point in the software application on each of the respective operating systems. The pair frames are then processed to generate a delta value that masks graphical display output constructs for the respective that are time-invariant across the pair of frames. The delta values generated during each test run are then compared, preferably using a statistical analysis, to validate that the graphical display output of the given software application is consistent across the respective operating systems. The technique may also be used to validate the application across multiple execution runs in a homogenous computer system.
TW087114203A 1997-12-22 1998-08-27 Method and system for validating application graphical display output TW428136B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US99562997A 1997-12-22 1997-12-22

Publications (1)

Publication Number Publication Date
TW428136B true TW428136B (en) 2001-04-01

Family

ID=25542037

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087114203A TW428136B (en) 1997-12-22 1998-08-27 Method and system for validating application graphical display output

Country Status (4)

Country Link
JP (1) JPH11338736A (en)
KR (1) KR19990062579A (en)
CN (1) CN1179271C (en)
TW (1) TW428136B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001097034A1 (en) * 2000-06-14 2001-12-20 Seiko Epson Corporation Automatic evaluation method and automatic evaluation system and storage medium storing automatic evaluation program
US7379600B2 (en) * 2004-01-28 2008-05-27 Microsoft Corporation Method and system for automatically determining differences in a user interface throughout a development cycle
WO2013108381A1 (en) * 2012-01-18 2013-07-25 トヨタ自動車 株式会社 Information processing device and information processing method
WO2021108214A1 (en) * 2019-11-25 2021-06-03 Nxstage Medical, Inc. User interface monitoring and verification thereof in medical treatment systems

Also Published As

Publication number Publication date
CN1179271C (en) 2004-12-08
KR19990062579A (en) 1999-07-26
JPH11338736A (en) 1999-12-10
CN1227940A (en) 1999-09-08

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees