TW427078B - Digital modulation method, digital demodulation method, digital modulation circuit, and digital demodulation circuit - Google Patents

Abstract

A digital modulation method which is to conduct multiplexing for the initial data of a plurality types of t bits in the beginning on the input block (before conversion) to generate a plurality types of multiplexing sections; and conducting exclusive logic and operation on the beginning t bits and the t bits thereafter for each multiplexing sections and using the operation result to replace the immediate following t bits; and, conducting exclusive logic and operation on the replaced t bits and the immediate following t bits and using the operation result to replace the t bits thereafter; similarly, conducting the same combining process in the following and individually operating the generated plurality types of the direct current component of sections after conversion from the combining process; and comparing each other with the absolute value of each direct current components to select the minimum converted section to output to the outside.

Description

4270 7 Q A7 B7 ^ ¾—Printed by the Central Government Bureau of Off-line Work Consumer Cooperatives. V. Description of the Invention (1) 1 I Field of Skills 1 1 I The present invention relates to a digital modulation method for digitally modulated m circuits. Demodulation circuit and digital demodulation method 0 The present invention relates in particular to a digital modulation circuit and a digital tuning circuit for recording a waveform of a recorded letter in order to record a 1 1 1 unknown data string in a recording medium. Method and digital demodulation circuit and digital demodulation method for demodulating the doubled waveform into a series of 1¾ 1 1 material series 0 '/ idea 1 thing 1 a. Refill the scene technology item 1 Binary data series are adjusted Match into a proper writing signal waveform record | And recorded in the recording medium 0 such as two The raw material series is paginated by RLL 1 1 bricks and then recorded in the recording medium by NRZ I. This can increase 1 t high recording density. 0 Binary data series sometimes have M as it is. 1 1 NRZ Modification or NRZ in 1 changes and recorded in the recording medium. Order 1 In the RLL code, the data words of π bits are sequentially output from the input material of the loser. The data will be recorded separately. Code word converted into η-bits> The 1 1 | conversion is applied to increase the minimum value Tm in of the polarity inversion interval of the recording signal after NRZ I modulation and increase the minimum value Tm ax Limit 0 means to limit the number of bit factories 0 j existing in bit factory 1 j between bit factory 1 j and bit "1 J in bit code after RLL I encoding is limited to d 且 and k涸 Κ 下 者. ί 1 The RLL code converted under this limit is considered to be beneficial (d, k; η) 1 | RLL code) 1 I In the R RZ I modulation, the RLL code M bit factory 1 ″ is inverted ! ί ΪChoose 1 1 I with the bit factory 0 J without inverting the modulation so that after the NRZ I modulation record 1 1 the bit inversion interval in the signal will be greater than before the NRZ I modulation RLL generation 1 1 The bit reversal interval 0 in the code is therefore the same as the RLL code 1 before NRZI modulation! This paper size applies the Chinese national standard ((_: NS) Λ4 specification (2 丨 OX 297 mm) | 3 9 5 5 0 427078 A7 B7 V. Description of the invention (2) Comparison of recording and reproduction in a recording medium, the situation in which M records the recorded signal after the NRZI stem is recorded in the recording medium and reproduces it can reduce the reproduction signal. The result is that the waveform is distorted, and the error can be reduced. In the case that the reading error of the same degree is allowed, the record number after the NRZI modulation is recorded in the recording medium, compared with the recorded signal before the NRZI modulation. Recorded in The conditions in the recording medium can actually improve the recording density. The following points are expected in the wave series of the recording signal. (1) The minimum value of the polarity inversion interval Tmin of the recording signal, Tmin, Tmin is M "d + 1" and It is calculated by detecting the product of the window width Tw. When the recording density is increased, the reversal interval of the recording signal becomes smaller, and the reproduced signal is easily distorted due to the waveform disturbance. As a result, a burst error is easily generated. In order to reduce the reading When the waveform density of the recording medium with a higher recording density is reduced to reduce the output error, the larger T mi η is better. (2) The maximum value of the polarity inversion interval Tmax of the recording signal Tmax Tmax is M "k + 1 ″ and the detection window width Tw. The regeneration pulse cannot be obtained between the polarity is not inverted. Therefore, the clock cannot be directly generated from the regeneration pulse, and the clock is more likely to become incorrect. When the polarity is inverted As the interval becomes longer, the fluctuation of the DC component becomes larger, so the smaller TinaxK is better. (3) The DC component or low-frequency component recording device and reproduction device have AC coupling elements. Therefore, 'When the recording signal holds a DC component, Time * Because the waveform of the signal recorded in the AC coupling element is distorted, it is not good. Also, the DC component lost during the recording cannot be restored during reproduction. Therefore, the DC component or low frequency component M is more suitable for Chinese prisoners than the paper size. House mark 4 *. (RNS) λ_4 specification (210X2W mm) 2 3 9 5 5 0 (Read the precautions on the back and fill in it again ^ this page) '1τI I r—I-.1 [~ 4 270 7 8 A7 B7 Economics " Ministry of Judgment # ^ 局 贝 工 消 贽 联合 社 印 繁 5. Description of the invention (3) 1 1 The lesser is better 0 1 1 For the evaluation of the low-frequency component of the DC component in the E record signal, you can use 1 1 DSV (Digita 1 Sum Va 1 U e: Digital Sum Value) C DS V β Set bit 1 1 Please 1 | Set the value of 1 j to 1 j 1 Set the value of -0 j to "- 1 J * To find the first time 1 1 Read 1 to record the cumulative value of the starting point of the recorded signal waveform. If the DSV ’s absolute value is 1 pair value is small> the DC component or low frequency component is also small 0 For the attention in each code 1 | Evaluation of the stream component or low frequency component »CDS (CO dew 〇rd Dig it a 1 item and 1 S um-total number of codeword digits) c CDS is DS V in each codeword. If this is filled in! This 1 ~~ | CDS is small, the DC or low frequency component of the codeword is also small. Ά I 1 (4) Detection window width T W i I Detection window width Tw is provided by U / η) T and indicates that the time that can be used in the detection of the regenerative bit i 丨 yuan indicates the resolution capability. In addition, the detection window width IT w indicates that the reproduced signal due to waveform disturbance, noise, etc., has a lot of power to the phase change 1 1 I, and the larger one is better. 0 1 1 J (5) Constraint length LC 1 1 In order to change the code of Tin i η Tb a X DS V to 1 with reference to the codeword before and after, let's call the length of the codeword before and after the VVSH referenced at this time 1 1 as the constraint length L 〇0 The larger the L c is, the larger the erroneous transmission is-and it will also be complicated due to the 1 I circuit configuration. The smaller the M L c K is, the better. 1 1 However, in Japanese Patent Laid-Open No. 52-1 28024, it is disclosed that-1 1 is a technique for increasing the NRZ of the recorded signal after tuning τ i η * and reducing the technique of τυ ax 1 1 0 * 2 bit dataw 0 Γ d (data word) in the bulletin will be sequentially output from the data string that was input 1 1 and converted into 3 bit c 〇dew 〇rd (Generation 1! Codeword) RLL encoding • Ah can generate (1 7; 2 3) RLL code. The passivated I 1 paper guilt scale is applicable to the Chinese-National Standard (CNS) Λ4 specification (21 OX 297 mm) 3 3 9 5 5 0 The final bid of the Ministry of Justice and S; Industrial and consumer cooperatives 'seal *' 1 wood 427078 A7 B7 V. Description of the invention (4) The code string of the generated RLL code is modulated by NRZI. When the limit of d = 1 cannot be satisfied, (1, 7; 4, 6) RLL code is generated. Japanese Patent Laid-Open No. 1-27510 discloses a technique for performing code conversion (RLL coding) K to reduce the DC component of the recording 佶 number after NRZI modulation, which is to make Tmin of the recording signal after NRZI modulation. Technology that doesn't get smaller. In this publication, each π-bit segment is sequentially extracted from the code string after the code conversion *, and a plurality of redundant bits are inserted between each adjacent segment. The code string after the lengthy bit insertion is supplied to the HRZI modulation circuit. Here, the redundant bit is selected based on the state of the end portion of the immediately preceding segment, and whether the redundant bit is to be code-inverted between the inserted segments is selected. In other words, it is selected to reduce the DC component of the recording signal after NRZI modulation. Tioin is not reduced. Furthermore, Japanese Patent Publication No. 5-34747 discloses a method for converting a data string into an RLL. The code conversion rules are adjusted according to the arrangement of the data series, so that Tmin becomes 1.5T, Tmax becomes 4.5T, and Lc becomes 5T. Japanese Patent Laid-Open No. 4-7 7 9 9 1 discloses a technique for reducing the DC component of a recording signal after NRZI modulation and increasing Tmiri. According to the technique of the bulletin, 8-bit datawords are sequentially extracted from the input data string, and each dataword is converted into a 4-bit codeword. This conversion is performed in the code string after the conversion, and the number of bits "0" existing between the bits "1" becomes 1 M to 8 or less. In addition, there are two datawords for converting δ-bit data into 14-bit data. ^!-I nn m nrn ittt In (Please read the precautions before filling this page) This paper is applicable to Chinese countries. (ΓΝ5 j Λ4 specification u! 0x297 male foot) 4 3 9 5 5 0 4 270 7 8 ^ 0 〇Γ sentence V ο 2 low CO4 minus 0 points to ew into od flow ^ ^ 1 0 ^ Z _change M in — Letter 7 1 to AB _ Yu-Lu Zhi. Basically, remember Λ 2 'the next transposition Η 13 rdv of 13 TRZ to choose the CO end of WODS vde. The middle score is reported as a public account number straight 2] Λ * No. 10 31 letter 6-Lu Pingji special special tune book ZIZ R said Ν is low, the minus points are refilled and the degree is recorded as a secret note-俾The Π.1 report to the T Public University should be added. Place

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CW e is carried in the existing line, 17 string conversions are replaced by each subsequent conversion of rd to W0 in the ta system ad »Each conversion will be reversed (please read the precautions of 1 & before filling out this (Page) The digits between the digits and the digits. The number 2 is the number of digits. The number of the digits is 9 and the% of the digits. The digits of the 15 digits are 17 and the corresponding digits are the long digits of the wo digits on rd. The 8 2 I yuan and-position in 2 can be attached to the Iga ,, Zhongping Kai Teli special edition said on the general. There are two types of types that can be obtained from the second class. The third type is available with another-the Θ table with an intermediate report number is exchanged. The two C0 group followers are converted. The 15-bit long head of the Ministry of Economic Affairs, Standards and Standards Bureau of the Ministry of Economic Affairs ST. ^ ί 1 sentence alternatives. And the SV is set and the low reduction is reduced to the straight end of Γ0. At the end of the letter is recorded-Xiao Yiwu _E after the C0. The rephrasing is changed before the ZI R, N d instantaneous rd lies in £. The basis d is borrowed from C, borrowed, yuan, and the median said that the alternative is replaced by letter 4, dr, V, 3 J t The above is to restore the number of operations or table before the meta description, and the best choice for conversion is to choose additional options, such as M cases, etc.-It is expected that adults with low investment or low scores will receive Formed and converted to this paper, this paper scale is suitable for China 1¾ standard net (CNS), '\ 4 said grid (210X 297g t) 5 3 9 5 5 0 42707 8 A7 B7 Cooperative cooperative printing V. Description of invention (6) 1 1 〇 Therefore, the limitation of r on the aforementioned factory d "or" k J "will be caused by Yuan and the result 1 The unfavorable situation where Tin i η becomes smaller or Tm a X becomes larger 0 In addition, the place where the ternary of the code word III becomes larger It will happen that the Tv is small and the minimum decomposition ability becomes small. 1 1 Please 1 Unreasonable things 0 No reading J j Reading 1 1 Therefore, the main major aspect of the present invention is to provide-a kind of full suppression \ is I 1 I Digital modulation circuit for recording the DC component or low frequency component of 铧 signal, Digital / 1 Note 1 Modulation method Digital demodulation circuit and digital demodulation method Item 1 Another aspect of the present invention is to provide: --Kind of--The surface does not make the Τ mi η copybook -k'- Page 1 becomes smaller or Tm ax becomes larger-The surface can sufficiently suppress the DC component of the recorded signal or 1 low-frequency component digital modulation circuit digital modulation Method> Digital demodulation circuit 1 1 and digital demodulation method 0 1 1 Furthermore, another aspect of the present invention The huge system lies in: providing--a kind of--surface charge IT 1 points to suppress the DC component or low-frequency component of the recording signal and increase the Ttf 1 1 digital modulation circuit to improve the resolution ability N digital modulation method digital solution Modulation 1 j circuit and digital demodulation method 〇I In addition, another hundred aspects of the present invention are: providing--a digital modulation circuit that can reduce re-i | Variable digital demodulation circuit and digital demodulation method 0 1 1 Invention 塥 1 1 The digital modulation method of the present invention is to use an arbitrary Γ1 bit (but n ^ m ) Permutation corresponding to m-1 I Γ1 modulation method which converts to 1 to 1. Each m bit of the input digital data is treated as a code modulation order 1 1 bit, and each E bit is assigned K ID _ Π. η-bit tune data source 1 P-bits constituted by a predetermined number of data conversion units (t-bits)! This paper size applies to China National Standard (C: NS) Λ.1 specifications (210X 297 mm) 6 3 9 5 5 0 427〇 78 A7 B7 π Standard Bureau GiJ-Xiaozhu Hezhusha Yinfan 5. Description of the Invention (7) 1 i yuan input section data will be plural types of t-bit data each 1 1 (as initial data and Give multiple workers and use this to generate a complex number of conversions 1 i Change the actual material of the segment 0 Perform r— >! 1 on the data of the pre-conversion segment The calculation of the t bit at the beginning and the t bit immediately after it is read first. I read 1 r and its mutually exclusive logical sum (e XC 1 u si ve 1 0 g 1 C a 1 S um) T & I Result 1 t-bit after the replacement. The t-bit after the replacement is calculated for its attention. The 7-bit mutually exclusive m series and the t-bit matter immediately after the replacement of the calculation result are filled in with 1 yuan. The following also performs the calculation processing and replacement processing of the mutually exclusive logical sum.% 本-»^ I Combine the processing to the end of the pre-conversion segment data and generate the converted segment data from each of the transition pages 1 1 before the pre-conversion segment information. 0 Compare each white 1 1 ΙΠ-η modulation of each type The DC component M of the data of each modulation area 1 and 1 obtained from the latter segment is selected. The initial data corresponding to the data of the variable segment with a smaller absolute value of the DC component is selected to generate the initial data to be selected. I is expected to use m before the multiplex conversion for the segment data. 1 η modifies the segment for sale. 1 The better choice is based on the accumulation of the DC component of the final 11 bits of the segment data. Absolute value The minimum modulation section 1 1 data is performed by 0 1 1 and the description is based on the modulation that specifies the absolute value of the maximum amplitude of the maximum value of the cumulative value of the DC component 1 1 of the modulation section data. Section data 1 而 Performer 〇 1 1 Another aspect of the present invention — digital modulation circuit of the situation t ^ * By using any j 1 bit arrangement of any 1 1 1 meaning, any η bit (but η Π1) Conversion of permutation pair ate 成 to 1 1 1 to 1 m-η modulation method treats each M bit of the digital asset department as the generation 1 1 This paper is scaled to China State Standard (CNS) Λ4 Present case (2 丨 0XM7 male i) 7 3 9 5 5 0 427078 A7 B7 V. Description of the invention (8) i ί Code modulation unit 俾 makes each η bit π -η tune into η bit modulation cost The r 1 1 buyer is a 1-bit P-bit input section composed of a predetermined number of selling units (t-bits). At the beginning of the data, the t-bit asset section of the complex type 1 I, please 1 I, respectively, as the initial data to multiplex and generate multiple types according to the multiplexing circuit. Read 1 I Read 1 Type I conversion »r. Month , Section J material 0 For each of the pre-conversion section resources for the plural types ♦ 1 1 Perform the t bit at the beginning of the pre-conversion section resource and the t bit immediately after it < L Note 1 1 Mutual exclusion logic and calculus Reuse the result of the calculus to replace the t bit after its instant. Matter i, fill in 1 with the mutual exclusion logic and calculation script of t bit after the replacement and t bit after the instant -i'- | f Use the result of the calculation to replace the t bit after the instant. Page 1 1 Data modulation circuit and merge processing (C on V 0 1 ut 1 ο η Γ Γ 0 C es 3) consisting of mutual exclusion compliance calculation processing and replacement processing 1 1 The end of the 1st segment of the transformation area is generated from each of the pre-conversion segment contributions, and the post-conversion segment order is generated. 1 The data is calculated by the calculation circuit. Each of the plural types of post-conversion segment data is obtained by a calculation circuit. 1 Bai Jingyu m- DC component of each modulation section obtained by η modulation 1 1 The comparison circuit compares the magnitude of the m pair value of each DC component and M selects the circuit 1 f selects the modulation section with a smaller absolute value of the DC component Data corresponding to the first phase of data generation was generated using a modulation circuit 1-η modulation section data 1 1 corresponding to the initial data to be selected to be M 1 1 multiplexed before conversion. The better one is the U-month selection circuit which selects the modulation section data. In the end, the absolute value of the cumulative value of the DC component of the 1 bit is 0. Take the smaller initial data corresponding to the modulation section data 1 1 i. Furthermore, the aforementioned selection circuit selects the largest modulation section data. The value of m lirb for amplitude t 1 is the minimum initial resource corresponding to the modulated segment data. 〇1 1 Furthermore, there is a memory for storing the modulated segment data *. State Central China National Standards U'NS) Λ4 size (210X297 mm) 8 3 9 5 5 0 4270 78 A7 B7

V. Description of the invention (9)! The I circuit reads out the memory from the memory corresponding to the initial data selected by the selection circuit. The converted segment data M 1 performs m-η modulation = 1 1 and then the segment data is entered. It is stored in the memory. From the memory, 1 I, please 1 I. Input the data of the input section. The initial data selected by the selection circuit is pseudo-first read. 1 1 read 1. 2 The multiplexing circuit is multiplexed. The multiplexing circuit output converts the data in the I segment at the beginning to the mutual exclusion of the t bit at the beginning and the t bit at the instant. The 1 1 f series and calculation replace the fllff at the instant of t according to the result of the calculation. Permutation matters for bit 1 1 Fill the mutual exclusion logic and calculation of t-bit after t and t-bit after the moment VX The page,-, ί · '— I calculation results replace the moment In the t-bit bit M, the merge processing consisting of the mutually exclusive series 1 I and the arithmetic processing and replacement processing is also performed to the pre-conversion segment 1 1 The second data conversion circuit from the pre-conversion segment Data generation 1 The converted segment data and the M modulation circuit will output the converted segment data output from the second data conversion circuit I to M η modulation c 1 II. In addition, another form of the present invention is: A digital demodulation method in which 1 1 j uses the η bits of the input digital data as a code demodulation unit and each 1 I ω M η-m is demodulated into m bits (but η is m ) The demodulation data is generated in order. 1 The demodulation segment data is composed of a predetermined number of data inverse conversion units (t bits). 1 of the t-bits 1 1 Mutually exclusive logic and calculus and replace the first t-bits with the result of the calculus. ) Enter i I and delete the above 11 ^! The mutex logic and calculus of the t bit after the instant and the t bit after the instant t bit 1 i and replace the t after the instant according to the result of the calculation Bit 1 1 kk also performs the merge processing composed of the mutually exclusive ORR series calculation processing and setting processing 1 1 to the end of the demodulated segment data to generate a reversed 1 1 swapped segment. Responsibility 〇II This paper is in accordance with the Chinese National Standard (CNS) Λ4 size (210X29 · / mm) 0 3 9 5 5 0 This paper is in accordance with the Chinese standard 隼 (CNS) Λ4 size (210 X297 mm) 3 9 5 5 0 4270 7 8 A7 B7 V. Description of the invention (10) Furthermore, another aspect of the present invention is a digital demodulation circuit, which uses each n bit of the input digital data as a code demodulation The demodulation circuit uses the demodulation circuit to demodulate Kn-m into m-bit (but ηπ) demodulation data, and sequentially generates demodulation section data composed of a predetermined number of data inverse conversion units (t-bits). , Information Convert Units Μ latch circuit holds until the end of the replacement process of its data inverse conversion units. The inverse conversion circuit performs demodulation logic and calculation of the t bits at the beginning of the segment data and the t bits at the instant, and replaces the t bits at the beginning with the result of the calculation. And the t bit following the t bit immediately after the mutually exclusive OR logic calculation, and the t bit following the above is replaced according to the result of the calculation, the following will perform the calculation process by the mutex OR logic The merging processing consisting of the permutation processing and the end of the demodulated segment data is performed to generate the inverse transformed segment data. Furthermore, another aspect of the present invention is a digital modulation method, in which an arbitrary n-bit (but m) arrangement corresponds to a conversion pair 1-to-m-by In the η modulation method, each id bit of the human digital material is regarded as a code modulation unit, and the person who makes each m bit nn modulation into n bit modulation data, using a conversion table from the moment before The demodulation code unit or the initial data number after the conversion is completed, and the data of the demodulation code unit before the conversion are converted into the data of the demodulation code unit after the conversion to generate plural types of section data, and the plural types are compared with each other. The DC component of the segment data is the Kro-n modulated segment data with a smaller absolute value of the DC component. Furthermore, the other aspect of the present invention is to use a multiplexer circuit at the front end of the input section of p bits that is an integer multiple of t bits (bit st "eani) cut out by the input bit stream. Each of the t-bit initial data of plural types is increased by 10 (please read the notes on the back before filling this page) Ding-¾ 427078 A7 B7 1 1) 1 1 Process > K Generate a multiplexed segment of a complex type with respect to the multiplexed 1 I of the complex type. Each segment of the I segment is subjected to a calculation circuit to perform its multiplexed segment. Mutually exclusive logic and calculus of t-bits after the instant and use its calculation result I! Please [[If the t-bits after the instant are replaced, the t-bits after the permutation and the t-bits after the first read 1 I read 1 I-bit mutually exclusive compilation and calculation and replace its instantaneous back according to the result of the calculation > 1 t-bit = Μ The same is performed by the mutex logic and the Calculation processing and permutation Note 1 Matter 1 The combined processing composed of processing reaches the end of the multiplexed section. 0 The direct current term is used to calculate the complex number generated by the processing of the combination calculation circuit. The DC components of this class I converted section are compared with each other. The absolute value of each DC component is ν ν-1 1 The value of the smallest converted section can be selected by the selection circuit to 1 1 K and output to the outside. 1 1 Furthermore, another form of the present invention is to multiplex a 1 I complex number at the front end of a round-in section of an integer multiple of 1 yuan by the t bit from the input bit stream t. The t-bit initial data is generated by multiplexing the multiplexing segment 1 I into a multiplexed segment of 0 I. The first generation circuit inserts the initial data to the first stage.] Within a row variable and the first Μ Subsequent generations are sequentially provided with t-bit conversions. The second generation data is sequentially read from the front end of the multiplexed section except the initial data in the multiplexed section.电 变 1 1 The number M _ ·, the calculation circuit calculates the interrelationship between the antecedent variable and the current variable! 1 Lianji and Μ generates the converted data 0 Provides the converted data to the first — * Substitute it into the 1 I circuit at the same time According to the converted data, the second current calculation circuit M from the front end other than the first 1 I division of the multiplexed section is sequentially replaced by the second calculation circuit 1 1 1 », and the M DC component calculation circuits are calculated by the first 1st generation circuit, 2nd generation circuit 1% The processing of the first calculation circuit and the second calculation circuit are each complex I! This paper is compliant with the Chinese National Standard (CNS) Λ4 specification (2I0X297 mm) 11 3 9 5 5 0 427078 A7 B7 OK " Coordination of work and elimination of labor. Cooperative printing V. Description of the invention (12) 1 | Straight 1 I stream component t of the complex type generated by the multiplexed section of the number type and compare each DC component with each other The magnitude of the absolute value is selected! Ί | The circuit selects the smallest converted section and outputs it to the outside 0 1 I 谙 I Further 9 Another aspect of the present invention is a digital modulation circuit, read first 1 I read 1 I use the input section generation circuit to sequentially cut out the human section of t-bit integer multiples of the input bit (i η ρ ut it back 1 of 1 jstream) • and Attention 1 I Matter 1 The data generation circuit generates the initial data of t-bits of plural types. For the first time, the K term 1 is filled! Chapter ^ Substitute the circuit to the initial data Substituting into the preceding variable f and the second time M this V-I will sequentially replace the provided t-bit converted data, and the second generation M 1 1 I input circuit will sequentially input from the input area each time At the beginning of the segment, read the current of t bit 1 1 Actually put it into the current number of 0 Μ The first calculation circuit calculates the mutually exclusive logic of the leading variable and the 1 1 current tut number to generate the converted data and the converted data will be converted. Order 1 material is supplied to the first generation circuit, and the converted data is used to sequentially replace the current data extracted from the beginning of the input 1 1 section with the second calculation circuit. 0 Μ 1 | Generation circuit, second Substituting circuit% The first calculation circuit and the second calculation circuit 1 1 process the conversion of the complex type generated by the initial data about the complex type. The DC component of the post-segment i is calculated by the calculation circuit and compared with each other. The absolute of ingredients The size 9 is selected by the selection circuit, which is the smallest 1 1 converted section. It is output to the outside. 0 1 1 or 1 is better, 7 The converted ± m modulation circuit of the converted section is adjusted to a predetermined 1 | The recording letter segment of the method * Μ The DC component calculation circuits each calculate the DC to I i I points 0 1 when each white tone of the converted number segment is converted to the recording letter segment 0 and the Μ selection circuit will have selected The converted section is output towards the modulation circuit. 1 1 1 1 12 This paper size applies to Chinese gardener standards ((: \ 5), 6 and 4 cases (210/297 feet) 3 9 5 5 0 4270 7 8 A7 B7 Printed by the Central Bureau of Standards, Consumer Affairs, Cooperative Cooperatives. V. Description of the invention (1 ^ 1 i, or better, the DC component is a circuit that calculates the DC component of the final bit of the 1-bit segment of the converted area after the calculation. Cumulative value 〇1 1 I Furthermore, the DC component calculation circuit is calculated Please read the maximum amplitude of the cumulative value of 1 1 for the DC component of the converted section. 0 1 1 Furthermore, another aspect of the present invention is a digital modulation method that uses i & I of T & to input the bit stream. Note on the in-segment of the integer multiples of the t-bits that are opened. 1 At the beginning of each I, the initial data of the t-bits of the plural type are given to the M multiplexer, and the item is filled with I 1 Μ to generate the plural kinds. The multiplexing section is the mutex of plural kinds of multiplexing section on this page-k — I. The mutual exclusion of the t bit of the multiplexing section and the t bit 1 of the instantaneous 1 II are late. Computation and calculus, and replace its instantaneous t-bit 1 1 | 1 according to its calculation result. The mutual exclusion logic and calculus 1 of the t-bit and subsequent t-bit after replacement [and replace it with its calculation result T bit after the instant (the same under K) > Calculate processing and replacement processing by order 1 mutual exclusion logical sum The combined merging process to 1 1 The end point of the multiplexed segment 0 1 of the complex type generated by the merging process I The DC component of the converted segment can be calculated by each S and the magnitude of the m pair of each DC component i can be compared with each other Select the converted segment with the smallest size and output 1 I to the external 0 1 1 I. The comparison of the DC component is preferably based on adjusting the converted segment of the complex m type generated by the merge process 1 i Recording method 1 1 The DC component is recorded when the signal segment is recorded. 0 The calculated DC component is 1 1 is the cumulative value of the DC component of the final bit in the I ^ Γ segment after conversion. 0 is calculated by 1 i. The DC component is 1 of the cumulative value of the DC component of the converted section | the maximum amplitude is 0 1 I Furthermore, another aspect of the present invention is a number Demodulation circuit U 1! Paid standard home Peel (CN Qing ship χ depends not dust) 1 3 3 9 5 5 0 ^ 427078 A7 __B7 five dirty fine present described invention (! 4) The opening circuit opens an input section of a predetermined number of bits from the initial asset of the input bit stream M t bit, and performs the t bit at the beginning of the input section and the t bit immediately after it. Mutually exclusive logic and calculus, and replace the first t bits according to the calculus result. Perform the mutually exclusive logic and calculation of the t bit after the instant and the t bit after the t bit, and replace the t bit after the instant with the calculation result. The merge processing consisting of the repulsive logic sum calculation processing and permutation processing reaches the end point of the input section * to survive the inverse transformation section resources of the input section. Another aspect of the present invention is a digital demodulation method. A cutting circuit cuts out an input area of a predetermined number of bits starting from the input bit stream starting with the initial data of t bits, and performs the input in the input section. The mutual exclusion logic and calculation of the t-bit at the beginning and the t-bit at the instant, and the t-bit at the beginning is replaced according to the result of the calculation, and the t-bit after the transient and the t-bit after the transient are updated. The t-bits of the mutually exclusive logic and calculus are replaced in the following, and the t-bits after the instant are replaced according to the results of the calculations. The following also performs a merge process consisting of the calculus of logically exclusive sums and the replacement process. Enter the end of the segment data to generate inverse-transformed segment data for the input segment. M-τ elimination co-operation with the Central Bureau of Economic Affairs

---- 1--I-^ ------ Ding V,-& (Read the precautions on the back before filling in this page J. Preferably, the number of bits t of the initial data, in When the data length of the input section is set to 8 b bytes, it is selected in the range of 2 bits t to 8 bits. In addition, the number of bits t of the initial data and the number of bits t The number of bits P * in the input section of integer multiples is selected within a range that satisfies the relationship of 0.003 with t / p and 0.015. The field-type specification indicates that this paper scale applies to the Chinese national standard. (( : NS) M is a grid (210 × 297 common trend) 7777 ^ 14 39550 A7 427078 B7 V. Description of the invention (I5) Figures 1A and 1B are diagrams illustrating the concept of the present invention with M. Figures 2A and 2B are Figures 1A and 1B illustrate conversion and inverse conversion according to the merge processing shown in FIG. 1B and FIG. 1B. FIG. 3 shows examples of data conversion and inverse conversion using the conversion table M. FIG. 4A and Fig. 4B is a schematic block diagram of an embodiment of the present invention. Figs. 5A to 5D are diagrams showing an example in which the initial data of the merging process is dispersed in the input section. Fig. 6 is a diagram A block diagram of a modulator according to another embodiment of the invention. Fig. 7 is a block diagram showing another specific example of a modulator. Fig. 8 is a block diagram of a demodulator according to an embodiment of the invention. Fig. 9 shows a block diagram of another specific example of the modulator. Fig. 10 shows a block diagram of another specific example of the modulator. Fig. 11 shows a block diagram of another specific example of the demodulator. The figure shows that the initial data Tj of the initial data Tj in the merging process are each 1, 2, 4, and 8 bits. The initial data Tj are dispersed into 80 bytes as shown in FIGS. 5A to 5D. The case in the input section * indicates the characteristic diagram of the suppression effect of the DC component when the '(2, 7; 1 * 2) RLL modulation is performed. Fig. 13 also shows the operation (1, 7; 2, 3) The characteristic diagram of the suppression effect of the DC component in the case of RLL modulation. Fig. 14 shows that the number of bits t of the initial data Tj in the merging process is 1 > 2, 4 * 8-bit initial data Tj are dispersed into As shown in Figure 5A to this paper, the size of the paper is suitable for China (囡) A4 size (2IOX 297 mm) | 5 39 5 5 0 (Please read the notes on the back first (Fill in this page again.) The Central Standards Bureau of the Ministry of Scripture, Π.Τ-Consumer Cooperative Press 54 4270 78 A7 B7 V. Description of the Invention (16) Figure 5D and attached to the 40-byte input section In the case of (1,7; 2,3) RLL modulation, a characteristic diagram showing the suppression effect of the DC component is shown. Fig. 15 shows that the number of bits t of the initial data Tj in the merge process are each 1 The case where the initial data Tj of 2, 4, and bits are dispersed into the input section of the 30-bit group as shown in Figs. 5 to 5D shows the DC component of the case where RLL modulation is not performed. Suppressive effect character painting. FIG. 16 shows that the number of bits t of the initial data Tj in the merging process are each 1 * 2, 4 * 8 bits. The initial data Tj are dispersed into 160 bits as shown in FIGS. 5A to 5D. The situation in the input section of the group is a characteristic diagram showing the suppression effect of the DC component when (2, 9; 8, 15 ULL modulation) is performed. Figure 17 also shows the (1 * 7; 2, 3) RLL Characteristic diagram of the suppressive effect of the DC component in the case of modulation. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Figure 1δ is the initial information in the combined process The number of bits t of Tj is 1, 2, 4 * 8-bit initial data. Tj is added to the 40-byte input section, indicating the DC component of the case where RLL modulation is not performed at the end. The characteristic diagram of the effect. Fig. 19 shows the initial data Tj of the initial data Tj in the merge process, each of which is 1, 2, 4, 8 bits, and TJ is added to the 160-byte input section. The inside situation is a characteristic diagram showing the suppression effect of the DC component when the RLL modulation is not performed. The lap 20 system will be merged. The initial number of bits Tj in the middle of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) for each paper size, e, Λ cc. 4270 7 8 kl Β7 by the Ministry of Commerce " 标 " -5: 1 printed by the Bureau of Industrial and Commercial Cooperatives Fifth, the description of the invention (17) 1! Is the initial data of 1 2 4-8 bits Tj is added in the 1 1 I input section of the 80-bit group (2 -7 1 ff) RLL modulation, and 11 lines (1 9 7; 2 3) RLL modulation 1 The horizontal axis is normalized to the data bit frequency 1 I and 1 I rate fb to indicate high pass. Characteristic diagram of the suppressive effect of the components 0 Xiankuo 1 1 Reading 1 1 The back of the tube handle is the most shapely back 1 I 1 Figure 1 and Figure 1B are diagrams explaining the concept of the present invention with K. Note 1 thing 1 in the present In the invention, according to the j-type initial data multiplexer item shown in Fig. 1A, fill in 1 1 so that the initial exchange data is multiplexed before conversion. The sequence A is provided on the data sequence converter 2 shown in this I to the first B, and is merged. Fn Page 1 1 Generate the transformed data sequence B shown in Figure 1 A and use digital coding. 1 1 The generator 3 generates the desired recording waveform string. At this time, the DC component is measured. 1 The generator 4 presets the DC component (the absolute value of DSV) in the recorded waveform to the minimum order. | The selection information of the initial material is provided to the data sequence. The converter 2 can record 1 1 output DC components with the smallest DC segment. 0 1 1 | Figure 2 A 圄 and Figure 2 B are used to explain the 1 I merge processing shown in Figure 1A and Figure 1B. In Fig. 0 and Fig. 2 of the conversion and its inverse conversion, each data Do ~ 1 Du -1 is a data composed of t bits. Here * t bit can also be phase 1 1 equal to m bit 9 which is the unit of RLL modulation. It can also be unequal or 1 1 if it is not modulated. 1 j In data conversion, in each area 1 On the front end of the segment data, J type 1 type I initial data (transition number T j > is substituted according to the first generation institution 3 1 and is multiplied by 1 1 | to generate j type of pre-conversion segment data. The Section 1 of the data of type j before conversion 1 The second substitution mechanism 32 substitutes the first calculation mechanism 33, and the code conversion units starting from 1 1 except for the initial data T j are sequentially performed by the first transformation 1 1 This paper size applies to the Chinese National Standard Apple (CNS) Λ4 specification (2 丨 0X297) 漦 γ 7 3 9 5 5 0 4270 7 8 Μ Β7 Printed by the Consumer Cooperatives of the Central Standardization Bureau of the Ministry of Consumer Affairs 5. Description of the invention ( 18) The II mechanism 33 converts the current code conversion unit of the conversion target and the current code to 1 1 before the unit is changed. (Initial The code or calculation at the end of the data conversion or the conversion to 1 I for the unit) should be replaced by the second calculation mechanism 3 4 1 1 Please 1 | to become the current code conversion unit (combined processing) 〇 Then, the second calculation mechanism Read I 1 Read 1 I 34 That is to set the result of the merge operation to the previous back calculation for the next merge operation & 1 I 1 m number processing 0 Note 1 Filial 1 to generate j-type converted segment data > In other words, for j items, fill in 1 category of pre-conversion section data (multiplexing section) first. Use the code at the beginning of the script to adjust the unit D 〇 and the initial data T m 〇 d2 to generate a page. 1 1 In addition to the initial data of the front-end code, the actual conversion of the variable unit is D 0, that is, 1 i is replaced with Do 〇 Second, the above conversion is used to end The calculation of the data D 0 of the code modulation unit 1 1 and the m 〇 d 2 of the next code modulation unit D t, the order I can also generate the next converted data D 1, which is replaced by D 1 and below. 1 I Iteratively repeats the calculation processing and replacement processing performed by the exclusive operation and the 1 1 merge processing of the I group to the final code modulation unit of the sector 0 1 1 I of the previous segment resource (multiplexed segment) each performs the conversion of the mutually exclusive logic and calculation of the t bit at the front end of the segment data before the transition and the 1 1 t bit immediately after the conversion, and according to the calculation result The 1 t bit after the instant is replaced. The mutual exclusion between the t bit after the instant and the t bit after the instant. 1 1 The selection and calculation are based on the result of the calculation. 1 I also executes the merge processing consisting of the above-mentioned interactive logic and arithmetic processing and the above-mentioned replacement processing 1 1 to The end point of the pre-conversion section data is generated from each of the conversion 1! Month tj section data (multiplexed section). After the conversion section data is reversed, as shown in Figure 2B, Except for the reverse conversion 1! This paper rule is applicable to the Chinese standard house (C'NS) grid (2 丨 〇 × 297 mm) | g 3 9 5 5 0 4270 7 8 A7 B7 V. Description of the invention (19) Front area The demodulation code unit other than the decoding brick unit (transition number Tj) at the front of the segment data • The current demodulation code unit of the reverse conversion target is sequentially performed, and the demodulation code unit before the current demodulation code army is changed. (Initial data or decoded code units before inverse conversion) mutually exclusive logic and calculations * are replaced with the current demodulated code units (combination processing). Thereby, the post-transformation segment data is generated. In other words, first, using the calculation of the demodulation code unit 〇 at the beginning and mod2 of the initial data Tj to generate the inverse transformed data Do, this is replaced with! ) / 〇. Secondly, using the above calculation of 0 (the demodulation code unit before the inverse conversion) and the ind2 of the next demodulation code unit D '1 can also generate the next inverse converted data Di, which is replaced with D' 1. Under M, the same process is repeated until the final demodulation code unit of the segment is 0. In other words, the T bit at the beginning of the input segment ("before inverse conversion" in Fig. 2B) that facilitates the reverse conversion of data is performed. Mutual exclusion of the Yuan and its t-bits (please read the notes on the back before filling in this page) After you have performed the performance and compilation, it will be described in a short time. The former replacement of the Yuan fruit level t settlement settlement should be used immediately afterwards and the exchange of the yuan position and the Yuan position by the Central Bureau of Standards Bureau of the Ministry of Work Consumer Cooperatives printed and described. The sum of the points on the point t and the moment of the final processing are expected to be calculated by the zone of the calculation stage and J 刖 fruit series. The reduction and the sample group are rational in the same way as the logic, and they will be replaced immediately before the reversal is reversed. From the section's time zone, you can change the data in the siTfi zone. Enter 1 in place and enter this order into the code, such as the code generation M adjustment, and the single code generation mediation. For single transcoding, the reverse generation is tuned in the solution as shown in this example. When it comes to the upper position, it also plays a single code to reflect its tone. The wrong side of the error is sent to the point where the loss is transmitted and the M is not correct. The paper size applies the Chinese National Standard (CNS) A4 (210X 297 mm) 9 1Λ 3 9 5 5 0 427078 A7 B7 V. Description of the invention (2 o) When a temporary error occurs on the demodulation code unit I * This error will only affect the demodulation code unit after the inverse conversion. The reversal of the reversal and the conversion of the materials are shown in the table. Table 3 is the most used to make the table available. 2 The table is shown in Figure 3. The example of the 0 chart is instantly changed from the table. The rotation is shown in Fig. 3. The first 4 digits of the single-code generation solution such as J τ that can be converted are transferred. The previous number is compiled at the beginning of the actual period or the single-code conversion is performed before β. After the single code solution, the code is replaced by the HTS * solution. The picture 3 shows the code or LLR travel. If the code is replaced by another single travel system, then the element of the column a of the word bit a is misplaced 3 and thereafter. It is expected that i2 withdraws the LP-U RL bit > -r 2Γ substitutes ^ for 2 and replaces a 噚 / f \ WMWi with inverse. It can be changed or changed, and the materials and equipments are more advanced. The material is changed to 4A, and the figure is wrong (please read the precautions on the back before filling this page) and the outline of the figure. Shi Shizheng's Mingfa was originally shown in Figure B 4 and shown in the middle series. Figure A 4 was calculated and combined with the profit.多 多多 科 Κ 予 人 轮 轮 种 · 种 种 种 种 种 种 种 利 种 利 利 利 种 利 种 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 种 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 利 种 种 种 利 利 利 利 利 利 利 利 利 利 利 利 利 种 种 种 利 利 利 器 利 利 利 利 利 利 利 利 利 利 比 3 器 利 器 利 Utilize and compare the performance of the VSD with the VSD Use the Ricoh Ministry of Economic Affairs Central Standardization Bureau Staff Consumer Cooperatives to print the value of 0 The shape wave number is recorded after the concatenation is used to change the tone __ I to Z β R 3 £ -N is small or most changed to ϊ ZO value RJ * T The students of the Department of Health and Regeneration are shown in Figure 4B. They are used in the wave, and the recording record is changed into 2 2 devices. The calculations are performed together, and the materials are used by the 11 2 devices. Capital wave wave reuse and loss Early. The reasons for the loss are in parallel, and the materials will be shown in 5D when the chart is displayed. The first paper is 5A. The paper size of this paper applies the Chinese National Standard (CNS) A4 (210X297 mm). 20 3 9 5 5 0 4 270 7 8 A7 B7 Men ’s workers in the central ministry and the smashed bureau. Consumers' cooperation and printing. 5. Inventory 21) It is an example of the human section in the example shown in Figure 1B Although the initial data T j of type j is multiplexed at the beginning of the 1 1 I section of the input area, the initial data in the example shown in Figures 5A to 11D is divided into M points in the section. Lose more 1 1 Please 1 1 Worker 0, that is, 5 A draws the 8-bit initial data in the input section before reading 1 I read 1 | at the beginning for multiple workers, the 5 B picture is The 4 places of 2 places are divided by Μ 1¾ 1 | 1 The 5C of scattered workers is shown in Figure 4 in 4 places of 2 places. 5D Fig. 5D shows that in each S place of 1 bit, multiple workers are divided into 0 bits and one item is filled in i. The data conversion efficiency is the same. In Figure 1 but in Figures 5A and 5B, the large-scale suppression of the DC component 1 1 is the same, but the calculation in the case of Figure 5B is less than that in Figure 5A. 0 I 1 The circuit configuration also becomes It is very easy. In other words, by using a data conversion efficiency 1 1 which is the same as that in FIG. 5A and FIG. 5B, a relatively simple circuit can obtain the effect of sufficiently suppressing the 1 system DC component. i 1 In addition »As shown in Figures 5A to 5D above, when the initial resource score 1 1 is divided into Z, the number of bits in each input segment of j is P = P / 2 ', and Attachment 1 1 The number of bits of the initial segmentation data added to the front end of each input segmentation segment is 1 Τ = t / Z, and the system is set to a wide range of 0. 0 0 3 ^ T / P Yun 0 .0 15 ″ The inside is more appropriate than 1 i. 1 6 is a block diagram of the modulator of another embodiment of the invention-1 l Figure 6 The unit of Go code modulation is composed of t bits The input section data of 1 is input from input terminal 90, using the initial data multiplexer 9 of type j. The initial data of t-bits of type j on the front end of each section 1 of l 1 (conversion number) T j) 1 can be multiplexed 9 to generate j multiplexed sections (pre-conversion section data 1 1 data) 3 in J) t, the so-called 1 section (P bit = t bit X 2) Refers to a book 1 1 2 1 Biaoxin (('NS) / \ 4 specifications (2Ι0χ 297 mm) 3 9 5 5 0 427078 A7 B7 V. Description of the invention (22) Several code modulation unit U-bit data), and It is a unit for comparing the absolute value of DSV. (Read the notes on the back, read the notes on the back, and then fill out this page. For the initial materials of j type (transition number Tj), each of the multiplexed sections of j type (pre-conversion section data) that is multiplexed on the front end * In the data converter 92a, the data conversion in the merge processing described in FIG. 2 is performed in order to generate j-type converted segment data. The data converter 92a includes the data in FIG. 2 The first and second substitution agencies 31 and 32 and the first and second calculation agencies 33 and 34 are described, and the converted segment data of the 1Tj type are stored in the first segment memory 93a, respectively. At the same time, it is input to j types of I DSV 丨 calculation and comparator 94. In this j type 丨 DSVI calculation · comparator 94, each of the j segment conversion data of the j type is subjected to RLL modulation and NIL modulation. The absolute value of the DSV in the situation, and the data of the converted segment where the absolute value of the DSV becomes the smallest is selected. When selecting the converted segment of the absolute value of the DSV, the data is collected, ^ Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Print out an inquisition showing the result of the selection The selector 95. The selector 95 pseudo-reads out the converted segment data (the absolute absolute value of DSV is the converted segment data) corresponding to the selection result from the above-mentioned 1 segment memory 93a and inputs it to The RLL modulator 96. In this way, the RLL modulator 96 is used to sequentially open the m-bit data index from the tribute string | each data index is converted into an n-bit code word and RLL modulation is performed Afterwards, NRZ I modulation can be performed by using NRZI modulator 97. In addition, Figure 6 is a circuit that adjusts the input section to record waveforms by using RLL modulation and NRZI modulation. After conversion, the paper size of this paper applies the Chinese National Standard (CNS) Λ4 specification (210'〆297 mm) 22 3 9 5 5 0 427078 A7 _____B7 V. Description of the invention (2 3) The data is for MRLL modulation and KRZI modulation In this case, the absolute value of the DSV is used as the absolute value of the DSV of the comparison target, but this is a condition unique to the circuit shown in Figure 6. For example, as shown in the aforementioned 4A * If the record in K is generated by the merge process Of the converted segment of the The absolute value of V is selected, and the DSV whose absolute value is the smallest after the conversion is selected. This can be used as a recorded waveform for NRZ modulation or NRZI modulation. At this time, the detection window can be increased. Wide Tw, and the effect of improving the regeneration decomposition ability. In this way, the object of calculating the DSV in order to suppress the DC component can be determined according to the desired recording waveform. In addition, the same applies to the case of communication bars. Figure 7 shows the tuning A block diagram of another specific example of a transformer. Printed by the Central Ministry of Economic Affairs, the Ministry of Economic Affairs and the Ministry of Economic Affairs (Please read the precautions on the back before filling out this page) This embodiment is designed to reduce the amount of memory in one sector. Quantity is constituted for the purpose. That is, in the specific example shown in FIG. 6 described above, in order to use the initial data of j type (transition number Tj), the converted section data of the j type converted is stored in the 1-section memory 93a, and The entire 1-segment memory 93a requires the capacity of the sector. In view of this, in this embodiment, B stores a multiplexed section (the data before the conversion), and the memory capacity of the K1 section is sufficient as the necessary capacity of the section memory 93b. In the following description, the description of the same parts as those of the specific example of FIG. 6 is simplified. The input section data | inputted by the input terminal 90 is pseudo stored in the first section memory 93b, and is simultaneously input to the j-type initial data multiplexer 91a. The j-type initial data multiplexer 91a multiplexes the j-type initial data (conversion number Tj). This generates the j-type segment data before conversion (this paper size is applicable to Chinese national standard 4M CNS) Λ4 specification (210X 297 mm) 23 3 9 5 5 0 270 7 8 at B7 V. Description of the invention (24) Multiplexed section). The segment data before conversion of the "] type, that is, input to the data converter 92a and is subjected to the aforementioned merge processing and is treated as the converted segment data of the j type. Mj type 丨 DSV 丨 calculation comparator 94 Compare the absolute value of DSV after RLL modulation and HRZI modulation, and detect the converted segment data where the absolute value of DSV becomes the smallest. Then, the actual data of the detected converted section (transition number Tj) is selected, and the selection result is provided to the initial data multiplexer 91b. After inputting the selection result, the initial data multiplexer 91b will multiplex the selected initial data (transition number Tj) at the front end of the input segment data read out by the 1-section E memory 93b and provide it to the data. Converter 92b. With this, the material conversion in the above-mentioned combination processing is performed in the material converter 92b, and the converted segment data is generated. The converted segment data is subjected to RLL modulation by the RLL modulator 96, and further NRZI modulator 97 is used for NRZI modulation and output. In addition, when RLL modulation and NRZI modulation are not performed on the recorded waveform, the comparison target portion of the absolute value of DSV is appropriately changed in accordance with the adopted recording method. It is the same as the embodiment shown in Fig. 6 above. FIG. 8 is a block diagram of a demodulator in one embodiment of the present invention. The data input to the demodulator shown in Fig. 8 is first supplied to the RLL demodulator 102 and demodulated by the RLL. The data (data before reverse conversion) demodulated by the RLL is supplied to the latch 103 and held, and is also supplied to the data reverse converter 104 at the same time. The data inverse converter 104 is composed of delay data (previous demodulation code unit) input from the latch 103 and data (current demodulation code unit) of the inverse conversion object input from the RLL demodulator 102, and Carry out the above-mentioned combined paper standard suitable for China Store Standard (CNS) A4 specification (2 丨 0X297 male; ~ ~~~ 1 4 3 9 5 5 0 (Please read the precautions on the back before filling this page) Order A7 4270 7 8 B7 V. Invention description (25) and the inverse conversion of processing. Therefore, the data will return to the original recorded data. In addition, when the recorded waveform is modulated by non-MRLL modulation and NRZI modulation, such as Section 4B As shown in the figure, the NRZI demodulator 101 or RLL demodulator 102 * shown in Fig. 8 is not required, and a demodulation circuit can be appropriately set according to the recorded waveform. Fig. 9 shows another specific example of a modulator, which is The modification shown in Fig. 6. That is, 1 is a specific example of the RLL modulator 96 shown in Fig. 6, and (1, 7) RLL modulation 96A can be used. If it is the implementation shown in Fig. 9 Form, the absolute value of DSV when (1 * 7; 2,3) RLL modulation and NRZI modulation are compared with each other, and the absolute value of the DSV is selected. The value is the smallest converted segment data. Here, the absolute value of the DSV to be compared may also be, for example, the final bit value of the converted segment data, or may be the largest value in the converted segment information. The absolute value of the amplitude. Fig. 10 shows another specific example of the modulator, which is a modification of Fig. 7. That is, an RLL modulator 96AM is provided instead of the RLL modulator 96 shown in Fig. 7. _And use type j 丨 DSV 丨 calculation • comparator 94 compares the absolute value of DSV after (1,7; 2,3) RLL modulation and HRZI modulation, and detects the conversion with the smallest absolute value of DSV Post-segment data. Then the initial data (transition number Tj) of the detected post-post-segment data is selected and the selection result is provided to the initial data multiplexer 91b. Figure 11 shows another specific example of the demodulator The example diagram is an example of the demodulator shown in Fig. 8. That is, the (1,7) RLL demodulator 102AM is used instead of the RLL demodulator 102 shown in Fig. 8. First, input data is provided to HRZI demodulator 101 and MNRZI demodulation * followed by M (l, 7) RU demodulation (please read the precautions on the back before filling this page)

-1T 6, [· Ay The size of this paper is the national standard of China (CNS) Λ4 specification (210X 297 mm) 25 3 9 5 5 0 ^ 4270 7 8 B7 Printed by Cooperatives

5. Description of the invention (2 6) The device 10 2 A performs RLL demodulation. The RLL demodulated data (data before inverse conversion) is supplied to the latch 1 03 and kept at κ 4 and provided to the data inverse converter 104 c. The data inverse converter 10 4 is used by the latch Read the delay data of the input device 1 0 3 first (previous demodulation code generation) and the reverse conversion target data (current demodulation code) input from the back of (1 > 7) RLL demodulator 1 02A. (Unit) Perform the inverse conversion of the merging intention processing. Therefore, the data W is returned to the original recording method and the data items are filled in again. Figure 12 on this page shows the initial blame T j in the merger processing. Each of t and ^ · are 1 2 and 4 8-bit initial resources T j are dispersed as shown in FIGS. 5A to 5D and added to 80 Characteristic in the input section of the byte indicates the performance of the suppression effect of the DC component when (2 7; 1 2) RLL is fine-tuned. Figure 13 shows the same (1 2; 2 3) RLL The characteristic diagram of the suppression effect of the DC component in the case of modulation. Figure 14 shows the number of bits t of the initial data T j in the merge process as 12, 4 »8-bit initial data T j As shown in Fig. 5A to Fig. 5D, the case of being added to the 40-byte input section shows the characteristic circle of the suppression effect of the DC component when (1 7 2 3) RLL modulation is performed. In the 15th painting system, the number of bits t of the initial data T j in the merge process is 12, 4, and the 8-bit initial data T j is divided as shown in Figs. 5A to 5D. In the case of an 80-byte input section, the RLL modulation is not performed. 1¾ The characteristics of the suppression effect of the DC component of the brother. Figure 16 shows the number of bits t of the initial data T j in the merge process is 1 2 > 4, and the initial data of the S bit T j is dispersed. Figures 5A to 5D are applicable to the Chinese national standard (C _ \ _ S). The size of this paper is Λ4 (210X 297 mm). 26 3 9 5 5 0 'Λ27〇7 8 Α7 Β7 V. Description of the invention (27) This is a characteristic diagram showing the suppression effect of the DC component when the (2, 9; 3, 15) RLL modulation is performed when it is added to the 160-byte input section. Fig. 17 shows that the initial data Tj of the initial data T j in the merging process are each 1, 2, and 8 bits. Tj is divided as shown in Figs. 5A to 5D and added to 160. The situation in the input section of a byte is a characteristic diagram showing the suppression effect of the DC component in the case of (1,7; 2,3) RLL modulation. Figure 1S shows the case where the initial data Tj in the merge process is twelve, two, four, and eight bits of initial data, and is added to the 40-byte input section, indicating that it has not been performed. Characteristic diagram of the suppression effect of the DC component in the case of RLL modulation. FIG. 19 shows the case where the initial number of bits t of the initial data Tj in the merge process is 1, 2, 4, and 8 bits, respectively, and the initial actual data T is added to the 160-byte input section. A characteristic diagram of the suppression effect of the DC component when RLL modulation is not performed. FIG. 20 is performed by adding the initial actual data Tj of the initial data Tj in the merge processing to 1, 2, 4, and 8 bits to the input section of 80 bytes, respectively. 7; 1,2) RLL modulation (solid line) and (1,7; 2,3) RLL modulation (dotted line normalizes the horizontal axis to the data bit frequency fb and the table shows Qualcomm Characteristic diagram of the suppression effect of the component pressure. As can be understood from Figs. 12 to 19, according to each embodiment, it can be seen at a glance that the number of M bits t is 2 or even 4, 8. The inhibitory effect of the ingredients .. ------ II (Please read the precautions on the back before filling this page) For paper printed by Manchuria Intermediate Affairs Bureau, Peigong and Hezhu Bamboo Co., Ltd. Chinese paper standards apply China (CNTS) Λ4 specification (210 X 297 mm) 27 3 9 5 5 0 ^ ^ 2Ί〇Ί ^ Α7 Β7 V. Description of the invention (2δ) Moreover, as shown by the dotted line in Figure 20, it can be clearly compared with The situation of (1,7; 2,3) RLL modulation is shown by the solid line. (2,7; 1,2) RLL modulation effect can be divided into straight and large ones. Piece profit P The number of seeds in the h industry and the number of seeds in the material t are added to the section before the end. &Amp; The number of types of seeds in the section of the transition is more than the number of conversions. Combine and handle PMU Rico.m / materials before the material section area change to the capital section area after the conversion straight and wait for the comparison and divided into direct control points within the spine can be used as media. The highest-ranking young talents in the post-replacement system are the points that can be scored and streamed. The direct paper can be selected and selected. The degree of fluidity is recorded. The national paper standard (CNS) Λ4 size (210 X 297) is applicable. ) 28 3 9 5 5 0 {Please read the notes on the back before filling this page

1T A. I.

Claims (1)

d27〇7 8 Attachment iill H3_ No. 871 0 3 6 9 7 Application for a patent application scope amendment (August 2, 1989) A digital modulation method * will be arbitrary in any m-bit arrangement η-bit (but nSm) arrays correspond to the mn modulation method that converts one-to-one. · Each b-bit of the input digital data is used as the code modulation unit. 俾 Make each a-bit each sn-ri modulation. Digital modulation method of ri-bit modulation data; at the beginning of P-bit input section data composed of a predetermined number of data conversion units (t-bits), plural types of t-bit assets are used. The number of species is regenerated, and the number of materials at the beginning of the material period is to be changed from each material segment area. Each species has 0 species. The bank's calculation of the input material is 3--replaced, and then the reciprocal unit is replaced. The reciprocated unit is replaced by the reciprocated unit. After that, change the position and the result of the element to calculate t Perform the re-examination and reconciliation of the repertoire and the reconciliation of the repercussions. The repercussions should be executed before the reciprocal reinterpretation. The borrowed materials can be transferred to the reorganization of the reorganization office. After the change, the employee welfare committee of the Central Standards Bureau of the Ministry of Economic Affairs printed the materials and sections after the change. After the materials are replaced, the ratios are different from each other, and the materials and materials are changed. Transformed into various students from the respective sections of K and BTT to obtain the expected resources, and then transferred to various types of 对 & 复 number of pairs of pairs and perfect students, the raw material flow directly mentioned in the beginning and the previous selection The selection of the materials in the direct flow zone of the material flow section is more than the change in the value of the material flow zone. The selection of the material period should be selected before the m-statement. For the change of the material section, select the item of its normal variable number before the eleventh paragraph. Fan Lizhuan please string as 2 paper standards applicable to China ® Standards (CNS) A4 specifications (210 X 297 public) 3 9 5 5 0 4270 7 8 H3 The Central Standards Bureau of the Ministry of Economic Affairs-Industrial Welfare Commission printed and selected the data based on the smallest modulation section data with the absolute value of the cumulative value of the DC component in the final bit of the specific modulation section data. 3. For the digital modulation method of item 1 in the scope of patent application, where the aforementioned selection is based on the modulation data of the smallest absolute value of the maximum amplitude of the DC component cumulative value of the specific aforementioned modulation data. Proceeder. 4. The digital modulation method according to any one of items 1 to 3 of the scope of patent application, wherein the aforementioned i-n modulation method is (1,7; b · n) RLL modulation method. 5. —A kind of digital modulation circuit * is in any m-bit arrangement · Any η-bit (but nSra) arrangement is correspondingly converted into a 1-to-1 m-η modulation method > _ 人 之Each Π-bit of digital data is regarded as a code modulation unit. Those who make each m-bit ι-η modulation into η-bit modulation data, including a multiplexing mechanism * in a predetermined number of conversion units (t Bit) constitutes the front end of the P-bit rotation segment data, and multiplexes the t-bit data of the plural types as initial data, respectively, and multiplexes them to generate the plural-type pre-conversion segment data; the data conversion mechanism, For each pre-conversion segment data of the aforementioned plural types • Perform mutually exclusive logic and calculations of the t-bits at the front end of the pre-conversion segment data and the t-bits immediately after it and use the results of the calculations to replace their instants T bit, the mutually exclusive compilation and calculation of the t bit after the replacement and the subsequent t bit, and then use the result of the calculation to replace the t bit after the instant The multiplexing process consisting of the calculation process of the mutually exclusive logic sum and the replacement process described above is multiplexed. End of the transformation section | Μ Generate the reprinted paper from each of the pre-conversion section data. The paper size is applicable to the Chinese family standard (CNS) A 4 specification (210 X 297 mm) 3 9 5 5 0 427078 __H3_ After the change Segment data; performance agencies, each of which obtains the DC components of each modulated segment data obtained by the respective m-η modulations of the plurality of types of converted segment data converted by the aforementioned data conversion mechanism; Before the compositional calculation is performed, the value of the comparison ratio is smaller than the ratio of the mutual structure. The initial comparison of the comparison mechanism of the comparison mechanism is compared with the adjustment of the previous section. The selection of the small K is more useful, and the selection of the structure of the machine will be straightforward and %%. The selection of the structure of the material is selected by the construction machine. The value of ΗDuo M, which was converted in front of the capital section, is expected at the beginning of the capital term. The accumulators of the fan selection are profitable materials. Please construct the application section in the application area. For example, select the adjustment bit of the transmission power in Liuliu 6 before the application. The community has become the most important part of the adjustment, and the 5th item of the number of adjustment bits of its road power in the selection. The perimeter fan is expected to apply for a special fund for the initial application, such as the Ministry of Economic Affairs Central Standards Bureau Employee Welfare Committee & the system of the absolute limit. Zhenzhe material is the most expensive period of the initial period of the initial investment of the period should be described in the area of variable funding. The pre-segment area and the change of the selection of the small 'The most structure is the value of the selection of the right to change the number of bits in the power of the body of the memory of the material in the post-segment area changes fflw Please choose from the application if there are 8 structural changes, including package changes, and structural options] Yueyi and reading in the collision SM. Recall the previous response from the Π- travel and merge the material section after the beginning of the response period The chooser changes the item including the number of WF digits in the electric circuit of the circuit. 5 The circle fanli special please string as 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public #) 3 9 5 50 Economy Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Education 427078 __H3_ Yes, memory for storing the aforementioned round-robin sector data; the second multiplexing institution, which will extract the input sector data from the aforementioned memory, will be selected by the aforementioned selection agency All The selected initial data is multiplexed; Lu and the second data conversion agency perform the t-bit at the beginning and the t-bit immediately after Mutual exclusion logic and calculation and use its calculation result to replace the instant t bit, perform the mutual exclusion logic and calculation of the replaced t bit and the following t bit, and use the calculation result to replace the following In the t bit * M, the merge processing consisting of the aforementioned mutually exclusive operation sum calculation processing and the aforementioned replacement processing is also performed until the end of the pre-conversion segment data. Μ generates a post-conversion area from the pre-conversion segment data. Segment data, and the aforementioned modulation mechanism uses Mm-n to modulate the converted segment data rotated by the aforementioned second data conversion mechanism. 10. The digital conversion circuit according to any one of items 5 to 9 of the scope of patent application, wherein the aforementioned m-η modulation method is (1, tORLL modulation method input and output of each material element digit The η-series auto-position and demodulation digit demodulation bit solution i generation bit π is the solution but the position > n All η when the number of units is reversed and the number of materials is reversed. The ordering and reconciliation of the material mediation unit position of the material section US mediation; the material section section describes the front of the end of the advance and the last momentary exchange unit, its position and the result of the yuan is calculated as 1J. The use of conjunctive calculations and post-harvest recounts the pre-logical logic of the meta-bits < Jt t's emblem. The paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 3 9 5 5 0 427078 The t-bit mutual exclusion series and calculation after H3 and f ί The result of the calculation replaces the instantaneous t-bit. The following also executes the logic of the pre-mutual exclusion Sum calculation process and the aforementioned replacement process Those who combine the data to the end of the demodulated segment data to generate the inverse-transformed segment data. 0 1 2 — — a type of digital demodulation circuit »includes; each n-bit of the digital data input by the demodulation mechanism Used as a code demodulation unit and demodulated by white demodulation circuit η-n into m bits (but η m) 9 Generates sequentially a predetermined number of data inverse conversion units (t bits) The demodulation section data of the demodulation section is maintained by the latch mechanism until each data inverse conversion unit is replaced. The M and the inverse conversion section perform the demodulation section generated by the previous demodulation section. The t-bits at the beginning of the data and the t-bits of the following t-bits are mutually exclusive and calculated, and the t-bits at the beginning are replaced according to the results of the calculations. T-bit The combination process consisting of the above-mentioned mutually exclusive series and the wing process and the above-mentioned replacement process is also performed to the demodulation section under the t bit of the instant after the repulsive series and calculation are replaced by the calculation result. The end point of the data Μ Generate the segment data after the inverse transformation. 0 13 · — A kind of digital modulation method M. Arbitrary m-bit arrangement converts any η-bit (but η ^ π) arrangement into 1-to-1 m -η modulation method, using each m bit of the input digital data as the code modulation unit | 者 If each m bit is adjusted to η bit modulation data, use a conversion table The data of demodulation code units or initial data numbers and conversion demodulation code units from ιαα before the end of the conversion is applied to the Chinese paper standard (CNS) A4 (210 X 297 cm) 3 9 5 5 0 8 7 ο 7 2 4 After code mediation, change to a 6B number like the straight-forward material segment area. Repeat the comparison before, and compare the small value of the material segment area with the material asset segment area. The Π layer Μ Μ includes the electric variable number of the packet circuit < Ϊ1, the open stream bit is lost by multiples of the unit bit P which is entered in the segment area before the long position of the lending machine; the number of units is complex; the bb each symbol bit multiplex zone section from / 1/1 Η Η lot of configuration classes coffin species of number of workers multiplexed plurality into said lifetime Μ a 'to X' multiple configuration to machine to the operator material acting owned and opened at the beginning of the period combined with Zhili Duan's calculations and multiple series of rebuttal rebuttals, each of the various bits and pieces of the daggers are divided into groups, and the number of species is immediately after the sum of the bits and the results of the replacement. The calculation of the instantaneous calculation and its meta-bit t-calculus t-calculation are followed by the exchange of profits. Μ ml R3 rt- The united group of the united unit ΪΕ 处 处 理 理 理 换 换 换 述 述 述 述 述 述 和 和 和 和 和 理 理 理 理 处 处 处 瞬 演 演 演 C C C C 3C Η0. Male 0 The finalized electricity is divided into a stream and directly connected to the paragraph The district has been converted from the post calculation to the various types, and the segmented structure of the point structure is finally divided into different divisions. The work flow of the biochemical laboratory is more straightforward, and the structure is printed by the staff welfare committee of the Central Standards Bureau of the Ministry of Economic Affairs. The small machine calculates its selection and sorting into K-stream. Those who are smaller than those who have lost the game before the big game are smaller than those of the dynasty. After the formation of the flow, the machine can choose between each rotation and the selected M. It is smaller than the first Q. The number of digits is integer, and the number of the two digits of t will be reopened from: each of them contains a person, including the wheel end, the electricity from the front, and the reconfiguration of the segmentation zone. Η Enter the number of digits The size of this paper is applicable to the specifications of the Chinese National Standards (CNS) A4 (210 X 297) 6 3 9 5 5 0 8 7 ο · 7ί The initial supply and resumption of the number of materials in the material period will be divided into the initial order of the second birth and the next generation of the artificial machine. The second generation of the material will be given to the second phase of the material. Η Explain the previous paragraphs except the sequence of the Huai Yihuan machine into the second generation of the second generation of the material flow electricity before the beginning of the material t out of the M material material period before the beginning of the paragraph before the beginning of the number change flow # & to the structure榇 Calculation-The first period of profit is changed to the current period of the current exchange period. Counting the material and calculating the internal work; changing the capital, playing the road, the material, the first electricity, the information, the first, the first, the narrative, the transfer of the technology, replacing the former, the former, the first division, the progress, the first from the front, the order, According to the calculation structure to the funding head of the material reading machine and the calculation of the material after the conversion, the performance of the second material is transferred to the outside, as described later, and the material is exchanged before the material is exchanged. Use Yanli Yi's first computer to calculate the calculations, and the roads will be divided into the current generation. Second, the roads will be calculated by the people. There are many kinds of II numbers. It is divided into straight sections and then changed. Η Several complex lives are obtained from each place and structure. The calculation is divided into different sections before the direct description. H Selects the economy. Zou Central Standards Bureau Staff Welfare Committee It is printed as a small big one whose value is large and the absolute one is divided into straight and straight lines. The performer moves out of the wheel department and then changes to the merged area. The most inclusive electric transformer fflw-bit number of the doubled round Integer The number of units t is cut out in the order of flow, and the number of units such as the unit t that is input and output from the formation section of the production machine is restored. The production machine uses the construction machine to generate raw materials and materials. Applicable to S Family Family Standard (CNS) A4 specifications (210 X 297 public directors) 3 9 5 5 0 42707 8 _H3_ First-generation institution • Initially put the aforementioned initial data into the preceding variables, and the second time after the replacement The t-bit conversion data provided by the preface is printed by the Central Bureau of Standards of the Ministry of Economic Affairs The reasoning of constructing the small electric square number stream segment and the electric power generation reading > i machine big change is fixed, and the direct analogy of the electric reporting place in Fuzhi District is added to its pre-constructed pre-construction, which is the same as the previous two. When the selection is completed, the number of input elements and machine-numbers will be changed to the number of sorts. The number of digits in the paragraph and the internal paragraph will be re-divided. . The performances of the section are made by the travel capital one machine, and the small one is confident. From the first person to the second person, they are lost to the second person. After they have been in office, they will be recorded in the end of each record. In other words, it means that the previous paragraph will be converted from the previous one to the next one, and the second one will be composed of the value part transformation. The second from the former-generation area will be compared to the other 16 changes. Each paragraph will advance the first and last ratio. The dynasty to the front will change the tuning, the district, the former, the next, and the next phase will be recombined and 14 will be rehearsed from the road; the structure and the structure are converted to the electric transfer mutual branch J. . Calculated before the performance, the calculation of the input into the ^ section into sections 箕 feed material branch performance class after the stream structure Fanbao District stream area to replace the variable performance material resources to implement a machine direct exchange for more profits Straight forward two open streams, one reprimand, two capitals, and the current stream has been transferred from the first choice to each other-the letter and the exchange of the third and the last exchange of the direct rehearsal and selection, please call the pre-recorded restructuring section The previous ones are based on the calculations of Xiaoshen Qiji, and the previous capital and achievements are quoted. The performance of this paper is equivalent to the Chinese National Standard (CNS) A4. Grid (210 X 297 male 3 9 5 5 0 points »The description selection mechanism is the person who rotates the selected W · month description conversion section towards the aforementioned modulation circuit and rotates it out. If you ask for the first patent scope ^ The digital modulation circuit of any of the 16- * items, in which the DC component calculation mechanism described above is the one that calculates the cumulative value of the DC component of the final bit of the converted segment. The digital tuning circuit of any one of the items 1 to 16 in which Λ Α. The DC component calculation mechanism described above calculates ^ r. Month ti describes the maximum amplitude of the cumulative value of the DC component of the converted section. 20 . For example, the digital modulation circuit of item 17 of the patent application park, where the predetermined method described is (1 7) RLL modulation method > 2 1 • A digital modulation method T-bit integer The front end of the input section of the multiplied P bit each sends the initial data of the t bit of the complex number to the multiplexing section to generate a multiplexing section of a plurality of types. T > month y multiplexing of the plurality of types Each segment performs a mutually exclusive operation and calculation of the t-bit of the Jf · 刖 end of the multiplexed section and the t-bit of the instant, and uses the result of the operation to replace the t-bit of the instant to perform the replacement. Mutually exclusive logic and calculations of the following t-bits and the instantaneous t-bits1, and use the calculation results to replace the instantaneous t-bits. The following calculations are also performed by the mutual exclusion and summation ^ -t- Describe the merge process composed of the replacement process to the S * N point of the multiplexed segment »The quotient calculations are from >-Describe the DC of the complex type of the converted segment generated by the merge process Components and compare the absolute value of each DC component with each other The smallest is 1 tl, which describes the converted section and applies the Chinese National Standard (CNS) A4 specification (210X297 public attenuation) toward the paper scale. G 3 9 5 5 0 427078 H3 External output 0 22 The method of digital modulation of the term is as follows: * The comparison of the DC component is based on the conversion of the plural types of the converted segment generated by the 1 J-narration merging process into the recording signal segment of the predetermined recording method. For DC component, please perform the digital modulation method of item 21 of the patent scope »where the DC component calculated is the cumulative value of the DC component of the final bit in the segment after the conversion. 0 24 For example, please refer to the digital modulation method of item 21 of the Fanfan Garden, where the calculated DC component is the largest cumulative value of the DC component in the converted section. Format 025 — A digital demodulation circuit including; a cutting mechanism that cuts out a predetermined number of bits from the input bit stream starting from the initial bit of M t bits, and an inverse conversion mechanism that performs the cutting structure The mutually exclusive operations and calculations of the t-bits in the input section and the t-bits at the end and the instantaneous t-bits are replaced by the first t-bits according to the result of the calculation. Ml The mutex and calculation of the t-bit after the instant and the t-bit following the t-bit immediately after the instant and using the calculation result to replace the following t-bit * M are also performed by Λ C. Merge processing consisting of narration mutually exclusive operation and calculation processing and narration replacement processing to the end of the round of segment data 1 Μ Generate the inverse conversion segment of the input segment. 0 26 A digital demodulation method Cut out from the input bit stream > λ t-bit initial data starts with a predetermined number of bits of input segment 1 Performs the aforementioned _-bit segment of the t-bit and its immediate t-bit Standard (CNS) A4 specification (210X297 princes) 1 〇3 9 5 5 0 Mutually exclusive compilation and calculation of 2707 8 _ H3_ printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs • Use this calculation result to replace the t bit in the front end To perform the mutually exclusive logic and calculation of the t bit after the instant and the t bit after the instant t bit, and use the result of the calculation to replace the t bit after the last bit. The same applies below A merge process consisting of the calculation process of the mutually exclusive compilation sum and the replacement process described above is performed to the end point of the input segment data to generate the inverse conversion segment data of the round segment. 27. For example, the digital modulation circuit of item 10 of the patent application, wherein the number of bits t of the initial data is located at 2 bits, such as when the length of the data in the round-in section is set to 80 bytes. Forget those within £ 8. 28. For example, the digital modulation circuit of the scope of application for patent No. 10, wherein the initial actual number of bits t and the number of bits P in the input section of the number of bits that are integer multiples of the number of bits t, It is within the range that satisfies the relationship of 0.003 t / p and 0.015 each. 29. For example, the digital modulation circuit of item 28 in the scope of the patent application, wherein each round division of the integer value P / z bits is obtained by dividing the input section of the aforementioned p bits by the M integer value z At the beginning of the segment, an integer value t / z = T-bit initial segment data is added by dividing the integer value z by the initial data of the aforementioned t-bits | K each generates a multiplexed segmented segment and processes it in the same way The composition of each multiplexed segmentation segment, the number of bits T of the initial data of each segmentation, and the number of bits P * of the round-in segmentation segment that is an integer multiple of the number of bits T are located to satisfy 0.003 ^ t / f > S 0.015. 30. For example, the digital modulation method of item 4 of the scope of patent application, in which the number of bits in the input section of the initial number of bits t is an integer multiple of the number of bits 11 The paper size is applicable to the Chinese national standard (CNS ) A4 specification (210X 297 public love) 3 9 5 5 0 427078 H3 P, which is within the range of 160 bits and 1600 bits. 31. The digital modulation method according to item 4 of the scope of patent application, wherein the number of bits t of the aforementioned preliminary data is within a range of 8 bits each of 2 bits t. lfi 32. If the digital adjustment of item 4 of the scope of patent application, (1) Taste core: Among them, the number of bits t of the above-mentioned initial multiples of the period data and the number of bits p in the segment 1 are in the range of 0.003S t / pS 0.015. Within the scope of the system. 33. The method of digital modulation according to item 32 of the scope of the patent application, wherein each input partition of the integer value p / z = p bits is obtained by dividing the integer value z by the aforementioned P bit input section At the beginning of the segment, an integer value t / z = the initial data of T bits divided by the initial value of M is added to each of the M integer values z. Each multiplexed segmentation section is generated by each M, and each The method of multiplexing segmentation, the number of bits T of the initial data of each segmentation and the number of bits P of the input segmentation segment which are integer multiples of the number of bits T, are located at 0.003 T / Pg 0.015 Within the scope of the relationship. Printed by the Staff Welfare Commission of the Central Standards Bureau of the Ministry of Economic Affairs This paper is applicable to countries and countries (c N S) A 4 (2 ΙΟ X 297 公 #) 3 9 5 5 0