經濟部中央標準局員工消費合作社印製 -4270 7 2 at _ 13。 五、發明説明（i) 本發明係有關於一種充電泵電路（charge pump circuit)，特別有關於一種能準確提供調升和調降電流脈 衝串（up and down current pulses)之充電泵電路。 依據先前相關技術，如美國專利第5,646,563號所揭 露者，如第1圖所示，充電泵120已被普遍應用於鎖相 迴路（PLL : phased-locked lo〇ps)100 中，以控制施予電 壓控制振盈器（VCO : voltage controlled oscillator)140 之 輸出電塵Vout。輸出電壓Vout基本上由流向濾波器 (filter) 130之電流Ic決定，電流Ic代表流入輸出節點125 之調升電流Ip和流出輸出節點125之調降電流In之差 值，開關電晶體122則用來導通(turn on)或關閉（turn off) 電流源（current source) 124，以提供調升電流Ip、對節點 125充電（charge)、並增加輸出電壓值Vout ’同理，開關 電晶體128則用來導通(turn on)或關閉（turn off)電流源 (current source)126，以提供調降電流In、對節點125放 電（discharge)、並減少輸出電壓值Vout。至於濾波器130 則用來減少因切換調升電流Ip和調降電流In所致之輪 出電壓波動（output voltage fluctuations)。 相位比較器（phase comparator)或偵測器（phase detector) 110則各自提供一調升控制信號UP和調降控制 信號DN以控制開關電晶體122、128之切換動作’其中 相位偵測器110主要係選擇一參考信號REF-IN ’而來自 電壓控制振盪器140之時序信號（clock signal) VCO-IN， 則透過直接或除頻器（frequency divider)150之路徑以與 ---------?--；----.訂-----線： -* (請先間讀背面之注意事項科填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X2?7公# ) 經濟部中央標準局員工消費合作社印製 4270 7 2 A7 __ Η 7 ____mmm m I ·>·^ν r-------* ~ ' ·ι _ _ 五、發明説明（2 ) 參考彳§破REF-IN比較其相位差（phase difference)。 其中’調升控制信號UP和調降控制信號DN之脈衝 寬度（pulse width)樣分別決定開關電晶體122、128之導 通時間’且此脈衝寬度與參考信號REF-IN和時序信號 VCO-IN之相位差成一比例關係。 舉例而言，當參考信號REF-IN和時序信號VCO-IN 同相位（in phase)時’不僅可使鎖相迴路1〇〇鎖住^ (locked)，且調升控制信號UP和調降控制信號dn具有 匹配之脈衝寬度’調升電流Ip和調降電流In也必須相 等，以維持固定之輸出電壓Vout '和固定VCO 140之頻 率振盪。 反之，當參考信號REF-IN和時序信號VCO-ΙΝ不同 相位（not in phase)時’相位偵測器11〇會改變調升控制 信號UP或調降控制信號DN之脈衝寬度，並隨之選擇 導通（turn on)電流源124或126，以改變輸出電壓v〇ut 和VCO 140之振盪頻率。 例如當時序信號VCO-IN落後(trail)參考信號reF-IN 時’調升控制信號UP之脈衝寬度將相對調降控制信號 DN增加，而此增加之脈衝寬度，亦使調升電流Ιρ和輪 出節點之充電持續期間增加’進而提高輸出電壓v〇m和 VCO 140之震盪頻率。 此外，如第2圖所示，在CMOS充電泵電路12〇中， 由於P通道電晶體處理系統供應電壓VI)E>能力較佳， 因此典型開關電晶體122和電流源124係採用一 p通道 本纸張尺度適用中國國家標準< CNS ) Λ4規柊（210X 297公处） (請先閲讀背而之注意事項再填寫本I'〕 丁 '-5 線- 427072 Λ7 Η 7 五、發明説明（3 ) 裝置（P channel device)，另由於N通道電晶體處理接地 電壓VSS能力較佳，因此典型開關電晶體128和電流源 126 係採用一 N 通道裝置（n channel device)。 在理想狀態下，電流源或充電電晶體124之導通期間 應等於調升控制信號UP之脈衝寬度，而流入節點125 以進行充電之調升電流Ip，其持續時間亦和調升控制信 號UP之週期（period)相同。同理，電流源或放電電晶體 126之導通期間應等於調降控制信號DN之脈衝寬度， 而流入節點125以進行放電之調降電流in，其持續時間 亦和調降控制信號DN之週期（period)相同。因此，輸出 電壓Vout值之增減量係精確地比例於調升控制信號UP 和調降控制信號DN之脈衝寬度。 例如當開關電晶體122依據調升控制信號UP而導通 (switch on)時，由於開關電晶體122與充電電晶體124 間之節點1電壓幾乎等於系統供應電壓VDD如5V，因 此當其（5V)與偏壓電路200所提供之閘極偏壓VBP如4V 之差超過充電電晶體124之起始電壓Vth如0.7V時，即 可導通此充電電晶體124，藉此使調升電流Ip流入輸出 節點125。 但在實際例子中，當開關電晶體122導通時，由於開 關電晶體122和充電電晶體124之接面（junction)和路徑 (route)所致之寄生電容（parasitic capacitor)C2，也同時被 充電到電壓VDD並儲存了一些寄生誤電荷（parasitic error charge)。因此，當開關電晶體122關閉（switch off) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公蝥） ---------气--^----訂I;-----線， (誚先閱讀背面L注意事項#填寫本頁) 經濟部中央標準局員工消費合作社印製 經满部中央標準局負工消費合作社印裝 d27〇^ 2 A7 _____ Η 7 五、發明説明（4 ) 時’原本應隨之關閉之充電電晶體124,以及調升電流Ip 也應停止流入輸出節點125之情形並未立即發生，其原 因在於當開關電晶體122關閉（switch off)時，儲存有寄 生誤電荷之電容C2仍舊使節點1保持在電壓Vdd左右， 故充電電晶體124並未立即關閉，且寄生誤電荷會透過 充電電晶體124而繼續流入輸出節點125，致使輸出電 壓Vout繼續增加’此等現象必須直到電容C2因持續放 電而使節點1電壓小於充電電晶體124之閘極偏壓與起 始電壓之和如4.7V(V1$VBP+Vth)，進而關閉充電電晶 體124為止。 依據上述，流入節點125之調升電流Ip，其持續時 間不僅決定於調升控制信號UP之脈衝寬度，同時也受 節點1之寄生電容C2所儲存之誤電荷影響，因此，輸 出電壓Vout值之增減量無法精確地比例於調升控制信號 UP ° 同理’由於開關電晶體128和放電電晶體126之接面 (junction)和路徑（route)所致之寄生電容（parasitic capachor)C4 ’使流出節點125之調降電流In ’其持續時 間不僅決定於調降控制信號DN之脈衝寬度，同時也受 節點2之寄生電容C4所儲存之誤電荷影響，因此，輸 出電壓Vout值之增減量也無法精確地比例於調降控制信 號DN。 其次，參照在N通道MOS類比開關之充電饋入模型 與測量一文（measurement and modeling of chargePrinted by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs -4270 7 2 at _ 13. V. Description of the invention (i) The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit capable of accurately providing up and down current pulses. According to the prior art, as disclosed in US Patent No. 5,646,563, as shown in FIG. 1, the charge pump 120 has been widely used in a phase-locked loop (PLL) 100 to control the administration. The output of the voltage controlled oscillator (VCO: voltage controlled oscillator) 140 is Vout. The output voltage Vout is basically determined by the current Ic flowing to the filter 130. The current Ic represents the difference between the rising current Ip flowing into the output node 125 and the falling current In flowing out of the output node 125. The switching transistor 122 uses To turn on or turn off the current source 124 to provide the boost current Ip, charge the node 125, and increase the output voltage value Vout 'Similarly, the switching transistor 128 is It is used to turn on or turn off the current source 126 to provide the regulated current In, discharge the node 125, and reduce the output voltage value Vout. As for the filter 130, it is used to reduce output voltage fluctuations caused by switching the rising current Ip and the falling current In. The phase comparator or phase detector 110 respectively provides an up control signal UP and a down control signal DN to control the switching action of the switching transistors 122 and 128. Among them, the phase detector 110 mainly A reference signal REF-IN 'is selected, and the clock signal VCO-IN from the voltage controlled oscillator 140 is passed through the path of a direct or frequency divider 150 to ------- -?-; ----. Order ----- line:-* (Please read the Caution Section on the back to fill in this page first) This paper size applies to Chinese National Standard (CNS) Λ4 specification (210X2 ? 7 公 #) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4270 7 2 A7 __ Η 7 ____mmm m I (2) Refer to 彳 §break REF-IN to compare its phase difference. Among them, the pulse widths of the UP control signal UP and the DN control signal DN determine the on-times of the switching transistors 122 and 128, respectively, and the pulse width is related to the reference signal REF-IN and the timing signal VCO-IN. The phase difference is proportional. For example, when the reference signal REF-IN and the timing signal VCO-IN are in phase, not only can the phase-locked loop 100 be locked (locked), but also the up control signal UP and down control The signal dn has a matching pulse width 'the rising current Ip and the falling current In must also be equal in order to maintain a fixed output voltage Vout' and a fixed VCO 140 frequency oscillation. Conversely, when the reference signal REF-IN and the timing signal VCO-ΙΝ are not in phase, the phase detector 11 will change the pulse width of the up control signal UP or down control signal DN, and choose accordingly. The current source 124 or 126 is turned on to change the output voltage vout and the oscillation frequency of the VCO 140. For example, when the timing signal VCO-IN trails the reference signal reF-IN, the pulse width of the 'up control signal UP will increase relative to the down control signal DN, and the increased pulse width also causes the up current Iρ and the wheel The charging duration of the output node is increased, thereby increasing the oscillation frequency of the output voltage v0m and VCO 140. In addition, as shown in FIG. 2, in the CMOS charge pump circuit 120, since the P-channel transistor processing system supply voltage VI) E > has better capability, the typical switching transistor 122 and the current source 124 use a p-channel. This paper size applies to Chinese National Standards < CNS) Λ4 Regulations (210X 297) (Please read the precautions before filling in this I '] Ding'-5 line-427072 Λ7 Η 7 V. Description of the invention (3) device (P channel device), and because the N-channel transistor has a better ability to handle the ground voltage VSS, a typical switching transistor 128 and current source 126 use an N-channel device. In an ideal state The conduction period of the current source or the charging transistor 124 should be equal to the pulse width of the lifting control signal UP, and the rising current Ip flowing into the node 125 for charging should also have the same duration as the period of the lifting control signal UP Same. Similarly, the conduction period of the current source or the discharge transistor 126 should be equal to the pulse width of the down-regulation control signal DN, and the duration of the down-regulation current in flowing into node 125 for discharging is also the same as the down-regulation control. The period of the signal DN is the same. Therefore, the amount of increase or decrease of the output voltage Vout is precisely proportional to the pulse width of the up control signal UP and the down control signal DN. For example, when the switching transistor 122 is based on the up control signal UP When switching on, since the voltage of node 1 between the switching transistor 122 and the charging transistor 124 is almost equal to the system supply voltage VDD, such as 5V, when its (5V) is less than the gate voltage provided by the bias circuit 200 When the difference between the voltage VBP and 4V exceeds the initial voltage Vth of the charging transistor 124 such as 0.7V, the charging transistor 124 can be turned on, so that the rising current Ip flows into the output node 125. However, in a practical example, when the switch When the transistor 122 is turned on, the parasitic capacitor C2 caused by the junction and the route of the switching transistor 122 and the charging transistor 124 is also charged to the voltage VDD and stores some parasitics. Parasitic error charge. Therefore, when the switch transistor 122 is turned off (paper off) This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 cm) --------- 气-^ ---- Order I; ----- line, (诮 read the first note on the back # Fill in this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Central Standards Bureau Off-line Consumer Cooperatives d27〇 ^ 2 A7 _____ Η 7 V. Description of the invention (4) At the time, the situation that the charging transistor 124 that should have been turned off and the rising current Ip should also stop flowing into the output node 125 did not happen immediately because the switching transistor 122 was turned off (switch off), the capacitor C2 storing the parasitic false charge still keeps the node 1 at a voltage of about Vdd, so the charging transistor 124 is not turned off immediately, and the parasitic false charge will continue to flow into the output node 125 through the charging transistor 124, causing The output voltage Vout continues to increase. 'These phenomena must be continued until the capacitor C2's voltage at node 1 is less than the sum of the gate bias voltage and the starting voltage of the charging transistor 124 due to continuous discharge, such as 4.7V (V1 $ VBP + Vth), and then closed. Until the transistor 124 is charged. According to the above, the duration of the boost current Ip flowing into the node 125 is not only determined by the pulse width of the boost control signal UP, but also affected by the false charge stored in the parasitic capacitance C2 of node 1. Therefore, the output voltage The increase or decrease cannot be accurately proportional to the control signal UP °. Similarly, the parasitic capachor C4 caused by the junction and route of the switching transistor 128 and the discharging transistor 126 is caused to flow out. The duration of the drop current In 'of the node 125 is not only determined by the pulse width of the drop control signal DN, but also affected by the false charge stored in the parasitic capacitance C4 of the node 2. Therefore, the increase or decrease of the output voltage Vout value cannot be achieved. Precisely proportional to the down control signal DN. Secondly, refer to the measurement and modeling of charge in the N-channel MOS analog switch.
本紙張尺度適用中國國家椋準（CNS ) Λ4規#, ( 2!〇x 297公ITT 計先閲讀背而之;i意事項再填寫本頁)This paper size applies to the Chinese National Standards (CNS) Λ4 规 #, (2! 〇x 297 public ITT meter read first; back to the top; i)
'IT 線* A7 Η 7 4270 7 2 五、發明説明（5 ) feedthrough in n-channel MOS analog switches :其記載 於 IEEE J. Solid-State Circuits, vol SC-20. No. 6，pp. 1206-1213, Dec. 1985.)，以及在MOS類比開關中充電注 入分析與測量一文（measurement and analysis of charge injection in MOS analog switches :其記載於 IEEE J_ Solid-State Circuits, vol SC-22. No. 2, pp. 277-281, Apr. 1987.)，可知由於脈衝饋入效應（clock feedthrough effect)，存在於開關電晶體122閘極和源極之寄生重叠 電容（overlap capacitor)Cl，於調升控制信號UP之脈衝 後緣時點，亦即在開關電晶體122關閉時，會艳注—些 電荷於寄生電容C2,使得寄生電容C2儲存之誤電荷増 加，因而流入輸出節點125之不正常電流將變得更大並 持續更久。 同樣的情形也發生在開關電晶體128閘極和源極μ， 寄生重疊電容（overlap capacitor)C3於調降控制信號 之脈衝後緣時點，亦即在開關電晶體128關閉時，會推^ 注一些電荷於寄生電容C4,使得寄生電容C4储存之誤 電荷增加，因而流出輸出節點125之不正常電流也隨之 變大並持續更久。 有鑑於此，本發明之目的係為了解決上述問題， 供一種充電泵，其利用一對除錯電晶體（debugged transistors)除去寄生電容儲存之誤電荷，以輪出正確（大 小、持續時間）的充電電流、放電電流及因此產生之輪出 電壓。 __8____ 適用中國國家標隼（CNS ) Λ4現柢（210X297公总） ~ ^ I . 、、1ΤΪ (誚先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印" 4 2 7 0 7 Λ: Η' 五、發明説明（6) 本發明之另一目的在於提供一種鎖相迴路，其將前述 充電泵提供之輸出電墨，耦合至一遽波器，並由電壓控 .·. ' 制振盈器（VCO)輸出一響應（reSp〇nse)該輸出電廢之時序 信號。 為達成上述目的’本發明提供一種鎖相迴路係包括： 一濾波器，具有一既定電壓；一電壓控制振盪器（vco)， 耦接該濾波器’其依據該濾波器之既定電壓輸出一時序 信號；一相位偵測器，耦接該時序信號和一參考信號以 進行比較，並決定輸出一第一控制信號或一第二控制信 號；及一充電泵電路’耦接該相位偵測器和該濾波器， 以依據該相位偵測器輸出之第一控制信號或第二控制信 就SX又該遽波器之既定電壓值，其包括：一偏壓電路， 用以提供一第一偏壓和一第二偏壓；一充電電晶體，其 閘極耦接該第一偏壓；一放電電晶體，其閘極耦接該第 * 二偏壓，且其汲極耦接該充電電晶體之汲極以形成一輸 出節點’其耦接該濾波器；一第一開關電晶體，一端耦 接於一第一供應電壓，另一端耦接於該充電電晶體之源 極以形成一第一節點，且其閘極耦接該第一控制信號以 控制電流是否經該充電電晶體流入該輸出節點，使該濾 波器之既定電壓值調升：一第一除錯電晶體，其汲極耦 接該充電電晶體之源極，其閘極則耦接該第一控制信號 之互補信號’以控制是否對在該第一節點上之一第一寄 生電容進行放電，並予以關閉；一第二開關電晶體，一 端耦接於一第二供應電壓，另一端耦接於該放電電晶體 令紙恨迺用中國國家榡準（CNS ) Λ4規枋（2丨0Χ 297>:Γ^Γ --------- i— -- (請先閱讀背而之注意事#填寫本頁 訂 經濟部中央樣率局貝工消費合作.杜印製 經漪部中央標率局員工消費合作社印製 427072 A? _______ 157 五、發明説明（7 ) 之源極以形成一第二節點，且其閘極耦接該第二控制信 號以控制電流是否經該放電電晶體而自該輸出節點流 出’使該濾波器之既定電壓值調降；及一第二除錯電晶 體，其汲極耦接該放電電晶體之源極，其閘極則耦接該 第二控制信號之互補信號，以控制是否對在該第二節點 上之一第二寄生電容進行放電，並予以關閉。 以下’就圖式說明本發明之鎖相迴路及充電泵電路的 實施例’其中，在不同圖示中使用相同之參考符號，係 指示相同或同義之元件。 圖式簡單說明 第1圖係顯示傳統技術中，具有充電泵之鎖相迴路方 塊圖。 第2圖係顯示一依據第1圖之傳統技術中，充電泵之 部份電路圖。 第3圖係顯示本發明之一實施例中，充電泵之部份電 路圖。 第4圖係顯示本發明之另一實施例中，充電泵之部份 電路圖。 第5圖係顯示本發明之另一實施例中，調升信號和調 降信號之互補信號產生器電路圖。 第6A圖係顯示傳統充電泵之調降電流In(t)曲線。 第6B圖係顯示本發明充電泵之調降電流In⑴線。 第6C圖係顯示調降控制信號DN之脈衝電壓V(t) 曲線。 _ 10 本紙張尺度適用中國國家標隼（CNS ) Λ4規枋（210x 297公 I--] n -------i·,---- { I--1 T______1 ^ 1 g» -'V吞 髮 (请先M讀背面之注意事項#填涔本貫) 經濟部中央標準局員工消費合作社印裝 Λ7 B7 五、發明説明（）8 第7A圖係顯示傳統充電泵之調升電流Ip⑴曲線β 第7Β圖係顯示本發明充電泵之調升電流Ιρ⑴曲 線。-' 第7C圖係顯示調升控制信號up之脈衝電壓V⑴曲 線。 [符號說明] 100〜鎖相迴路；Π0〜相位偵測器；120〜充電泵；130， 230〜濾波器；140〜電壓控制振盪器；15〇〜除頻器；2〇〇， 300〜偏壓電路；510 ’ 520〜互補信號產生器；122，222〜 開關電晶體；124 ’ 224〜充電電晶體；126，226〜放電電 晶體；128，228〜開關電晶體；125，225〜輸出節點；C1， C2，C3 ’ C4〜寄生電容；242 ’ 244〜除錯電晶體；5U，513， 514〜反相器；512~傳輸閘；52卜523，524〜反相器；522〜 傳輸閘。 實施例 請參閱第3圖，其顯示本發明充電泵之—實施例，其 包括如下元件。 首先一偏壓電路（bias circuit)300係用以提供一第一 偏壓VBP和一第二偏壓VBN。其次，一充電電晶體224， 其閘極耦接第一偏壓VBP，且在源極所在位置之節點3 上之一寄生電容C2 ’係儲存有一第一寄生誤電荷。至於 對應之放電電晶體226，其閘極耦接第二偏壓VBN，且 在源極所在位置之節點6上之一寄生電容C4,係儲存有 一第二寄生誤電荷。另外放電電晶體226之汲極耦接充 ______ 11 本紙張尺度適用中國國家榇準（CNS〉Λ4現枱（210X297公# ) H ! I---US- ---I n n τ _______ _ I I ("先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 4270 7 2 五'發明説明（9) ' 電電晶體224之及極以形成一輸出節點225。 另外一第一開關電晶體222 端叙接於第一供應電 壓=D，另-端_於充電電晶體以之源極以形成一 第一即點3，且其閘極耦接一第一控制信號up以控制電 流Ip是否經充電電晶體224流入輸出節點225，而一第 一除錯電晶體242,其汲極耦接充電電晶體224之源極， 其閘極職接第-控制信號UP之互補信冑刪，用以 控制是否對存於寄生電容C2《第—寄生誤電荷形成放 電路徑’並關閉充電電晶體224。 同理，一第二開關電晶體228，一端耦接於第二供應 電壓VSS’另-端耗接於放電電晶體226之源極以形成 一第一節點6，且其閘極耦接一第二控制信號DN以控 制電流In是否經放電電晶體226而自輸出節點225流 出，而一第二除錯電晶饉244，其汲極耦接放電電晶體 226之源極，其閘極則耦接第二控制信號DN之互補信 號DNB，用以控制是否對存於寄生電容C4之第二寄生 誤電荷形成放電路徑，並關閉放電電晶體226。 舉例而言，充電泵220可於輪出節點225提供一輸出 電壓Vom予外部裝置，例如鎖相迴路中之電壓控制振盪 器（VCO)’以控制VCO 440產生之時序信號CKi頻率， 其中輸出電壓Vout之變化係依注入節點225之調升電流 Ip與流出節點225之調降電流In之差電流Ic決定，此 外’於節點225之位置進行調升電流lp或調降電流匕 之切換時，透過濾波器，可以平滑輸出電壓¥〇以之波形， _____ 12 本紙張尺度剌中國國家操华（CNS ) Λ4規将（210 \297公释) ------- (鄣先閱讀背面之注意事項再填寫本頁) I- 遴 270 Ή 經濟部中央標準局員工消費合作社印^ Α7 Β7五、發明説明（10 ) 如選擇一低通慮波器（low pass filter)230，其含有一電阻 R1、電容C5和C6，由於以濾波器平滑波形為一習知技 術，ϋ不予贅述。 此外，時序信號CK能選擇經過除頻器（frequency divider)或直接耗接到相位偵測器410，形成輸入信號 VCO-IN，其可指示VCO 440之操作頻率。相位偵測器410 另輕接一參考信號，例如從具有外頻（external crystal)之 振盪器（未顯示）中選擇一參考信號REF-IN，以與輸入信 號VCO-IN進行比較，並藉此輸出一控制信號，其中當 時序信號VCO-IN為相位領先者，輸出一調降控制信號 DN，當時序信號為相位落後者，則輸出一調升控制信號 UP。 至於偏壓電路係為一傳統技術，熟習此技藝者當可置 換其他等效結構，例如偏壓電路300主要係提供一第一 偏壓VBP與充電電晶體224之閘極，並提供一第二偏壓 VBN與放電電晶體226之閘極，其中，P通道電晶體322、 332之閘極接地，汲極耦接系統電壓VDD，以隨時保持 導通狀態，同理N通道電晶體328之閘極耦接系統電壓 VDD，汲極耦接電路接地VSS，以隨時保持導通狀態。 此外，在偏壓電路300部份，P通道電晶體322、324 和N通道電晶體326、328係分別與開關電晶體222、充 電電晶體224、開關電晶體226、充電電晶體228具有相 同之類型（type)和既定比例之尺寸大小（dimensions)。 接著，P通道電晶體324和充電電晶體224之閘極耦 13 ---------^------訂 I ------腺— (請先閱讀背而之注意事^再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公释） 4 270 7 2 經濟部中央標準局員工消費合作社印裂 A7 B7 五、發明説明（u ) 接到P通道電晶體334之閘極，且p通道電晶體334之 閘極另與其汲極一起耦接，因此，通過P通道電晶體324 之電流II和通過充電電晶體224之調升電流Ip係鏡射 (mirror)參考電流產生器340產生之參考電流IREP，其次， N通道電晶體326之閘極係耦接其汲極及N通道放電電 晶體226之閘極，因此，通過放電電晶體226之調降電 流In即鏡射通過N通道電晶體326之電流II，另由於P 通道電晶體324與N通道電晶體326之串聯關係，故亦 導引相同之電流II。同時，偏壓電路300分別在充電電 晶體224之閘極產生偏壓VBP，以及在放電電晶體226 之閘極產生偏壓VBN。 另P通道充電電晶體224,其汲極係耦接N通道放電 電晶體之汲極以形成一輸出節點225,其耦接至濾波器 230 = 如先前技術背景所述，調升開關電晶體222，串接於 供應電壓VDD和充電電晶體224之源極間，其閘極則 耦接調升控制信號UP以控制調升電流Ip是否經充電電 晶體224流入輸出節點225 *進而使濾波器230之既定 輸出電壓值Vout調升。 然而’由於在節點3上之寄生電容（parasitic capacitor)C2 ’儲存了寄生誤電荷（parasitic error charge)， 因此’當開關電晶體222關閉（switch off)時，原本應隨 之關閉之充電電晶體224，以及調升電流Ip也應停止流 入輸出節點225之情形並未立即發生，換句話說，充電 本紙張尺度適用中國國家標隼（CNS ) Λ4規栝（2IOX 297公赞 ^-- (請先閱讀背面之-注項再填寫本頁) -s A7 4270 7 2 B7 五、發明说明（12 ) 電晶體224並未立即關閉，且寄生誤電荷也透過充電電 晶體224而繼續流入輸出節點225，致使輸出電壓Vout 繼續增如。 本發明之實施例則另利用一 P通道除錯電晶體242， 透過節點3，其汲極耦接充電電晶體224之源極，其閘 極則耦接調升控制信號UP之互補信號UPB，其源極則 透過節點5連接一偏壓VBP2，用以當互補信號UPB導 通P通道除錯電晶體242時，對在節點3上之寄生電容 C2形成放電路徑，並迅速關閉充電電晶體224 ^ 同理，調降開關電晶體228，串接於接地電壓VSS和 放電電晶體226之源極間，其閘極則耦接調降控制信號 DN以控制調降電流In是否經放電電晶體226流出輸出 節點225，進而使濾波器230之既定輸出電壓值Vout調 降。 經濟部中央標隼局貝工消費合作社印裂 然而，由於在節點6上之寄生電容（parasitic capacitor)C4 ’儲存了寄生誤電荷（parasitic error charge)。 因此，當開關電晶體228關閉（switch off)時，原本應隨 之關閉之放電電晶體226，以及調降電流In也應停止流 入輪出節點225之情形並未立即發生，換句話說，玫電 電晶體226並未立即關閉，且寄生誤電荷經由放電電晶 體226而繼續流出輸出節點225，致使輸出電壓Vout繼 續減少。 本發明之實施例則另利用一 N通道除錯電晶艎244， 透過節點6，其汲極耦接放電電晶體226之源極，其閘 本纸張尺度適财ϋ时縣（CNS)峨格（训心祕免） 4270 7 2 A7 1Π 五、發明説明（13 ) 極則耦接調降控制信號DN之互補信號DNB，其源極則 透過節點8連接一偏壓VBN2，用以當互補信號DNB導 通N通道除錯電晶體244時’對節點6存在之寄生電容 形成放電路徑，並迅速關閉放電電晶體226。 請參閱第4圖其顯示本發明之另一實施例，p通道 除錯電晶體242和N通道除錯電晶體244之源極偏壓 VBP2和VBN2可選擇另連接一偏壓電路，或者使用同 一偏壓電路300，而透過節點5’、8,分別耗接到偏壓VBP 和VBN ’如此，可節省功率消耗和晶片使用面積。 請參閱第5圖’其顯示本發明之另一實施例中，調升 信號UP和調降信號DN之互補信號產生器電路51〇、520 圖。例如透過產生器電路510之串聯反閘511、513可輸 出調升信號UP’而透過反閘514則可輸出互補調升信號 UPB’其中為配合兩者之遲延時間，另形成一傳輸閘512 於產生器電路510中。 同理’透過產生器電路520之串聯反閘521、523可 輸出調降信號DN’而透過反閘524則可輸出互補調降 信號DNB，其中為配合兩者之遲延時間，另形成一傳輸 閘522於產生器電路520中。 請參閱第6A-6C圖之比較，首先依據第6C圖，其 顯示調降控制信號DN之脈衝電壓V⑴曲線，其中，在 傳統充電泵中，由於流出節點125之調降電流In，其持 續時間不僅決定於調降控制信號DN之脈衝寬度，同時 也受寄生電容C3、C4儲存之誤電荷影響，因此，如第 ________16 本紙張尺度適用中國國家榡準（CNS ) Λ4規格（210X2^7公筇） I — - ---Γ__— 才 T ------ I T _ ί - ϋ I _ ^ l (請先閲讀背面之注意事項再填寫本頁) 經漓部中央標隼局員工消費合作社印製 經濟部中央標準局員工消費合作社印聚 4270 7 2 A7 ___________137 ____ 五、發明説明（14) 6A圖顯示之傳統充電泵之調降電流in(t)曲線，並無法 精確地響應調降控制信號DN。 反之’在本發明之實施例中，由於利用一 N通道除 錯電晶體244使節點6上之寄生電容C4形成放電路徑， 並迅速關閉放電電晶體226 ’因此，如第6B圖顯示之調 降電流In(t)曲線’可精確地響應調降控制信號DN。 同理’請參閱第7A-7C圖之比較，首先依據第7C 圖’其顯示調升控制信號UP之脈衝電壓v⑴曲線，其 中’在傳統充電泵中’由於流入節點125之調升電流ip， 其持續時間不僅決定於調升控制信號UP之脈衝寬度， 同時也受寄生電容C1、C2儲存之誤電荷影響，因此， 如第7A圖顯示之傳統充電泵之調升電流Ip⑴曲線，並 無法精確地響應調升控制信號UP。 反之’在本發明之實施例中，由於利用一 p通道除 錯電晶體242使在節點3上之寄生電容C2形成放電路 徑，並迅速關閉充電電晶體224，因此，如第7B圖顯示 之調升電流Ip⑴曲線，可精確地響應調升控制信號up。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之 精神和範圍内’當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 _____Γ7'IT line * A7 Η 7 4270 7 2 V. Description of the invention (5) feedthrough in n-channel MOS analog switches: It is described in IEEE J. Solid-State Circuits, vol SC-20. No. 6, pp. 1206- 1213, Dec. 1985.), and a measurement and analysis of charge injection in MOS analog switches: documented in IEEE J_ Solid-State Circuits, vol SC-22. No. 2 , pp. 277-281, Apr. 1987.), it can be seen that due to the clock feedthrough effect, the parasitic overlap capacitor Cl existing in the gate and source of the switching transistor 122 is used for the lift control. The timing of the trailing edge of the pulse of the signal UP, that is, when the switching transistor 122 is turned off, some charges will be injected into the parasitic capacitor C2, causing the false charge stored in the parasitic capacitor C2 to increase, so the abnormal current flowing into the output node 125 will change. Be bigger and last longer. The same situation also occurs at the gate and source μ of the switching transistor 128, and the parasitic overlap capacitor C3 is at the trailing edge of the pulse of the down control signal, that is, when the switching transistor 128 is turned off, it will push ^ Note Some charges in the parasitic capacitor C4 increase the false charges stored in the parasitic capacitor C4, so the abnormal current flowing out of the output node 125 also increases and lasts longer. In view of this, the object of the present invention is to solve the above problems, and provide a charge pump that uses a pair of debugged transistors to remove the false charges stored by the parasitic capacitors in order to rotate out the correct (size, duration) Charge current, discharge current, and the resulting output voltage. __8____ Applicable to China National Standards (CNS) Λ4 now (210X297 total) ~ ^ I., 1T (诮 Please read the notes on the back before filling this page) Printed by the Consumers' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs " 4 2 7 0 7 Λ: Η 'V. Description of the invention (6) Another object of the present invention is to provide a phase-locked loop, which couples the output electric ink provided by the aforementioned charge pump to a wave filter and is controlled by a voltage ... 'The VCO outputs a response (reSpOnse) timing signal of the output electrical waste. To achieve the above objective, the present invention provides a phase-locked loop system including: a filter having a predetermined voltage; a voltage controlled oscillator (vco) coupled to the filter; and outputting a timing based on a predetermined voltage of the filter. A signal; a phase detector coupled to the timing signal and a reference signal for comparison and determining to output a first control signal or a second control signal; and a charge pump circuit 'coupled to the phase detector and The filter, based on the first control signal or the second control signal output by the phase detector, has a predetermined voltage value for SX and the waver, and includes a bias circuit for providing a first bias. Voltage and a second bias; a charging transistor whose gate is coupled to the first bias; a discharging transistor whose gate is coupled to the * second bias and whose drain is coupled to the charging circuit The drain of the crystal forms an output node, which is coupled to the filter; a first switching transistor, one end of which is coupled to a first supply voltage, and the other end of which is coupled to the source of the charging transistor to form a first A node, and its gate is coupled to the A control signal to control whether a current flows into the output node through the charging transistor, so that a predetermined voltage value of the filter is raised: a first error-correcting transistor whose drain is coupled to a source of the charging transistor, and The gate is coupled to the complementary signal of the first control signal to control whether a first parasitic capacitor on the first node is discharged and turned off; a second switching transistor, one end of which is coupled to a first Two supply voltages, and the other end is coupled to the discharge transistor to make the paper use the Chinese National Standard (CNS) Λ4 gauge (2 丨 0Χ 297 >: Γ ^ Γ --------- i—- -(Please read the back of the first thing to note #Fill in this page to order the shellfish consumer cooperation of the Central Sample Rate Bureau of the Ministry of Economic Affairs. Du printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperative of the Central Standards Bureau. (7) a source electrode to form a second node, and a gate thereof coupled to the second control signal to control whether a current flows from the output node through the discharge transistor, so as to reduce a predetermined voltage value of the filter ; And a second error-correcting transistor whose drain is coupled to the discharge The source of the transistor, and its gate is coupled to the complementary signal of the second control signal to control whether a second parasitic capacitor on the second node is discharged and closed. The embodiment of the phase-locked loop and the charge pump circuit of the present invention, wherein the same reference symbols are used in different diagrams to indicate the same or synonymous components. Brief Description of the Drawings Figure 1 shows the conventional technology with charging Block diagram of the phase locked loop of the pump. Fig. 2 is a circuit diagram of a charge pump in the conventional technology according to Fig. 1. Fig. 3 is a circuit diagram of a charge pump in an embodiment of the present invention. Fig. 4 is a circuit diagram of a part of a charge pump in another embodiment of the present invention. Fig. 5 is a circuit diagram of a complementary signal generator of a rise signal and a down signal in another embodiment of the present invention. Figure 6A is a curve showing the decrease current In (t) of a conventional charge pump. FIG. 6B is a diagram showing a regulated current In⑴ line of the charge pump of the present invention. Fig. 6C shows the curve of the pulse voltage V (t) of the down-control signal DN. _ 10 This paper size applies Chinese National Standard (CNS) Λ4 Regulation (210x 297 male I--] n ------- i ·, ---- {I--1 T______1 ^ 1 g »- 'V Swallow Fat (please read the notes on the back first # fill in the original) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of the invention () 8 Figure 7A shows the rising current of the traditional charge pump Ip⑴ curve β Figure 7B shows the rising current Iρ⑴ curve of the charge pump of the present invention.-'Figure 7C shows the pulse voltage V⑴ curve of the rising control signal up. [Symbol] 100 ~ Phase-Locked Loop; Π0 ~ Phase Detector; 120 ~ charge pump; 130, 230 ~ filter; 140 ~ voltage controlled oscillator; 150 ~ frequency divider; 200, 300 ~ bias circuit; 510 '520 ~ complementary signal generator; 122,222 ~ switching transistor; 124 '224 ~ charging transistor; 126,226 ~ discharging transistor; 128,228 ~ switching transistor; 125,225 ~ output node; C1, C2, C3' C4 ~ parasitic capacitance; 242 '244 ~ Error-correcting transistor; 5U, 513, 514 ~ Inverter; 512 ~ Transmission gate; 52 ~ 523, 524 ~ Inverter; 522 ~ Transmission For an embodiment, please refer to FIG. 3, which shows an embodiment of the charge pump of the present invention, which includes the following components. First, a bias circuit 300 is used to provide a first bias VBP and a second Bias VBN. Second, a charging transistor 224, whose gate is coupled to the first bias VBP, and a parasitic capacitance C2 'on node 3 where the source is located stores a first parasitic error charge. As for the corresponding The gate of the discharge transistor 226 is coupled to the second bias voltage VBN, and a parasitic capacitance C4 on the node 6 where the source is located stores a second parasitic error charge. In addition, the drain of the discharge transistor 226 Coupling charge ______ 11 This paper size is applicable to China's national standard (CNS> Λ4 current station (210X297 公 #) H! I --- US ---- I nn τ _______ _ II (" Read the note on the back first Please fill in this page for further information) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4270 7 2 Five 'Invention Description (9)' Transistor 224 sums up to form an output node 225. Another first switching transistor 222 Connected to the first supply voltage = D, the other-terminal _ to the charging transistor to The source is to form a first point 3, and its gate is coupled to a first control signal up to control whether the current Ip flows into the output node 225 through the charging transistor 224, and a first error-correcting transistor 242, which draws The pole is coupled to the source of the charging transistor 224, and its gate is connected to the complementary signal of the first-control signal UP, which is used to control whether the parasitic capacitance C2 "the parasitic mischarge forms a discharge path 'and turns off the charging. Transistor 224. Similarly, a second switching transistor 228 has one end coupled to the second supply voltage VSS 'and the other end connected to the source of the discharge transistor 226 to form a first node 6, and its gate is coupled to a first Two control signals DN are used to control whether the current In flows from the output node 225 through the discharge transistor 226, and a second error-correcting transistor 244 whose drain is coupled to the source of the discharge transistor 226 and whose gate is coupled The complementary signal DNB connected to the second control signal DN is used to control whether a discharge path is formed for the second parasitic false charge stored in the parasitic capacitor C4, and the discharge transistor 226 is turned off. For example, the charge pump 220 may provide an output voltage Vom at an output node 225 to an external device, such as a voltage-controlled oscillator (VCO) 'in a phase-locked loop to control the frequency of the timing signal Cki generated by the VCO 440, where the output voltage The change of Vout is determined by the difference current Ic between the rising current Ip injected into the node 225 and the falling current In flowing out of the node 225. In addition, when the switching of the rising current lp or the falling current d at the position of node 225 The filter can smooth the waveform of the output voltage ¥ 〇, _____ 12 This paper size: China National Standards (CNS) Λ4 gauge (210 \ 297 public release) ------- (鄣 Please read the note on the back first Please fill in this page again) I- Lin 270 印 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs ^ Α7 Β7 V. Invention Description (10) If a low pass filter 230 is selected, it contains a resistor R1 Capacitors C5 and C6, since filter smoothing is a known technique, will not be repeated here. In addition, the timing signal CK can be selected through a frequency divider or directly connected to the phase detector 410 to form an input signal VCO-IN, which can indicate the operating frequency of the VCO 440. The phase detector 410 is further connected to a reference signal. For example, a reference signal REF-IN is selected from an oscillator (not shown) with an external frequency to compare with the input signal VCO-IN and thereby A control signal is output. When the timing signal VCO-IN is a phase leader, a down control signal DN is output. When the timing signal is a phase behind, a up control signal UP is output. As for the bias circuit is a traditional technology, those skilled in the art can replace other equivalent structures. For example, the bias circuit 300 mainly provides a gate of the first bias VBP and the charging transistor 224, and provides a The second bias voltage VBN and the gate of the discharge transistor 226, among which the gates of the P-channel transistors 322 and 332 are grounded, and the drain is coupled to the system voltage VDD to maintain the on-state at any time. Similarly, the N-channel transistor 328 The gate is coupled to the system voltage VDD, and the drain is coupled to the circuit ground VSS to maintain the on-state at any time. In addition, in the bias circuit 300 section, the P-channel transistors 322, 324 and N-channel transistors 326, 328 are the same as the switching transistor 222, the charging transistor 224, the switching transistor 226, and the charging transistor 228, respectively. Type (type) and dimensions (dimensions) of a given proportion. Next, the gate coupling of the P-channel transistor 324 and the charging transistor 224 13 --------- ^ ------ Order I ------ Gland— (Please read the back Attention ^ Please fill in this page again) This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 public release) 4 270 7 2 Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs printed A7 B7 V. Description of invention (u) To the gate of P-channel transistor 334, and the gate of p-channel transistor 334 is also coupled with its drain. Therefore, the current II through P-channel transistor 324 and the rising current Ip through charging transistor 224 are The reference current IREP generated by the mirror reference current generator 340. Secondly, the gate of the N-channel transistor 326 is coupled to its drain and the gate of the N-channel discharge transistor 226. Therefore, through the discharge transistor 226 The reduced current In is the current II mirrored through the N-channel transistor 326, and because of the series relationship between the P-channel transistor 324 and the N-channel transistor 326, the same current II is also guided. At the same time, the bias circuit 300 generates a bias VBP at the gate of the charge transistor 224 and a bias VBN at the gate of the discharge transistor 226, respectively. In addition, the P-channel charging transistor 224 has a drain coupled to the drain of the N-channel discharging transistor to form an output node 225, which is coupled to the filter 230. As described in the previous technical background, the switching transistor 222 is raised , Connected in series between the supply voltage VDD and the source of the charging transistor 224, and its gate is coupled to the rising control signal UP to control whether the rising current Ip flows into the output node 225 through the charging transistor 224 * and then makes the filter 230 The predetermined output voltage value Vout rises. However, 'the parasitic capacitor C2 on node 3' stores a parasitic error charge. Therefore, when the switching transistor 222 is switched off, the charging transistor which should have been turned off with it 224, and the situation that the rising current Ip should also stop flowing into the output node 225 did not happen immediately. In other words, the Chinese paper standard (CNS) Λ4 regulations (2IOX 297 public praise ^-(Please Read the note on the back first, then fill out this page) -s A7 4270 7 2 B7 V. Description of the invention (12) Transistor 224 is not immediately turned off, and the parasitic error charge continues to flow into the output node 225 through the charging transistor 224 As a result, the output voltage Vout continues to increase. In the embodiment of the present invention, a P-channel error-correcting transistor 242 is used. Through node 3, its drain is coupled to the source of the charging transistor 224, and its gate is coupled to the regulator. The complementary signal UPB of the rising control signal UP is connected to a bias voltage VBP2 through the node 5 to form a discharge circuit for the parasitic capacitance C2 on the node 3 when the complementary signal UPB turns on the P-channel error-correcting transistor 242. In the same way, the charging transistor 224 is switched off quickly. In the same way, the switching transistor 228 is lowered and connected in series between the ground voltage VSS and the source of the discharging transistor 226, and the gate is coupled to the lowering control signal DN to control the regulating Does the falling current In flow out of the output node 225 through the discharge transistor 226, thereby lowering the predetermined output voltage value Vout of the filter 230. However, due to the parasitic capacitance at node 6 due to the parasitic capacitance at node 6 (Parasitic capacitor) C4 'stores a parasitic error charge. Therefore, when the switching transistor 228 is switched off, the discharging transistor 226 that should have been turned off and the regulated current In should also stop. The situation of flowing into the round-out node 225 does not happen immediately, in other words, the Mei transistor 226 is not immediately turned off, and the parasitic error charge continues to flow out of the output node 225 through the discharge transistor 226, so that the output voltage Vout continues to decrease. In the embodiment, an N-channel error-correcting transistor 244 is used. Through the node 6, its drain is coupled to the source of the discharge transistor 226. Yanshi County (CNS) Ege (Mind training) 4270 7 2 A7 1Π V. Description of the invention (13) The pole is coupled to the complementary signal DNB of the down-regulation control signal DN, and its source is connected to a bias via node 8. Pressing VBN2 is used to form a discharge path for the parasitic capacitance existing at node 6 when the complementary signal DNB turns on the N-channel error-correcting transistor 244, and quickly close the discharge transistor 226. Please refer to FIG. 4, which shows another embodiment of the present invention. The source bias voltages VBP2 and VBN2 of the p-channel error-correcting transistor 242 and the N-channel error-correcting transistor 244 can be connected to another bias circuit or can be used. The same bias circuit 300 is consumed by the bias voltages VBP and VBN 'through the nodes 5' and 8, respectively, so that power consumption and chip use area can be saved. Please refer to FIG. 5 ', which shows the complementary signal generator circuits 51o and 520 of the up signal UP and the down signal DN in another embodiment of the present invention. For example, through the series reverse gates 511 and 513 of the generator circuit 510, the boost signal UP 'can be output, and through the reverse gate 514, the complementary boost signal UPB' can be output. Among them, a transmission gate 512 is formed to match the delay time of the two. Generator circuit 510. In the same way, through the series anti-gates 521 and 523 of the generator circuit 520, the down-regulation signal DN can be output, and through the anti-gate 524, the complementary down-signal signal DNB can be output. In order to match the delay time of the two, another transmission gate is formed 522 is in the generator circuit 520. Please refer to the comparison of Figs. 6A-6C. First, according to Fig. 6C, it shows the pulse voltage V⑴ curve of the down control signal DN. Among conventional charge pumps, due to the down current In flowing out of node 125, its duration It is not only determined by the pulse width of the control signal DN, but also affected by the false charges stored in the parasitic capacitors C3 and C4. Therefore, as per ________16, this paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X2 ^ 7mm)筇) I —---- Γ __— 才 T ------ IT _ ί-ϋ I _ ^ l (Please read the notes on the back before filling this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4270 7 2 A7 ___________137 ____ V. Description of the Invention (14) The curve of the reduction current in (t) of the traditional charge pump shown in Figure 6A cannot accurately respond to the reduction control Signal DN. Conversely, in the embodiment of the present invention, because an N-channel error-correcting transistor 244 is used to make the parasitic capacitance C4 on node 6 form a discharge path, and the discharge transistor 226 is quickly turned off, therefore, the adjustment is shown in FIG. 6B The current In (t) curve 'can accurately respond to the down control signal DN. Similarly, please refer to the comparison of Figs. 7A-7C. First, according to Fig. 7C, it shows the pulse voltage v⑴ curve of the rising control signal UP, where 'in a traditional charge pump' because of the rising current ip flowing into the node 125, Its duration is not only determined by the pulse width of the lifting control signal UP, but also affected by the false charges stored in the parasitic capacitors C1 and C2. Therefore, the lifting current Ip⑴ curve of the conventional charge pump as shown in Figure 7A is not accurate Ground responds to the rising control signal UP. On the contrary, in the embodiment of the present invention, since a p-channel error-correcting transistor 242 is used to form a parasitic capacitor C2 on node 3 to form a discharge path, and the charging transistor 224 is quickly turned off, the adjustment as shown in FIG. 7B The rising current Ip⑴ curve can accurately respond to the rising control signal up. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. _____ Γ7
TcNS ) Λ4規格（2丨0X297公费) " -------I (請先閱讀背面之注意事項再填舄本頁)TcNS) Λ4 specification (2 丨 0X297 public fee) " ------- I (Please read the precautions on the back before filling this page)