經濟部智慧財產局員工消費合作衽印製 427062 5〇94twf.doc/o〇6 A7 _ B7 五、發明說明（/) 本發明是有關於一種啓動電路，且特別是有關於一 種省電型啓動電路。 請參照第1圖，其所繪示爲習知啓動電路繪示圖。一 般電流源或者參考電壓之類的應用電路系統中所使用的啓 動電路（stm-up circuit) 10，都是採用一個較弱（weak ) 的PMOS電晶體20 (其W/L<<1 )，串聯一個較強（strong) 的NM0S電晶體30 (其W/L>>1 )。而PM0S電晶體20的 閘極連接至Vss (低電壓源），使其永遠保持在導通（turn-on)的狀態。當系統電源開啓時，A點的電壓協助應用系 統40進入正常的工作狀態，然而，當應用系統40正常動 作後，應用系統40會升高NM0S電晶體30閘極至設計的 工作電壓，使得NM0S電晶體30變成導通狀態，並且以 此狀態維持下去。而由於PM0S電晶體20與NM0S電晶 體30同時保持在導通狀態，造成電流在V„-PM0S-NM0S-路徑上的持續導通，導致電源功率的浪費。 在而一般的應用系統30電路中，會包括具有二個工 作狀態（初始狀態與未狀態，initial state與final state) 的電路稱之爲參考電路42，例如能隙電壓參考（bandgap v〇ltage reference)電路或者負回授（negative feedback)電 路，其必須藉助啓動電路10才能夠使參考電路42脫mm 姶狀態並到達末狀態，而一旦參考電路42到達末狀態時’ 啓動電路10與應用系統40之間的連接將會自行切斷’医1 此不會影響應用系統本身的穩定性與可靠性。但S啓動電 路10本身並不會變成關閉狀態，所以會有電源功 ------------r --------訂---------線') (請先閱讀背面之注意事項再填寫本頁) 3 經濟部智慧財產局員工消費合作社印製 427062 50 94 twf , doc / 006 A7 __B7_ 五、發明說明（之） 費。 因此本發明係提供一種省電型啓動電路，包括有電 源開啓自動重置電路，其會在應用系統到達正常運作時關 閉PM0S使得啓動電路不會有電源功率的浪費。 本發明係提供一種省電型啓動電路，包括有控制電 路，其會在應用系統到達正常運作時關閉啓動電路與應用 電路之間的連接。 本發明提出一種省電型啓動電路，其簡述如下： 電源開啓自動重置電路其在電源動作時提供開啓訊 號，並經過特定時間之後將開啓訊號更改爲關閉訊號。啓 動電路，耦接至應用系統與電源開啓自動重置電路，並根 據開啓訊號來開啓該啓動電路，並送出啓動電路開啓訊 號，而根據關閉訊號來關閉啓動電路，最後應用系統在到 達正常工作狀態後產生應用系統訊號，在啓動電路接收到 應用系統訊號時將啓動電路開啓訊號更改爲啓動電路關閉 訊號。控制電路，耦接於啓動電路與應用系統之間，根據 所接收之啓動電路開啓訊號，送出參考訊號至應用系統， 根據所接收之啓動電路關閉訊號，停止控制電路與應用系 統之間的訊號傳遞。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1圖其所繪示爲習知啓動電路繪示圖； 4 (請先閱讀背面之';t意事項再填寫本頁) 裝--------訂---------線 本紙張尺度適闬中國國家標準（CNS>A4規格（21ϋχ 297公釐） 經濟部智慧財產局員工消費合作社印製 427062 5094twf.doc/006 Λί _Β7 五、發明說明（g ) 第2圖其所繪示爲本發明省電型啓動電路繪示圖繪 示；以及Printed by the Consumer Property Cooperation Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs 427062 5〇94twf.doc / o〇6 A7 _ B7 V. Description of the Invention (/) The invention relates to a startup circuit, and in particular to a power-saving startup Circuit. Please refer to FIG. 1, which shows a conventional start-up circuit. The start-up circuit (stm-up circuit) 10 used in an application circuit system such as a general current source or a reference voltage uses a weak PMOS transistor 20 (whose W / L < < 1) A strong NMOS transistor 30 (whose W / L > > 1) is connected in series. The gate of the PMOS transistor 20 is connected to Vss (low voltage source), which keeps it in a turn-on state forever. When the system power is turned on, the voltage at point A assists the application system 40 to enter the normal working state. However, when the application system 40 operates normally, the application system 40 will raise the gate of the NMOS transistor 30 to the designed operating voltage, making NMOS The transistor 30 is turned on, and is maintained in this state. And because the PM0S transistor 20 and the NM0S transistor 30 remain in the on state at the same time, the current is continuously conducted on the V „-PM0S-NM0S- path, resulting in a waste of power. In the general application system 30 circuit, A circuit including two working states (initial state and non-state, initial state and final state) is called a reference circuit 42, such as a bandgap voltage reference circuit or a negative feedback circuit. The reference circuit 42 can be brought out of the mm state and reached the end state by means of the start circuit 10, and once the reference circuit 42 reaches the end state, the connection between the start circuit 10 and the application system 40 will be cut off by itself. 1 This will not affect the stability and reliability of the application system itself. However, the S start circuit 10 itself will not turn off, so there will be power work ------------ r ---- ---- Order --------- Line ') (Please read the notes on the back before filling this page) 3 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 427062 50 94 twf, doc / 006 A7 __B7_ V. Explanatory Notes (of) Fees. Therefore, the present invention provides a power-saving startup circuit including a power-on automatic reset circuit, which will turn off the PM0S when the application system reaches normal operation so that the startup circuit will not waste power. A start-up circuit includes a control circuit that closes the connection between the start-up circuit and the application circuit when the application system reaches normal operation. The present invention provides a power-saving start-up circuit, which is briefly described as follows: Power-on automatic reset circuit It provides an on signal when the power is on, and changes the on signal to a off signal after a certain period of time. The start circuit is coupled to the application system and the power on automatic reset circuit, and the start circuit is turned on according to the on signal and sent out The startup circuit turns on the signal, and the startup circuit is turned off according to the shutdown signal. Finally, the application system generates an application system signal after reaching the normal working state. When the startup circuit receives the application system signal, it changes the startup circuit on signal to the startup circuit off signal. Control Circuit, coupled to start-up circuit Between application systems, a reference signal is sent to the application system according to the received start-up signal, and a signal is closed according to the received start-up circuit, and the signal transmission between the control circuit and the application system is stopped. The features, advantages and advantages can be more obvious and easy to understand. The preferred embodiments are described below in conjunction with the accompanying drawings, and are described in detail as follows: Brief description of the drawings: Figure 1 shows a conventional startup circuit. Figure; 4 (Please read the '; notice on the back before filling in this page) Loading -------- Order --------- The size of thread paper is suitable for Chinese National Standards (CNS > A4 specification (21ϋχ 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 427062 5094twf.doc / 006 Λί _Β7 V. Description of the invention (g) Figure 2 shows the power-saving start circuit of the invention Drawing; and
第3圖其所繪示爲本發明省電型開啓電路之較佳實施 例繪示圖E 標號說明： 10、丨10啓動電路 20 ' 120 PMOS 電晶體 30 ' 130 NMOS 電晶體 40、140應用系統 42、142參考電路 200電源開啓自動重置電路 210 ' 220 ' 330 ' 340 PMOS 230 ' 240 ' 250 ' 350 ' 360 NMOS 260、270、280、310、320 反相器 290切換開關 300控制電路 實施例 請參照第2圖，其所繪示爲本發明省電型啓動電路繪 示圖。本發明之省電型啓動電路100耦接至應用電路140 中之參考電路142，包括電源開啓自動重置電路200、啓 動電路110與控制電路300。FIG. 3 shows a preferred embodiment of the power-saving start-up circuit of the present invention. E Symbol description: 10, 10 start-up circuit 20 '120 PMOS transistor 30' 130 NMOS transistor 40, 140 application system 42, 142 Reference circuit 200 Power on automatic reset circuit 210 '220' 330 '340 PMOS 230' 240 '250' 350 '360 NMOS 260, 270, 280, 310, 320 Inverter 290 selector switch 300 control circuit embodiment Please refer to FIG. 2, which is a diagram illustrating a power-saving startup circuit of the present invention. The power-saving startup circuit 100 of the present invention is coupled to the reference circuit 142 in the application circuit 140 and includes a power-on automatic reset circuit 200, a startup circuit 110, and a control circuit 300.
啓動電路Π0有PMOS電晶體120與NMOS電晶體 130，PMOS電晶體120源極接至電源內的高電壓〔V,。）， PMOS電晶體120汲極接至NMOS電晶體130汲極，而NMOS 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ------------#衣 *--- ----訂·------- '5^ * (請先閱讀背面之注意事項再填寫本頁) 427062 5094twf . doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（¥) 電晶體130源極接至電源內之低電壓（Vss)。PMOS電晶 體120閘極接至電源開啓自動重置電路200。NMOS電晶 體130閘極接至應用系統丨40內之參考電路142。 在電源開啓時應用系統140尙未進入正常的工作狀 態，此時應用系統140內之參考電路142送至NMOS電晶 體130閘極的電壓（應用系統訊號）太低所以未能開啓。 此時電源開啓自動重置電路200會先送出低電壓訊號 (開啓訊號）至PMOS電晶體120閘極並予以開啓’此時 A點爲高電壓準位（啓動電路開啓訊號）並將此高電壓準 位送至控制電路300，控制電路300此時達成與應用系統 140中之參考電路142的連接並且送出參考訊號’並根據 參考訊號此參考電路142可脫離初始狀態並到達末狀態。 當參考電路142到達末狀態，而應用系統140進入正 常狀態，此時參考電路U2會送出高電壓準位（應用系統 訊號）至NMOS電晶體130閘極使其開啓，開啓後A點被 拉低至低電壓準位（啓動電路關閉訊號），控制電路300 接收到此低電壓準位，切斷參考訊號與參考電路H2之間 的聯繫。 而電源開啓自動重置電路200,可在一個充裕的特定 時間之後送出高電壓（啓動電路關閉訊號）至PMOS電晶 體120閘極，用來關閉此PMOS電晶體120,而此時由於 NMOS電晶體130開啓所以A點的電壓依舊爲底電壓準位， 並且在啓動電路]10上由於PMOS電晶體120的關閉，不 會有習知的電流路徑產生，所以不會有電源功率無謂浪費 本紙張尺度適用中國國家標準（CNS)A4规格（210 X 297公楚） ------------ ^--------訂---------線< (請先閲讀背面之注意事項再填寫本頁) 4 2 7 0 6 2 5094twf,doc/006 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（f) 的情形發生。解決了習知啓動電路的問題。 請參照第3圖，其所繪示爲本發明省電型開啓電路之 較佳實施例繪示圖。 首先介紹電源開啓自動重置電路200，PMOS (第一 PMOS) 210的閘極與汲極連接，源極連接高電壓。 電阻器（R) —端連接至PMOS 21.0汲極，另一端點 連接至NMOS (第一 NMOS) 230閘極與電容器（C) 一端， 而電容器另一端接低電壓。 PMOS (第二PMOS) 220的源極連接高電壓，閘極連 接至NMOS 230閘極，PMOS 220汲極連接至NMOS 230汲 極。 NMOS (第二NMOS) 240汲極連接至NMOS 240閘極 與NMOS 230源極，NMOS 240源極連接至低電壓。 NMOS(第三NM〇S )250汲極連接至NMOS 230源極， NMOS 250源極連接至低電壓。 反相器（第一反相器）260輸入端連接至NMOS 230 汲極，反相器260輸出端連接至NMOS 250閘極與反相器 (第二反相器）270輸入端，反相器270輸出端連接至反 相器（第三反相器）280輸入端。 切換開關290耦接至高電壓、低電壓與反相器280輸 出端，當反相器280輸出低準位訊號至切換開關290，此 時切換開關290送出低電壓（開啓訊號），當反相器280 輸出高準位訊號至切換開關280，此時切換開關290送出 高電壓（關閉訊號）。 7 (請先閱讀背面之;i音？事項再填寫本頁) 裝The starting circuit Π0 has a PMOS transistor 120 and an NMOS transistor 130. The source of the PMOS transistor 120 is connected to a high voltage [V,] in the power source. ), The PMOS transistor 120 drain is connected to the NMOS transistor 130 drain, and the NMOS paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ------------ # 衣 * --- ---- Order · ------- '5 ^ * (Please read the notes on the back before filling in this page) 427062 5094twf .doc / 006 A7 B7 Employees, Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative. V. Description of Invention (¥) The low voltage (Vss) of the transistor 130 source is connected to the power supply. The gate of the PMOS transistor 120 is connected to the power-on automatic reset circuit 200. The gate of the NMOS transistor 130 is connected to the reference circuit 142 in the application system 40. When the power supply is turned on, the application system 140 尙 does not enter the normal working state. At this time, the voltage (application system signal) sent from the reference circuit 142 in the application system 140 to the NMOS transistor 130 is too low to be turned on. At this time, when the power is turned on, the automatic reset circuit 200 will first send a low voltage signal (open signal) to the gate of the PMOS transistor 120 and turn it on. At this point, point A is the high voltage level (the start circuit start signal) The level is sent to the control circuit 300. At this time, the control circuit 300 reaches the connection with the reference circuit 142 in the application system 140 and sends a reference signal ', and according to the reference signal, the reference circuit 142 can leave the initial state and reach the final state. When the reference circuit 142 reaches the end state and the application system 140 enters the normal state, the reference circuit U2 will send a high voltage level (application system signal) to the gate of the NMOS transistor 130 to make it open, and point A will be pulled low after opening. To the low voltage level (starting circuit shutdown signal), the control circuit 300 receives the low voltage level and cuts off the connection between the reference signal and the reference circuit H2. The power-on automatic reset circuit 200 can send a high voltage (start-up circuit shutdown signal) to the gate of the PMOS transistor 120 after a sufficient specific time, which is used to turn off the PMOS transistor 120. At this time, due to the NMOS transistor 130 turns on, so the voltage at point A is still at the bottom voltage level, and because the PMOS transistor 120 is turned off on the start circuit] 10, no conventional current path will be generated, so no power will be wasted. Applicable to China National Standard (CNS) A4 specification (210 X 297 Gongchu) ------------ ^ -------- Order --------- line < (Please read the notes on the back before filling out this page) 4 2 7 0 6 2 5094twf, doc / 006 B7 The consumer cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs has produced the fifth, description of invention (f). Solved the problem of the conventional startup circuit. Please refer to FIG. 3, which illustrates a preferred embodiment of a power-saving start-up circuit of the present invention. First, the power-on automatic reset circuit 200 is described. The gate of the PMOS (first PMOS) 210 is connected to the drain and the source is connected to a high voltage. Resistor (R) — The terminal is connected to the PMOS 21.0 drain, the other terminal is connected to the NMOS (first NMOS) 230 gate and one terminal of the capacitor (C), and the other terminal of the capacitor is connected to a low voltage. The source of the PMOS (second PMOS) 220 is connected to a high voltage, the gate is connected to the NMOS 230 gate, and the PMOS 220 drain is connected to the NMOS 230 drain. NMOS (second NMOS) 240 drain is connected to NMOS 240 gate and NMOS 230 source, and NMOS 240 source is connected to low voltage. The NMOS (third NMOS) 250 drain is connected to the NMOS 230 source, and the NMOS 250 source is connected to a low voltage. The input terminal of the inverter (first inverter) 260 is connected to the drain of the NMOS 230, and the output terminal of the inverter 260 is connected to the NMOS 250 gate and the input of the inverter (second inverter) 270, the inverter The 270 output terminal is connected to the inverter (third inverter) 280 input terminal. The switch 290 is coupled to the high-voltage, low-voltage and inverter 280 output terminals. When the inverter 280 outputs a low-level signal to the switch 290, the switch 290 sends a low voltage (open signal), and when the inverter 280 outputs a high level signal to the switch 280. At this time, the switch 290 sends a high voltage (close signal). 7 (Please read the "i" on the back? Matters before filling out this page)
* I I I I* I I I I
fB tf *fl I 線 本紙張尺度適用中國國家標準（CNS)A4規格（210^297公釐) 4 2 7 0 6 ?- 5094twf.doc/006 五、發明說明（厶） 在電源開啓時，由於電容器尙未充電，此時NMOS 230 閘極爲低準位所以關閉，而PMOS 220此時爲開啓，所以 反相器260輸入端爲高準位，此訊號再經過反相器270與 反相器280後輸入至切換開關290爲低準位訊號，此時切 換開關290輸出低電壓之開啓訊號。 而設定電阻器與電容器的値，使其充電時間充裕， 並在充電至特定時間之後NMOS 230開啓，此時反相器260 的輸入端爲低準位，此訊號再經過反相器270與反相器280 後輸入至切換開關290爲高準位訊號，此時切換開關290 輸出高電壓之關閉訊號。 再來介紹控制電路300，反相器（第四反相器）310 輸入端連接至A點。反相器（第五反相器）320輸入端連 接至反相器310輸出端。 PMOS (第三PMOS) 330的源極連接高電壓，閘極與 汲極連接並且作爲應用系統140內參考電路142的參考訊 號。 PMOS(第四PMOS) 340源極連接至PMOS 330汲極， PMOS 340閘極連接反相器310輸出端。 經濟部智慧財產局員工消費合作社印製 (請先閒讀背面之注意事項再填寫本頁) NMOS(第四NM〇S)350汲極連接至PMOS 340汲極， NMOS 350閘極連接至反相器320輸出端。 NMOS (第五NMOS) 360汲極連接至NMOS 350源極 與NMOS 360閘極，NMOS 360源極連接至低電壓。 當A點的電壓爲高電壓準位（啓動電路開啓訊號）， 反相器310輸出低準位，開啓PMOS 340，反相器320輸出 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 4270 6 2 5 0 9 4 t w f . d o c ,/ ' 0 0 6 五、發明說明（q ) 高準位，開啓NMOS 350。此時在PMOS 330汲極上的電壓 變換即爲參考訊號並送入參考電路142，而根據參考訊號 此參考電路142可脫離初始狀態並到達末狀態。 當A點的電壓爲低電壓準位（啓動電路關閉訊號）， 反相器310輸出尚準位，關閉PM0S 340，反相器320輸出 低準位，關閉NMOS 350。此時沒有參考訊號可送入參考 電路，只有高電壓與低電壓送入參考電路來作爲電源使 用c 因此，本發明的優點係提供一種省電型啓動電路， 包括有電源開啓自動重置電路，其會在應用系統到達正常 運作時關閉PMOS使得啓動電路不會有電源功率的浪費。 本發明的另一優點係提供一種省電型啓動電路，包 括有控制電路，其會在應用系統到達正常運作時關閉啓動 電路與應用電路之間的連接。 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 {請先間讀背面之注意事項再填寫本頁) ·--------訂·--------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）fB tf * fl The size of the I-line paper is applicable to China National Standard (CNS) A4 (210 ^ 297 mm) 4 2 7 0 6?-5094twf.doc / 006 V. Description of the invention (厶) When the power is turned on, The capacitor 尙 is not charged. At this time, the NMOS 230 gate is closed at a very low level, and the PMOS 220 is turned on at this time. Therefore, the input of the inverter 260 is at a high level, and this signal passes through the inverter 270 and the inverter 280. The input to the switch 290 is a low-level signal. At this time, the switch 290 outputs a low-voltage on signal. The resistor and capacitor are set to have sufficient charging time, and the NMOS 230 is turned on after charging to a certain time. At this time, the input of the inverter 260 is at a low level, and this signal passes through the inverter 270 and the inverter. After the phaser 280 is input to the switch 290, it is a high-level signal. At this time, the switch 290 outputs a high-voltage shutdown signal. The control circuit 300 is described again. The input terminal of the inverter (the fourth inverter) 310 is connected to the A point. The input terminal of the inverter (fifth inverter) 320 is connected to the output terminal of the inverter 310. The source of the PMOS (third PMOS) 330 is connected to a high voltage, and the gate is connected to the drain and used as a reference signal for the reference circuit 142 in the application system 140. The source of the PMOS (fourth PMOS) 340 is connected to the drain of the PMOS 330, and the gate of the PMOS 340 is connected to the output of the inverter 310. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) NMOS (the fourth NMOS) 350 drain is connected to the PMOS 340 drain, and the NMOS 350 gate is connected to the reverse phase Device 320 output. NMOS (fifth NMOS) 360 drain is connected to NMOS 350 source and NMOS 360 gate, and NMOS 360 source is connected to low voltage. When the voltage at point A is at the high voltage level (starting circuit start signal), the inverter 310 outputs the low level, the PMOS 340 is turned on, and the inverter 320 outputs 8 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4270 6 2 5 0 9 4 twf .doc, / '0 0 6 V. Description of the invention (q) High level, turn on the NMOS 350. At this time, the voltage conversion on the drain of PMOS 330 is the reference signal and is sent to the reference circuit 142. According to the reference signal, the reference circuit 142 can leave the initial state and reach the end state. When the voltage at point A is at the low voltage level (start-up circuit shutdown signal), the inverter 310 output is still in the level, PM0S 340 is turned off, the inverter 320 outputs the low level, and the NMOS 350 is turned off. At this time, no reference signal can be sent to the reference circuit, and only high voltage and low voltage are sent to the reference circuit to be used as the power source. Therefore, the advantage of the present invention is to provide a power-saving startup circuit including a power-on automatic reset circuit. It will turn off the PMOS when the application system reaches normal operation so that the startup circuit will not waste power. Another advantage of the present invention is to provide a power-saving start-up circuit including a control circuit that closes the connection between the start-up circuit and the application circuit when the application system reaches normal operation. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. {Please read the precautions on the back before filling in this page) · -------- Order · -------- The size of thread paper is applicable to China National Standard (CNS) A4 (210 X 297 Mm)