經濟部智慧財產局員工消費合作社印製 427020 5(!92twt：doc/0〇6 五、發明說明（/ ) 本發明是有關於一種非揮發性記憶體元件（Nonvolatile Memory Device) 之製造方法 ，且特別是有關於 一種增加可電除且可程式唯讀記憶體（Electrically Erasable Programmable ROM; EEPR0M )之電容稱合 (Capacitive Coupling)的方法。 習知非揮發性記憶體元件，如可抹除且可程式唯讀記 憶體（Erasable Programmable Read Only Memory; EPROM)、可電除且可程式唯讀記憶體（EEPROM)、快閃 記憶體（Flash Memory)等，由於所存入的記憶或數據不 會因爲電源供應的中斷而消失，因此具有優越之資料保存 特性，故相關的硏究一直在持續地進行中。 對於這類的非揮發性記憶體元件之記憶電晶體 (Memory Transistor)而言，其結構包括用來儲存電荷 (Charge)的浮置閘（Floating Gate)和用來控制資料 存取的控制閘（Control Gate)，其中浮置閘位於控制閘 和基底之間，且處於浮置狀態，沒有和任何電路相連接， 而控制閘則與字元線（Word Line)相接，此外還包括穿 隧氧化層和介電層分別位於基底和浮置閘之間以及浮置 閘和控制閘之間，另外還有源極/汲極位於控制閘兩旁的 基底中。 在目前提高元件積集度的趨勢下，會依據設計規則縮 小元件的尺寸，且元件的操作電壓也會隨之降低。而在記 憶電晶體的操作上，通常浮置閘與控制閘之間的電容耦合 越大，其操作所需之工作電壓將越低。因此必須增加浮置 3 本紙張尺度適用中國國家標準（CNS)A·!規格（210 X 297公釐） 1----------J--------- - 訂---·------線· ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 t 427020 r 5{)92nvrc1i)c/006 Λ/ __07___ 五、發明說明（之） 閘和控制閘之間的電容（Capacitance)。 而增加電容耦合的方法，包括了增加浮置閘與控制閘 間之重疊面積（Overlap Area)、降低浮置閘與控制閘間 之介電層的厚度、以及增加浮置閘與控制閘間之介電層的 介電常數（Dielectric Constant; k)。然而，浮置閘與 控制閘間之介電層必須具備足夠的厚度，以防止元件在進 行操作時，陷入在浮置閘的電子進入至控制閘中，而導致 元件失效。至於增加浮置閘與控制閘間之介電層的介電常 數的課題，則牽涉到製程設備的更換與製程技術成熟度的 問題，並不是可以輕易達到的。 因此，本發明藉由增加浮置閘與控制閘間之重疊面 積，以增加可電除且可程式唯讀記憶體（EEPR0M)之記億 電晶體的電容耦合。 有鑑於此，本發明提供一種改善可電除且可程式唯讀 記憶體（EEPR0M)之電容耦合的方法，包括：提供已形成 元件隔離結構的基底，並於其上形成穿隧氧化層，之後於 穿隧氧化層上形成第一導電層，並於第一導電層上形成絕 緣層，此絕緣層中已定義出一開口，此開口對應於欲形成 之浮置閘的部份區域，續於絕緣層和第一導電層上形成大 致共形的第二導電層，剝除部份第二導電層，以於絕緣層 中之開口的側壁形成導電間隙壁，此導電間隙壁係爲浮置 閘的一部份，之後剝除絕緣層，並將第一導電層圖案化， 以定義出另一部份的浮置閘和選擇電晶體的閘極，接著形 成一層共形的介電層，以及形成第三導電層以做爲記憶電 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） n J: —λ- ϋ IB. ft It I n >1 訂---------線tw (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 427020 五、發明說明（$) 晶體的一控制閘。 因此，本發明藉由導電間隙壁的形成來增加浮置閘的 表面積，以增加浮置閘與控制閘間之重疊面積，以增加可 電除且可程式唯讀記憶體（EEPR⑽）之記憶電晶體的電容 耦合。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係繪示根據本發明一較佳實施例之一種可電除 且可程式唯讀記憶體胞的佈局圖；以及 第2A圖至第2E圖爲第1圖的II-II剖面圖，其係繪 示根據本發明一較佳實施例之一種可電除且可程式唯讀 記憶體的製造流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 100 :基底 104 :穿隧氧化層 106、106a、112 :導電層 106b :導電層（選擇電晶體的閘極） 108、108a、122 :絕緣層 110 :開口 112a :導電間隙壁 114 :記憶電晶體的浮置閘 118 :介電層 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先間讀背面之注意事項再填寫本頁) W---- 訂—-------線_ 經濟部智慧財產局員工消費合作社印製 d27020 五、發明說明（4) 120 :記憶電晶體的控制閘 124 :接觸窗開口 126 :位元線 130 :源極/汲極 150 :選擇電晶體 160 :記憶電晶體 實施例 第1圖所不，爲根據本發明一較佳實施例之一種可電 除且可程式唯讀記憶體（EEPROM)胞的佈局圖。EEPROM胞 係由一個選擇電晶體（SelectTransistor) 150和記憶電 晶體160所組成，其中選擇電晶體150係用來控制記億電 晶體160之資料的儲存與讀取之用。 第2A圖至第2E圖係繪示根據本發明一較佳實施例之 一種可電除且可程式唯讀記憶體（EEPROM)的製造流程剖 面圖，其中第2A圖至第2E圖係爲第1圖的II-II剖面圖。 請參照第2A圖，提供一基底100，比如是半導體矽基 底，於基底100中形成元件隔離結構（未繪示出），以定義 出主動區，其中元件隔離結構比如是場氧化層或淺溝渠隔 離結構，較佳的是場氧化層。之後於基底100的主動區先 形成一層厚度較厚的氧化層104,然後經微影蝕刻製程， 而於其中形成開口，暴露出欲形成穿隧氧化層的區域之基 底100表面，然後比如利用熱氧化法於厚氧化層104所暴 露出的基底100表面形成一層厚度較薄的穿隧氧化層 105，當然在形成穿隧氧化層105的同時，厚氧化層104 6 ------J--I J--------II ---.------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 427020 五、發明說明（乡） 的厚度亦會略爲增加。接著再於整個基底100上覆蓋一層 導電層106，其材質比如是摻雜的複晶矽，其形成方法比 如是化學氣相沈積法，之後於導電層106上覆蓋一層絕緣 層108，其材質比如是氧化矽，其形成方法比如是以四乙 氧基砂院（Tetra-ethyl-ortho-silicate; TEOS)爲製程 氣體進行化學氣相沈積製程。 接著請參照第2B圖，利用微影蝕刻的製程，將絕緣 層108圖案化成絕緣層108a，以於其中形成開口 110，此 開口 110位於穿隧氧化層105上，大致對應於後續將形成 之記憶電晶體160的浮置閘之部份區域且其尺寸大於穿隧 氧化層105之尺寸。之後於絕緣層108上覆蓋一層共形的 導電層112，其材質比如是摻雜的複晶矽，其形成方法比 如是化學氣相沈積法。 接著請參照第2C圖，對導電層112進行回蝕刻製程， 直至暴露出絕緣層108a的上表面，以於開口 U0的側壁 形成導電間隙壁112a，此導電間隙壁112a係爲浮置閘的 一部份。 接著請參照第2D圖，剝除絕緣層108a，以裸露出導 電間隙壁112a的其他表面，並將導電層106圖案化成導 電層106a和106b，以分別定義出記億電晶體160之另一 部份的浮置閘U4和選擇電晶體150的閘極106b，其中記 憶電晶體160的浮置閘114係由導電間隙壁112a和與其 相連的導電層106a所組成。因此，藉由導電間隙壁112a 的形成，可用以增加浮置閘114的表面積，以提高後續將 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 427020 5 (! 92twt: doc / 0〇6 V. Description of the Invention (/) The present invention relates to a method for manufacturing a nonvolatile memory device, and In particular, it relates to a method for increasing capacitive coupling of electrically erasable and programmable read-only memory (EEPR0M). Known non-volatile memory elements, such as erasable and removable Erasable Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), Flash Memory, etc. The interruption of the power supply disappears, so it has excellent data storage characteristics, so the related research has been ongoing. For the memory transistor of such non-volatile memory elements, its structure Including Floating Gate for storing charge and Control Gate for controlling data access, among them Floating Gate The control gate and the substrate are in a floating state and are not connected to any circuit. The control gate is connected to the Word Line. In addition, the tunnel oxide layer and the dielectric layer are located on the substrate. Between the floating gate and the floating gate and between the floating gate and the control gate, and in addition, the source / drain are located in the substrate on both sides of the control gate. Under the current trend of increasing the component accumulation, the component size will be reduced according to design rules. Size, and the operating voltage of the component will be reduced accordingly. In the operation of the memory transistor, usually the greater the capacitive coupling between the floating gate and the control gate, the lower the operating voltage required for its operation. Increase floating 3 This paper size is applicable to China National Standard (CNS) A ·! Specifications (210 X 297 mm) 1 ---------- J ----------Order- -· ------ Line · ^ (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs t 427020 r 5 {) 92nvrc1i) c / 006 Λ / __07___ V. DESCRIPTION OF THE INVENTION The capacitance between the gate and the control gate (Capacitance). Methods for increasing capacitive coupling include increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the distance between the floating gate and the control gate. Dielectric Constant (k) of the dielectric layer. However, the dielectric layer between the floating gate and the control gate must have sufficient thickness to prevent the electrons trapped in the floating gate from entering the control gate during the operation of the element, which will cause the component to fail. As for the issue of increasing the dielectric constant of the dielectric layer between the floating gate and the control gate, it involves the replacement of process equipment and the maturity of process technology, which cannot be easily achieved. Therefore, the present invention increases the capacitive area of the billion-transistor transistor that can be removed and programmable read-only memory (EEPR0M) by increasing the overlap area between the floating gate and the control gate. In view of this, the present invention provides a method for improving the capacitive coupling of an erasable and programmable read-only memory (EEPR0M), which includes: providing a substrate on which an element isolation structure has been formed, and forming a tunneling oxide layer thereon, and thereafter A first conductive layer is formed on the tunneling oxide layer, and an insulating layer is formed on the first conductive layer. An opening has been defined in the insulating layer, and this opening corresponds to a part of the floating gate to be formed, continued from A substantially conformal second conductive layer is formed on the insulating layer and the first conductive layer, and a part of the second conductive layer is stripped to form a conductive barrier wall on the side wall of the opening in the insulating layer. The conductive barrier wall is a floating gate. Part of the insulating layer, then stripping the insulating layer and patterning the first conductive layer to define the other part of the floating gate and the gate of the selected transistor, and then forming a conformal dielectric layer, and Form the third conductive layer as the memory. 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210x 297 mm) n J: —λ- ϋ IB. Ft It I n > 1 Order ---- ----- line tw (Please read the notes on the back before filling Page) Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed 427,020 V. invention is described in ($) a control gate crystals. Therefore, in the present invention, the surface area of the floating gate is increased by the formation of the conductive gap wall, so as to increase the overlap area between the floating gate and the control gate, so as to increase the memory capacity of the removable and programmable read-only memory (EEPR⑽). Capacitive coupling of the crystal. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 FIG. 2 is a layout diagram of an erasable and programmable read-only memory cell according to a preferred embodiment of the present invention; and FIGS. 2A to 2E are cross-sectional views taken along line II-II in FIG. A cross-sectional view of a manufacturing process of an erasable and programmable read-only memory according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 100: substrate 104: tunneling oxide layers 106, 106a, 112: conductive layer 106b: conductive layer (select gate of transistor) 108, 108a, 122: insulating layer 110 : Opening 112a: Conductive spacer 114: Floating gate of memory transistor 118: Dielectric layer The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back first) (Fill in this page again.) W ---- Order -------- Line _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs d27020 V. Description of the invention (4) 120: Control gate of memory transistor 124: Contact Window opening 126: bit line 130: source / drain 150: selection transistor 160: memory transistor Embodiment Not shown in Fig. 1 is a type that can be removed and programmed according to a preferred embodiment of the present invention. Read the layout of the memory (EEPROM) cell. The EEPROM cell is composed of a Select Transistor 150 and a Memory Transistor 160. The Select Transistor 150 is used to control the storage and reading of the data of the memory transistor 160. FIGS. 2A to 2E are cross-sectional views illustrating a manufacturing process of an erasable and programmable read-only memory (EEPROM) according to a preferred embodiment of the present invention, wherein FIGS. 2A to 2E are Section II-II in Figure 1. Referring to FIG. 2A, a substrate 100 is provided, such as a semiconductor silicon substrate, and an element isolation structure (not shown) is formed in the substrate 100 to define an active region. The element isolation structure is, for example, a field oxide layer or a shallow trench. The isolation structure is preferably a field oxide layer. Then, a thicker oxide layer 104 is formed in the active area of the substrate 100, and then a lithography process is performed to form an opening therein to expose the surface of the substrate 100 in the region where the tunnel oxide layer is to be formed. The oxidation method forms a thin tunneling oxide layer 105 on the surface of the substrate 100 exposed by the thick oxide layer 104. Of course, when the tunneling oxide layer 105 is formed, the thick oxide layer 104 6 ------ J- -I J -------- II ---.------ line (Please read the precautions on the back before filling this page) This paper is also applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 427020 5. The thickness of the invention description (township) will also increase slightly. Then, the entire substrate 100 is covered with a conductive layer 106. The material is, for example, doped polycrystalline silicon. The formation method is, for example, chemical vapor deposition. Then, the conductive layer 106 is covered with an insulating layer 108. The material is It is silicon oxide, and its formation method is, for example, a chemical vapor deposition process using Tetra-ethyl-ortho-silicate (TEOS) as a process gas. Next, referring to FIG. 2B, the lithographic etching process is used to pattern the insulating layer 108 into an insulating layer 108a to form an opening 110 therein. This opening 110 is located on the tunneling oxide layer 105, which roughly corresponds to the memory to be formed later. A part of the floating gate of the transistor 160 is larger than the size of the tunneling oxide layer 105. Then, a layer of conformal conductive layer 112 is covered on the insulating layer 108. The material of the conductive layer 112 is, for example, doped polycrystalline silicon. The formation method is, for example, chemical vapor deposition. Next, referring to FIG. 2C, the conductive layer 112 is etched back until the upper surface of the insulating layer 108a is exposed, so that a conductive gap wall 112a is formed on the side wall of the opening U0. This conductive gap wall 112a is a part of the floating gate. Part. Next, referring to FIG. 2D, the insulation layer 108a is stripped to expose the other surfaces of the conductive spacer 112a, and the conductive layer 106 is patterned into conductive layers 106a and 106b to define the other part of the billion-dollar transistor 160, respectively. The floating gate U4 and the gate 106b of the transistor 150 are selected. The floating gate 114 of the memory transistor 160 is composed of a conductive spacer 112a and a conductive layer 106a connected to the conductive spacer 112a. Therefore, the formation of the conductive spacer 112a can be used to increase the surface area of the floating gate 114 to increase the subsequent application of 7 paper sizes to the Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the back first) (Notes for filling in this page)
訂——：------線 V 經濟部智慧財產局員工消費合作社印製 427020 五、發明說明（各） 形成之控制閘與浮置閘114之間的電容稱合。 接著請參照第2E圖’於記億電晶體160的浮置閘114 上覆蓋一層共形的介電層118 ’此介電層118比如是藉由 化學氣相沈積法所形成的氧化矽-氮化砂-氧化矽（〇N〇) 結構。當然此介電層U8亦會覆蓋於選擇電晶體150的閘 極106b上。然後*於介電層上覆蓋一層導電層，並 將其圖案化，以形成記憶電晶體160的控制閘120，此導 電層的材質比如是摻雜的複晶矽或金屬。之後’在基底1〇〇 中形成於記憶電晶體160和選擇電晶體150的源極/汲極 130，其製作的方法可以進行離子植入製程而得。續於控 制閘120上覆蓋另一層厚度較厚的絕緣層122 ’此絕緣層 122係用於與後續將形成的導線做電性隔離，而此絕緣層 122中形成有接觸窗開口 124,此接觸窗開口 124並延伸 至介電層118和穿隧氧化層1〇4中，並於接觸窗開口 124 中塡入導電材質，以做爲位元線126之用。 綜上所述，本發明的優點爲藉由導電間隙壁的形成來 增加浮置閘的表面積，以增加浮置閘與控制閘間之重疊面 積，以增加可電除且可程式唯讀記憶體（EEPROM)之記憶 電晶體的電容耦合，進而降低元件的操作電壓，以及提高 資料儲存的可靠度。 本發明不僅適用於可電除且可程式唯讀記憶體 (EEPROM )，亦可適用於可抹除且可程式唯讀記憶體 (EPROM)或快閃記憶體（Flash Memory)等之記憶電晶 體的製造上，用以改善電容耦合。 8 ------I i ] I I - -------^ 11-[11111 . W (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 427 0 2 0 Λ ^ 50^2twt'.docA)06 i 1 —-^--— 五、發明說明（"]) 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------tl---1. >裝--------訂——；------線 > (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0 X 297公釐）Order ——: ------ Line V Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 427020 V. Description of the Invention (Each) The capacitance between the control gate and the floating gate 114 is equal. Next, please refer to FIG. 2E, “a floating dielectric layer 118 is covered on the floating gate 114 of the memory transistor 160.” The dielectric layer 118 is, for example, silicon oxide-nitrogen formed by chemical vapor deposition. Sand-silica (ONO) structure. Of course, this dielectric layer U8 will also cover the gate 106b of the selection transistor 150. Then, the dielectric layer is covered with a conductive layer and patterned to form the control gate 120 of the memory transistor 160. The material of the conductive layer is, for example, doped polycrystalline silicon or metal. After that, the source / drain 130 of the memory transistor 160 and the selection transistor 150 is formed in the substrate 100, and the manufacturing method thereof can be obtained by an ion implantation process. Continue to cover another thick insulating layer 122 on the control gate 120. This insulating layer 122 is used to electrically isolate the conductors to be formed later, and a contact window opening 124 is formed in this insulating layer 122. This contact The window opening 124 extends into the dielectric layer 118 and the tunneling oxide layer 104, and a conductive material is inserted into the contact window opening 124 to serve as the bit line 126. In summary, the present invention has the advantage of increasing the surface area of the floating gate through the formation of the conductive partition wall, so as to increase the overlap area between the floating gate and the control gate, so as to increase the chargeable and programmable read-only memory. (EEPROM) capacitive coupling of the memory transistor, thereby reducing the operating voltage of the component and improving the reliability of data storage. The invention is not only applicable to erasable and programmable read-only memory (EEPROM), but also applicable to erasable and programmable read-only memory (EPROM) or flash memory (Flash Memory), etc. To improve the capacitive coupling. 8 ------ I i] II-------- ^ 11- [11111. W (Please read the precautions on the back before filling out this page) The paper size applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) 427 0 2 0 Λ ^ 50 ^ 2twt'.docA) 06 i 1 —- ^ --— 5. Description of the invention ("]) Although the present invention has been disclosed as above with preferred embodiments However, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be regarded as the scope of patent application attached to it. The ones defined shall prevail. ------ tl --- 1. > install -------- order ——; ------ line > (Please read the precautions on the back before filling this page) Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 9 This paper size applies to China National Standard (CNS) A4 (2 丨 0 X 297 mm)