TW426964B - Fabrication method of copper alloy interconnects - Google Patents

Abstract

This invention provides the fabrication method of copper alloy interconnects. On the upper surface or the lower surface of pure copper metal layer, an adjacent copper alloy layer (Cu and Zr, Al, Ti, or Sn) is formed. Thermal annealing process is used to make Zr, Al, Ti, or Sn and so on diffuse into pure copper metal layer in order to form the copper alloy interconnects. Based on the fabrication method of this invention, the oxidation of pure copper metal can be prevented. Furthermore, the electromigration resistance of interconnects can be increased.

Description

V. Description of the invention ¢ 1) ---- The present invention relates to a semiconductor integrated device (semiconductor IC d = lce) process, especially a copper metal interconnect (interc ο can prevent oxidation) η nects) process. No matter what kind of electronic component is indispensable, the metal wire used for transmitting telecommunications, "semiconductor integrated circuit components," and so on. Each component must be electrically connected through proper interconnections in order to perform the desired function. In today's multi-layer interconnection process, in addition to making each layer of wire pattern, it is also necessary to use contact vias to form a contact channel between the component contact area and the wire 9 or between the multi-layer wires.纟 In terms of internal wire f, copper has become one of the most widely used materials due to its high conductivity and high ductility. However, copper metal is easily susceptible to irritation by children, and therefore, the technology of replacing pure copper metal with copper alloy has been proposed. As shown in Figure 1, Xige _ Zancup Road Gangbang: The map should not show the semiconductor substrate 10 with the groove 12 not formed, the symbol; 14 is Sakata from! ® # t & 丄 u 4 Ma copper alloy made by spattering copper alloys by physical vapor deposition (PVD); Putiankou 坫 .. 呤 ^ f 1N lean layer, using the pVD method to form a copper alloy layer Gap fill is not good, women's football, BS main and easy to produce voids (question 15) τϊΕ 〇 In addition, as shown in Figure 2, the bottle-body base 20, symbol 22 indicates diffusion ^ And the figure is dark; ^ is formed with the groove 21 to lead to other components, and the symbol 24 :; = dust is used to prevent the diffusion of copper metal I, ^ > 1 ^ ^ ^ ECD ^ ^ ^ ^ ^ (ECD) ^ ^ ^ Pure copper metal I cannot form steel Zhen Er Er Jia ', but can only form the production method of the second aspect of the present invention in view of this, which is made by thermal diffusion; for copper interconnects Forming a copper alloy layer, so that

4 269 6 4 V. Description of the invention (2) Prevent pure copper metal from being oxidized, and increase the resistance of the electron migration (e 1 ect romigrat ion) of the interconnect. According to the above object, the present invention provides a method for manufacturing a copper alloy interconnect, which is suitable for forming a semiconductor substrate having a trench or a dual damascene structure. The manufacturing method includes the following steps: on the sidewall and bottom of the trench or dual damascene structure Forming a copper alloy seed layer; forming a copper metal layer filled with the trench or the dual damascene structure by an electrochemical deposition method; and performing a thermal tempering step to mix other metals into the copper metal layer to form copper Alloy inner wire. Furthermore, according to the above-mentioned object, the present invention provides another method for manufacturing a copper alloy interconnect, which is suitable for forming a semiconductor substrate having a trench or a dual damascene structure. The above manufacturing method includes the following steps: forming an infill using an electrochemical deposition method The copper metal layer of the above-mentioned trench or double damascene structure; a copper alloy cover layer is formed above the copper-gold layer; a thermal tempering step is performed to mix other metals in the upper copper metal layer to form copper alloy interconnects . ^ The above copper alloy is an alloy of copper and at least one group selected from the group consisting of zirconium, aluminum, titanium, and tin metals, which is formed by sputtering using a physical vapor deposition method. ^ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible ', a preferred embodiment is given below, and in conjunction with the attached round form, the explanation is as follows: Illustration. Figure 1 shows the cross section of the copper interconnects formed by the first conventional technique. Figure 2 shows the cross sections of the copper interconnects formed by the second conventional technique. Figure 3A and 3C are diagrams according to the present invention. 1 Example Formation of Copper Alloy

426964 V. Description of the invention (3) A schematic cross-sectional view of the manufacturing process of the line. Figures 4A to 4C are schematic cross-sectional views of a process for forming a steel alloy internal wire according to a second embodiment of the present invention. Explanation of symbols 100, 200 to semiconductor substrate. 1 0 1 ~ groove. 102, 20 2 ~ Diffusion barrier layer. 1 0 4 ~ seed layer of copper alloy. 106, 204a ~ copper alloy interconnect. 204 to copper metal layer. 206 ~ Copper alloy coating. First Embodiment The following uses FIGS. 3A to 3C to explain the first aspect of the present invention in more detail! Examples. First, please refer to FIG. 3A. This figure shows a semiconductor (such as a single crystal silicon) substrate 100 having a number of elements (not shown) and a trench 101, and the symbol 102 is used to prevent copper metal from diffusing to other substrates. The diffusion barrier layer of the device is made of materials such as buttons (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN), and the thickness is, for example, between 200 and 400 A. between. Next, please refer to FIG. 3B, which is a subsequent step of FIG. 3A. A physical vapor deposition (PVD) method is used to form a copper alloy seed layer on the surface of the diffusion barrier layer 102. seed layer), the material of the copper alloy seed layer 104 is steel and

Page 6 4269 6 4 V. Description of the invention (4) At least one alloy of metal (Zr), aluminum (A1), titanium (Ti), or tin (Sn), whose purpose is to establish subsequent electrochemical deposition (elect ro -chemical deposition (ECD) copper metal structure. Then, referring to FIG. 3C, an electrochemical deposition method (ECD) is used to form the copper metal layer filled in the trench 101, and secondly, thermal annealing is performed at a temperature of 800 to 1000 ° C. A copper alloy interconnect 106 is formed by doping a copper (Zr), aluminum (A1), titanium (Ti), or tin (Sn) metal into the copper metal layer. The zirconium, aluminum, titanium, or tin metal is diffused from the copper alloy seed layer 104 to the copper metal layer by using the thermal energy provided by the thermal tempering step. Second Embodiment The second embodiment of the present invention will be described in more detail with reference to Figs. 4A to 4C. First, please refer to FIG. 4A, which shows a semiconductor (such as a single crystal silicon) substrate 200 having a plurality of elements (not shown) and a trench 201 formed therein, and a symbol 202 denotes a metal used to prevent copper metal from diffusing to other The material of the diffusion barrier layer of the device is, for example, a button (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (T i N), and the thickness is, for example, between 200 and 40 0 A. . Secondly, the electrochemical metal deposition method (ECD) is used to form the copper metal layer filling the above-mentioned trench 201 after 204 °. 'Please refer to FIG. 4B' using physical vapor deposition (PVD) on the steel metal. A thick copper alloy cap layer 206 is formed over the layer 204. The material of the copper alloy cover layer 206 is, for example, copper and at least

Page 7 4269 6 4_ 5. Description of the invention (5) A zirconium (Zr), aluminum (A1), titanium (Ti), or tin (Sn) metal. Please refer to Figure 4C, at 80 0 to 1,000. T: temperature annealing step (annealing), so that the copper metal layer 204 is doped with (Zr), aluminum (A1), '(Ti), or tin (Sn) metal to form a wire 204a. Features and Effects of the Invention The present invention is characterized in that the surface of the pure copper metal layer or an adjacent copper alloy layer (Cu and Zr, A1, Ti, or Sn, etc.) is thermally tempered to make Zr, A1, Ti, or Sn It diffuses to pure copper to form a copper alloy interconnect.

According to the manufacturing method of the present invention, it is possible to prevent pure copper metal from being lifted and further increase the resistance value of the electron migration of the interconnect D. Although the present invention has been disclosed as above with a preferred embodiment, it limits the present invention. Anyone skilled in the art, Changes and retouching can be made without departing from the spirit and scope. Therefore, the present invention shall be determined by the scope of the appended patent application. alloy. The following is to heat into the inner surface of the zirconium steel alloy, and then use the metal layer to make the halogenation. It is not used to protect the scope of the invention.

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Claims (1)

κ%. m > ° 'Rev. JL · ^ _____ 426964 _ Case No. 88] 1! ^ f) 2 Beta year A month η VI' application patent scope 1. A manufacturing method of copper alloy interconnects, suitable for forming A semiconductor substrate with a trench or dual damascene structure. The manufacturing method includes the following steps: forming a copper alloy seed layer on the sidewall and bottom of the trench or dual damascene structure; The copper metal layer of the mosaic structure is subjected to a thermal tempering step to mix other metals into the copper metal layer to form copper alloy interconnects. 2. The method for manufacturing a copper alloy interconnect as described in item 1 of the patent application scope, wherein the step of forming a diffusion barrier layer is further included before the steel alloy seed layer is formed. 3. The method for manufacturing copper alloy interconnects as described in the second aspect of the application for patent application, wherein the diffusion barrier layer is selected from the group consisting of at least one of tantalum, nitride button, titanium, and titanium nitride. 4 · The manufacturing method of copper alloy interconnects as described in the scope of application for patents', wherein the copper alloy is copper and an alloy selected from the group consisting of at least one metal of aluminum, titanium, and tin. 5. The manufacturing method of copper alloy interconnects as described in the & patent application scope ' wherein the seed layer of the steel alloy is sputtered by physical vapor deposition. 6. —A method for manufacturing copper alloy interconnects ’is suitable for forming a semiconductor substrate with a trench or a dual damascene structure. The above manufacturing method includes the following steps Year B 4 2 69 6 ^ 881158〇2 6. Scope of patent application —- * -— A diffusion barrier layer is formed on the side wall and bottom of the above trench or double-inlaid hibiscus; Layer surface formation—steel alloy seed layer, said steel alloy copper ”is selected from the group consisting of y-type zirconium, aluminum, titanium, and tin metals; the electrochemical deposition method is used to fill the above grooves or double mosaic The structured copper metal layer is subjected to a thermal tempering step to mix the above-mentioned copper metal layer with zirconium, hafnium, titanium, or tin metal to form a steel alloy interconnect ^ 7. As described in item 6 of the patent application Manufacturing method of copper alloy interconnects' wherein the above-mentioned diffusion barrier layer is selected from the group consisting of at least one group, silver, aluminum, and gas. 8. The copper as described in item 6 of the scope of the patent application. Method for manufacturing alloy interconnects, wherein the copper alloy seed layer is deposited by physical vapor deposition method ° 9. A method for manufacturing copper alloy interconnects, which is suitable for forming semiconductors with trenches or dual damascene structures Substrate, the above manufacturing method includes the following steps: A wide diffusion barrier is formed on the side wall and the bottom of the trench or dual damascene structure, and a copper metal layer filled with the foregoing groove or dual ball structure is formed by an electrochemical deposition method, and a copper is formed above the copper metal layer. Alloy cover layer, the above-mentioned copper alloy-based copper is selected from the group consisting of at least -species, metal, metal and metal. 〇5〇3-4822-^? 1, ||: (page 10 4269 6 4 correction -Case No. nwn? _Year 6. Scope of patent application Alloy; applying a thermal tempering step to mix the copper metal layer with file, aluminum, zinc, or tin metal to form copper alloy interconnects. 10. The method for manufacturing a copper alloy interconnect in accordance with item 9 of the patent application claim, wherein the diffusion barrier layer is selected from the group consisting of at least one button, tantalum nitride, titanium, and titanium nitride. Π. The method for manufacturing a steel alloy interconnect as described in item 9 of the scope of the patent application, wherein the above-mentioned copper alloy coating layer is formed by a physical vapor deposition method. 12. —Production method of a kind of steel alloy interconnects' is applicable to a semiconductor substrate formed with a trench or a dual damascene structure. The above manufacturing method includes the following steps: An electrochemical deposition method is used to form a semiconductor substrate filled with the trench or dual damascene structure. A copper metal layer; forming a copper alloy cover layer on the copper metal layer; and applying a thermal tempering step to mix other metals into the copper metal layer to form a copper alloy interconnect. 13. The method for manufacturing a copper alloy interconnect as described in claim 12 of the scope of patent application, wherein the step of forming a diffusion barrier layer is further included before forming the surface metal layer. Manufacture of steel alloy interconnects 1 4. The manufacturing method of copper alloy interconnects y described in the patent application No. 丨 3, wherein the diffusion barrier layer is selected from the group consisting of a few kinds of titanium nitride And titanium nitride. 15. As described in item 12 of the scope of patent application 0503-4822T * Flptc 11th tribute 4269 6 4 0553-432 2ΤίΠ · ρ !: Page 12