426963 5002twfdoc/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 本發明是有關於一種半導體內連線（interconnect)的製 造方法，且特別是有關於一種介層窗（via)開口的製造方 法。 在半導體尺寸逐漸邁入〇·25μπι，甚至0.25μηι以下的 製程，當在介電層100中形成開口 102時，介電層100的 蝕刻係以金屬層104上的阻障層106作爲一終止層而進 行，如第1圖所示。然而，由於以C4H8蝕刻阻障層106 上覆蓋的矽氧氮化物層107與介電層100的蝕刻選擇比 (selectivity)不高（約在1 : 10左右），且阻障層106厚度不 大的情況下，使得在蝕刻介電層100時並無法停止在阻障 層106上，而直接暴露出底下的金屬層104，造成過度蝕 刻。過度蝕刻使得暴露出的金屬層104遭到濺鍍 (sputtering)，而形成含金屬的高分子108覆蓋住開口 102 側壁的介電層100，造成開口 102底部的戌寸縮小。而阻 障層106的損失造成製程完成後元件可靠度(reliability)降 低的問題，且須花費更多的時間進行淸洗含金屬高分子 108的動作，不僅增加操作時間，不符合降低成本的考量’ 更對阻障層106造成損壞，造成產品良率降低。 因此，本發明就是在提供一種介層窗開口的製造方 法，避免蝕刻介層窗開口時，形成高分子在介層窗開口底 部側壁沉積，造成開口縮小與可靠度降低等問題。 本發明就是在提供一種介層窗開口的製造方法’可以 減少後續製程以溶劑淸洗晶片的步驟。 本發明提供一種介層窗開口的製造方法，在一金屬層 3 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 本紙張尺度適甲令國园家標準（C1SS)A4規格（210>=297公:g ) 經濟部智慧財產局負工消費合作社印制ϊί 4* d^c/008 五、發明說明（v) 上依序形成一阻障層與一矽氧氮化物層，接著，在金屬層 上形成一介電層。之後利用光阻，且以矽氧氮化物層作爲 一蝕刻終止層，而在介電層中形成一開口，暴露出矽氧氮 化物層。續再去除光阻，且再以阻障層爲蝕刻終止層，將 矽氧氮化物層去除。 其中’蝕刻介電層時係在電漿反應室中通入 C^Fs/Ar/CO的蝕刻劑，而去除矽氧氮化物層時是利用 CHxFy/Ar/CO之混合氣體，故蝕刻阻障層與矽氧氮化物層 具有一高蝕刻選擇比，使得蝕刻步驟可順利停止在阻障 層。同時在去除光阻時可同時去除不必要高分子的沉積， 而在後續製程中可僅用去離子水淸洗即可，不僅節省操作 時間，避免阻障層金屬的侵蝕，同時亦降低成本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下： 圖式之簡單說明： 第1圖係顯示一種習知介層窗開口的剖面圖：以及 第2A-2D圖係顯示根據本發明較佳實施例介層窗開口 之製造流程剖面圖。 其中’各圖標號之簡單說明如下： 100、208 :介電層 102、212 :開口 104、202 :金屬層 106、204 :阻障層 4 ------------ --I-----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNSM1规格公釐了 經濟部智慧財產局員工消費合作社印製 4 269 6 3 ^ 5002twf.doc/008 B7 ----—-------—---------- 五、發明說明（3 ) 108 :局分子 200 :基底 1〇7、206 :砂氧氮化物層 210 :光阻 214 :介層窗開口 實施例 本發明之較佳實施例係利用矽氧氮化物層與阻障層的 高蝕刻選擇比’使介電層的蝕刻步驟可以停止在阻障層， 因此底下之金屬層不會暴露出，故也不會造成金屬層的損 害，同時可以避免不必要高分子的形成造成介層窗開口的 縮減。此外’若有不必要的高分子生成，可在去除光阻時 臨場（in-situ)去除，同時在後續製程中可省略以溶液淸洗晶 片的步驟，故可節省成本，減少溶劑對阻障層的破壞。 第2A-2D圖所示，爲根據本發明一較佳實施例之介層 窗開口之製造流程剖面圖。請參照第2A圖，在一基底200 上形成一金屬層202，例如爲鋁。接著，在金屬層2〇2上 形成一阻障層204，例如爲鈦/氮化鈦層，而氮化鈦層厚度 約爲200-500埃左右。之後，在阻障層2〇4上形成一矽氧 氮化物層206，例如以化學氣相沉積法形成’覆蓋阻障層 204 ° 接著，在基底200上形成一介電層2〇8 ’覆蓋矽氧氮 化物層206，介電層208例如爲二氧化矽。之後’在介電 層上208形成一光阻層21〇 ’而光阻層在經微影製程 後在預定形成介層窗開口的位置上形成一開口 212 ’暴露 ------------裝--------訂---------線 ， (請先閱讀背面之注意事項再填寫本頁) 本紙張K度適用中國國家標準規格（2】tM 2(J7公餐） 經濟部智慧財產局員工消費合作社印製 4 2 69 6 3 a? 5002lwf.doc/008 ___B7_ 五、發明說明（d ) 出部分介電層208 *如第2A圖所示。 請參照第2B圖’接著以光阻210定義介電層208，並 以矽氧氮化物層206爲蝕刻終止層，而在介電層208中形 成一介層窗開口 214，暴露出矽氧氮化物層206，其中垂 直的蝕刻輪廓約爲89°。蝕刻製程例如以電感耦式高密度 電漀蝕刻（ICP high density plasma etcher)進行，触刻氣體 包括C4F8、Ar與CO之混合氣體，更可包括C2F6。 之後，進行光阻210去除的步驟，例如以氧電漿灰化 (ash)方式去除。由於在蝕刻介電層208的步驟係停止在砂 氧氮化物層206,同時更調整反應室在一低偏壓的狀態 下，減少電漿轟擊的能量，因此，電漿更不會大量地蝕刻 阻障層2〇4，使金屬層2〇2暴露出，故電漿不會濺鍍金屬 層2〇2而引起含金屬的高分子ί几積在介層窗開口 214底部 側壁。但是在上述蝕刻步驟中’可能仍會有不含金屬的高 分子形成在介層窗開口 2丨4側壁或矽氧氮化物層206上， 則不含金屬的高分子可在氧電漿去除光阻210的同時臨場 去除，其可避免影響後續蝕刻矽氧氮化物的製程，如第2C 圖所示。由於不會產生含金屬高分子，而不含金屬高分子 又可以氧電漿去除，故介層窗開D 214側壁與矽氧氮化物 層2〇6上不會有高分子殘留’於是後續蝕刻製程可以順利 進行，而介層窗開口 214尺寸也較容易控制。 請參照第2D圖，接著，將暴露出的矽氧氮化物層204 臨場去除，此時調整蝕刻介電層2〇8的蝕刻氣體，選擇 CHxFy/Ar/CO爲蝕刻矽氧氮化物層206的蝕刻氣體，而 6 本紙張尺度適用中國國家標準（CNS)A)規格（2!ϋχ 297公釐） (請先閱讀背面之注意事項再填寫本頁) -^裝--------訂·-------- 4269 6 3426963 5002twfdoc / 008 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (f) The present invention relates to a method for manufacturing a semiconductor interconnect, and in particular to a via window (via ) Manufacturing method of opening. As the semiconductor size gradually advances into a process of 0.25 μm or even 0.25 μm or less, when the opening 102 is formed in the dielectric layer 100, the etching of the dielectric layer 100 uses the barrier layer 106 on the metal layer 104 as a stop layer. And proceed as shown in Figure 1. However, the etching selectivity of the silicon oxynitride layer 107 and the dielectric layer 100 covered by the C4H8 etching barrier layer 106 is not high (about 1:10), and the thickness of the barrier layer 106 is not large. In the case that the dielectric layer 100 cannot be etched on the barrier layer 106 when the dielectric layer 100 is etched, the underlying metal layer 104 is directly exposed, causing excessive etching. Excessive etching causes the exposed metal layer 104 to be sputtered, and a metal-containing polymer 108 is formed to cover the dielectric layer 100 on the side wall of the opening 102, thereby reducing the size of the bottom of the opening 102. The loss of the barrier layer 106 causes a reduction in the reliability of the device after the process is completed, and it takes more time to clean the metal-containing polymer 108, which not only increases the operation time but does not meet the cost reduction considerations. 'It also causes damage to the barrier layer 106, resulting in a decrease in product yield. Therefore, the present invention is to provide a method for manufacturing an opening of an interposer window to avoid the formation of a polymer deposited on the side wall of the bottom of the interposer window when the interposer window is etched, causing problems such as shrinkage of the opening and reduction of reliability. The present invention is to provide a method for manufacturing an interlayer window opening, which can reduce the steps of washing the wafer with a solvent in a subsequent process. The present invention provides a method for manufacturing an interstitial window opening, in a metal layer 3 (please read the precautions on the back before filling this page). The size of this paper is in accordance with A1 National Standard (C1SS) A4 specification (210 > = 297g: g) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ϊ 4 * d ^ c / 008 V. Description of Invention (v) A barrier layer and a silicon oxynitride layer are sequentially formed thereon, and then a dielectric layer is formed on the metal layer. Thereafter, a photoresist is used and a silicon oxynitride layer is used as an etch stop layer, and an opening is formed in the dielectric layer to expose the silicon oxynitride layer. Continue to remove the photoresist, and then use the barrier layer as the etch stop layer to remove the silicon oxynitride layer. Among them, when the dielectric layer is etched, C ^ Fs / Ar / CO etchant is passed in the plasma reaction chamber, and when removing the silicon oxynitride layer, a mixed gas of CHxFy / Ar / CO is used, so the etching barrier is The layer and the silicon oxynitride layer have a high etching selection ratio, so that the etching step can be stopped at the barrier layer smoothly. At the same time, when removing the photoresist, unnecessary polymer deposition can be removed at the same time, and in subsequent processes, only deionized water can be used for rinsing, which not only saves operation time, avoids corrosion of barrier metal, but also reduces costs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1 A sectional view showing a conventional via window opening: and FIGS. 2A-2D are sectional views showing a manufacturing process of the via window opening according to a preferred embodiment of the present invention. Among them, a brief description of each icon number is as follows: 100, 208: dielectric layer 102, 212: opening 104, 202: metal layer 106, 204: barrier layer 4 ------------- I ----- Order --------- line (please read the notes on the back before filling this page) This paper size applies to Chinese national standards Printed by the cooperative 4 269 6 3 ^ 5002twf.doc / 008 B7 ---------------------------- V. Description of the invention (3) 108: Bureau molecule 200: Substrates 107, 206: sand oxynitride layer 210: photoresist 214: interlayer window opening. A preferred embodiment of the present invention utilizes a high etching selectivity ratio of a silicon oxynitride layer and a barrier layer. The etching step of the electrical layer can be stopped at the barrier layer, so the underlying metal layer will not be exposed, so it will not cause damage to the metal layer, and it can avoid the formation of unnecessary polymers to reduce the opening of the dielectric window. 'If there is unnecessary polymer generation, it can be removed in-situ when removing the photoresist, and at the same time, the step of washing the wafer with the solution can be omitted in the subsequent process, so the cost can be saved. In this way, the damage of the barrier layer by the solvent is reduced. Figures 2A-2D are cross-sectional views of the manufacturing process of a via window opening according to a preferred embodiment of the present invention. Please refer to Figure 2A on a substrate 200 A metal layer 202, such as aluminum, is formed. Next, a barrier layer 204, such as a titanium / titanium nitride layer, is formed on the metal layer 202, and the thickness of the titanium nitride layer is about 200-500 angstroms. A silicon oxynitride layer 206 is formed on the barrier layer 204. For example, a chemical vapor deposition method is used to form a 'covering barrier layer 204 °'. Next, a dielectric layer 208 'is formed on the substrate 200 to cover silicon. The oxynitride layer 206 and the dielectric layer 208 are, for example, silicon dioxide. Thereafter, a photoresist layer 21 is formed on the dielectric layer 208, and the photoresist layer is formed in a predetermined opening of the dielectric window after the lithography process. An opening is formed at the position 212 'Exposed ------------ Installation -------- Order --------- line, (Please read the precautions on the back before (Fill in this page) The K degree of this paper applies the Chinese national standard specifications (2) tM 2 (J7 meal) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 69 6 3 a? 5002lwf.doc / 008 _ __B7_ 5. Description of the invention (d) Partial dielectric layer 208 is shown * as shown in Figure 2A. Please refer to Figure 2B 'and then define the dielectric layer 208 with a photoresist 210 and use the silicon oxynitride layer 206 as an etching stop A dielectric window opening 214 is formed in the dielectric layer 208, and the silicon oxynitride layer 206 is exposed. The vertical etching profile is about 89 °. The etching process is performed by, for example, inductively coupled high-density plasma etcher. The etching gas includes C4F8, a mixed gas of Ar and CO, and C2F6. After that, a step of removing the photoresist 210 is performed, for example, by an oxygen plasma ashing method. Since the step of etching the dielectric layer 208 is stopped at the sand oxynitride layer 206, and the reaction chamber is adjusted in a low bias state, the energy of the plasma bombardment is reduced, so the plasma will not be etched in large quantities. The barrier layer 204 exposes the metal layer 202, so the plasma will not sputter the metal layer 202 and cause metal-containing polymers to accumulate on the bottom side wall of the via 214. However, during the above-mentioned etching step, there may still be metal-free polymers formed on the sidewalls of the interlayer window opening 2 or 4 or on the silicon oxynitride layer 206, and the metal-free polymers may be removed by oxygen plasma. The resistance 210 is removed in situ at the same time, which can avoid affecting the subsequent process of etching silicon oxynitride, as shown in FIG. 2C. Since no metal-containing polymer is produced, and the metal-free polymer can be removed by the oxygen plasma, there will be no polymer residue on the side wall of the interlayer window D 214 and the silicon oxynitride layer 206. Therefore, subsequent etching is performed. The manufacturing process can proceed smoothly, and the size of the via window opening 214 is also easier to control. Please refer to FIG. 2D. Next, the exposed silicon oxynitride layer 204 is removed on the spot. At this time, the etching gas for etching the dielectric layer 208 is adjusted, and CHxFy / Ar / CO is selected as the silicon oxynitride layer 206 Etching gas, and 6 paper sizes are applicable to China National Standard (CNS) A) specifications (2! Ϋχ 297 mm) (Please read the precautions on the back before filling this page)-^ 装 -------- Order ・ -------- 4269 6 3
5 0〇2t\vf. doc/OOS5 0〇2t \ vf. Doc / OOS
經濟部智慧財產局員工消費合作社印製 五、發明說明（s ) CHxFy可以是CHF3、CH2F2或CH3F等，因此可使得矽氧 氮化物層206與阻障層204的蝕刻選擇比變大，故可以阻 障層2〇4爲蝕刻終止層而使電漿僅僅蝕刻矽氧氮化物層 206。其中，阻障層204爲氮化鈦層時，矽氧氮化物層206 與氮化鈦層的蝕刻選擇比可高於20 : 1，故蝕刻矽氧氮化 物層2〇6的製程得以順利進行。之後，再對晶片表面進行 濕淸洗的步驟，由於不會生成含金屬的高分子，而不含金 屬的高分子已在去除光阻的步驟中去除，因此可省略以溶 劑淸洗的濕淸洗製程，而僅以去離子水(DI water)淸洗晶片 表面即可，故可藉以避免溶劑侵蝕阻障層204，造成元件 可靠度降低的可能性。之後，在介層窗開口 2H中塡入導 電材料，則完成介層窗（未繪出）。 本發明係以C4FS、Ar與CO之混合氣體對介電層進行 蝕刻，而以CHxFy/Ar/CO對矽氧氮化物層進行蝕刻，因此 在蝕刻劑對矽氧氮化物層與阻障層具有較大的蝕刻選擇 比之下’蝕刻步驟可以停止在阻障層，故可避免金屬層暴 露出而濺鍍，使介層窗開口的尺寸可獲得較佳的控制。 另外，在去除光阻的步驟中可臨場去除高分子，故可 減少後續溶劑淸洗的步驟，避免阻障層的損害，故可提高 元件的可靠度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 衣紙張&度適用中國國家標準（CNWAI規格（21ϋ χ 297公釐） ----------- €-----丨訂------ 線 .. (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (s) CHxFy can be CHF3, CH2F2, or CH3F, etc. Therefore, the etching selectivity ratio between the silicon oxynitride layer 206 and the barrier layer 204 can be increased, so The barrier layer 204 is an etch stop layer so that the plasma etches only the silicon oxynitride layer 206. Wherein, when the barrier layer 204 is a titanium nitride layer, the etching selection ratio of the silicon oxynitride layer 206 to the titanium nitride layer may be higher than 20: 1, so the process of etching the silicon oxynitride layer 206 can be smoothly performed. . After that, the wafer surface is subjected to a wet cleaning step. Since metal-containing polymers are not generated, and metal-free polymers have been removed in the step of removing photoresist, the wet cleaning with solvent cleaning can be omitted. During the washing process, only the surface of the wafer is rinsed with DI water, so that the barrier layer 204 may not be attacked by the solvent, which may reduce the reliability of the device. After that, a conductive material is inserted into the opening 2H of the interlayer window to complete the interlayer window (not shown). In the present invention, the dielectric layer is etched with a mixed gas of C4FS, Ar, and CO, and the silicon oxynitride layer is etched with CHxFy / Ar / CO. Therefore, the silicon oxynitride layer and the barrier layer are etched with an etchant. With a larger etching selection ratio, the etching step can be stopped at the barrier layer, so the metal layer can be prevented from being exposed and sputtered, so that the size of the opening of the via can be better controlled. In addition, the polymer can be removed on-site in the step of removing the photoresist, so that subsequent solvent washing steps can be reduced, and damage to the barrier layer can be avoided, so that the reliability of the device can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Applicable to Chinese national standard (CNWAI specification (21ϋ χ 297 mm)) ----------- € ----- 丨 Order ------ Thread .. (please first (Read the notes on the back and fill out this page)