TW426926B - Integrated circuit package - Google Patents
Integrated circuit package Download PDFInfo
- Publication number
- TW426926B TW426926B TW088117266A TW88117266A TW426926B TW 426926 B TW426926 B TW 426926B TW 088117266 A TW088117266 A TW 088117266A TW 88117266 A TW88117266 A TW 88117266A TW 426926 B TW426926 B TW 426926B
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- package
- heat dissipation
- integrated circuit
- leads
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
τ 426926 五、發明說明（1) ' 發明u t明之镅Μ 本發明係關於一種積體電路封裝，特別是關於—種塑 *四列扁平封裝’其可增進元件之電特性。 、+為防止積體電路受外力或環境因素所導致的破壞，故 必需以適當方法予以封裝。此封裝包含半導體晶粒與引線 框（leadf rame)的結合、打線接合、及密封保護等。 積體電路會消耗大量功率而產生大量的熱能，一旦溫 度達到積體電路的操嗓上限時，其性能將大大地減低。此 外’於高溫下操作的i體電路，其穩定度及壽命均會減 低’甚至導致其操作速度下降、及其它不理想等操作特 性。因此’積體電路所產生的熱能必需能夠有效率地散 熱。 以下首先參考圖1說明習用的四列扁平封裝（(luad ilat package ’ QFP) 1〇〇。此qfp 1〇〇包含一模製塑膠包封 體1 0 1、一引線框，其具有一晶粒焊墊1丨〇及複數引線 102、一半導體晶粒1〇3、一層黏合劑1〇4用以結合半導體 晶粒103與晶粒焊墊11〇、及複數接合線（b〇nding wires) 111。由於現今及未來世代的積體電路係以高速運作而須 消耗大量功率，但QFP 100並不具有優良的散熱性，，由 此可知*QFP 100並不適合用於封裝現今或未來世代的積 體電路。 現今已發展出一種散熱加強型的QFp( thermal lyτ 426926 V. Description of the invention (1) 'Invention u t 明明 镅 This invention relates to an integrated circuit package, and more particularly to a kind of plastic * four-row flat package' which can improve the electrical characteristics of components. In order to prevent the integrated circuit from being damaged by external forces or environmental factors, it must be encapsulated by an appropriate method. This package includes the combination of semiconductor die and lead frame, wire bonding, and seal protection. The integrated circuit consumes a lot of power and generates a lot of thermal energy. Once the temperature reaches the upper limit of the integrated circuit's voice, its performance will be greatly reduced. In addition, i-body circuits that operate at high temperatures will have reduced stability and lifespan, and may even cause their operating speed to decrease, and other undesirable operating characteristics. Therefore, the thermal energy generated by the 'integrated circuit must be able to dissipate heat efficiently. The following first describes a conventional four-row flat package ((luad ilat package 'QFP) 100) with reference to FIG. 1. This qfp 100 includes a molded plastic encapsulation body 101 and a lead frame having a die. The pads 1 and 10 and the plurality of leads 102, a semiconductor die 103, a layer of adhesive 104 are used to combine the semiconductor die 103 with the die pads 110, and a plurality of bonding wires 111 .Since the integrated circuits of today and future generations need to consume a lot of power at high speed, but QFP 100 does not have excellent heat dissipation, it can be seen that * QFP 100 is not suitable for packaging current or future generation of integrated circuits. Circuit. A thermally enhanced QFp (thermally ly
第5頁 426926 五、發明說明（2) enhanced QFP)，此種QFP可允許積體電路在高速及高功率 下運作。圖2顯示一習用的散熱加強型Qi?p 200 »此散熱加 強型QFP 200與典型的QFP 100同樣具有：一模製塑膠包封 體201、一引線框’其具有一晶粒焊墊210及複數引線 202、一半導體晶粒203、一層黏合劑204用以結合半導體 晶粒203與晶粒焊墊210、及複數接合線211。此外，散熱 加強型QFP 200也包含一去入式散熱元件（drop-in heat spreader)212，其結合至晶粒焊墊210與晶粒203結合面相 反的表面上。此丟入式散熱元件212具有複數支撐腳 (support legs)213，其外表面露出於周遭空氣中。因 此’晶粒203所產生的熱可經由丟入式散熱元件212而流通 至模製塑膠包封體201及散發至周遭空氣中。 使用丢入式散熱元件212的優點為製程簡單，因為不 需加入額外的製程步驟來黏合散熱元件212與晶粒焊墊 210 ’故其製造成本低。然而，圖2所示之QFP 20 0中，為 避免散熱元件212與内部引線2〇5(引線102位於模製塑膠包 封體20 1内的部分）之間的短路，故必需將二者保持一定的 距離。由於散熱元件212與内部引線205之間無法太過接 近，故散熱元件2 12僅能提供有限的散熱效果，並無提供 改善QFP 200之電特性的正面影響。 發明概要 本發明的一目的為提供一種四列扁平封裝，其可增進 元件的電特性。Page 5 426926 V. Description of the invention (2) enhanced QFP) This QFP allows integrated circuits to operate at high speed and high power. Figure 2 shows a conventional thermally enhanced Qi? P 200 »The thermally enhanced QFP 200 has the same characteristics as a typical QFP 100: a molded plastic encapsulation body 201, a lead frame, which has a die pad 210 and The plurality of leads 202, a semiconductor die 203, and a layer of adhesive 204 are used to combine the semiconductor die 203 with the die pad 210, and a plurality of bonding wires 211. In addition, the thermally enhanced QFP 200 also includes a drop-in heat spreader 212 which is bonded to the surface of the die pad 210 opposite to the bonding surface of the die 203. The drop-in heat dissipation element 212 has a plurality of support legs 213, and its outer surface is exposed to the surrounding air. Therefore, the heat generated by the 'crystal grains 203 can be circulated to the molded plastic encapsulation body 201 and dissipated to the surrounding air through the throw-in heat dissipation element 212. The advantage of using the drop-in heat dissipation element 212 is that the manufacturing process is simple, because no additional process steps need to be added to bond the heat dissipation element 212 and the die pad 210 ', so the manufacturing cost is low. However, in the QFP 20 0 shown in FIG. 2, in order to avoid a short circuit between the heat dissipation element 212 and the internal lead 205 (the part of the lead 102 located in the molded plastic encapsulation body 20 1), it is necessary to keep the two. A certain distance. Since the heat-dissipating element 212 and the internal lead 205 cannot be too close, the heat-dissipating element 212 can only provide a limited heat-dissipating effect, and does not provide a positive impact on improving the electrical characteristics of the QFP 200. SUMMARY OF THE INVENTION An object of the present invention is to provide a four-row flat package which can improve the electrical characteristics of a device.
426926426926
本發明所揭露的四列扁平封裝 内部引線之間的距離大大縮小。結 使内部引線的電感值下降至少 四列扁平封裝的電特性。 此外’由於本發明的四列扁平 以降低其製造成本。 八本發明的第一實施態樣提供一 3 . 一引線框，其具有一晶粒焊塾 焊墊具有一第一主表面及位在第一 中，可以將散熱元件與 果，此距離的縮小可以 因此，可以大大改善 封裝的製程簡單，故可 主表面；一晶粒 散熱元件，其包 晶粒焊塾 面結合於 面的至少 數引線的 的積體電 裝。本發 緣材料包 之第一實 的絕緣材 本發 一部分塗 短路。具 路封裝中 明之第一 含聚酿亞 施態樣的 料可以實 明的第二 ，其結 含至少 的第二 覆有絕 體來說 ，此封 實施態 胺樹脂 積體電 質上與 實施態 合於晶粒 一支撐腳 主表面， 緣材料， ，在依照 裝可以為 樣的積體 、或環氧 路封裝中 複數引線 種積體電路 及複數引線 主表面之相 焊墊的第一 ’且此散熱 其中在散熱 用以防止散 本發明之第 一種塑膠四 電路封裝中 樹脂等。此 ，散熱元件 的一部分互 封裝，其包 ，其中晶粒 反側的一第 主表面；及 元件的第一 元件的第一 熱元件與複 一實施態樣 列扁平封 所使用的絕 外，本發明 的第一面上 相接觸。 封裝，其包 ’其中晶粒 反側的一第 晶粒’其結合於晶粒焊墊的第一主表面；及 其包含至少一支樓腳’且此散熱元件的第一 樣提供一 晶粒焊墊 含：一引線框，其具有 焊墊具有一第一主表面及位在第 種積體電路 及複數引線 主表面之相 主表面， 散熱元件The distance between the inner leads of the four-row flat package disclosed in the present invention is greatly reduced. The junction reduces the inductance of the internal leads by at least the electrical characteristics of the four-row flat package. In addition, the four rows of the present invention are flat to reduce the manufacturing cost. Eighth, a first embodiment of the present invention provides a lead frame having a die-bonding pad having a first main surface and located in the first, which can reduce heat dissipation components and fruits, and reduce the distance. Therefore, the packaging process can be greatly improved, and the main surface can be greatly improved. A die heat dissipation component including a chip assembly with at least several leads bonded to the die bonding surface and the surface. The first solid insulating material in the hairpin material package is partially short-circuited. In the package, the first material containing the poly-vinyl alcohol-containing material can be the second material, and the material containing at least the second material is covered with an insulator. In this case, the amine resin body is electrically and practically implemented. The first surface of the die-support foot, the edge material, the first lead of the multiple-lead-type integrated circuit and the main lead of the multiple-lead phase in the package that can be sampled or the epoxy circuit package. And this heat dissipation is used to prevent the resin in the first plastic four-circuit package of the present invention from dissipating heat. Therefore, a part of the heat dissipation element is mutually packaged, and the package includes a first main surface on the opposite side of the die; and the first heat element of the first element of the element and the flat sealing package used in the multiple embodiment of the present invention. The first side of the invention is in contact. A package, which includes a first die on the opposite side of the die, which is bonded to the first major surface of the die pad; and a package that includes at least one leg, and the first heat sink provides a die. The pad includes: a lead frame having a pad having a first main surface and a phase main surface located on a first integrated circuit and a plurality of lead main surfaces, and a heat dissipation element
4269 26 五、發明說明（4) 面結合於晶粒焊墊的第二主表面，其中在散熱元件的第— 面的至少-部分置有複數隔膜，用以防止散熱元件與複數 引線的短路。 :體來說’在依照本發明之第二實施態樣的積體電路 ί裝中，此封裝可以為一種塑膠四列扁平封裝。本發明之 施態樣的積體電路封裝中所使用的複數隔膜的材料 胺=元二卜第本第二實施態樣的積趙 與複數引線"分1:;觸面上的複數隔膜可以實質上 單說明 本發明之上述及其他目的、優點和特色由以下較佳 細例之詳細說明中並參考圖式當可更加明白，其中： 圖1為顯示習用的四列扁平封裝的剖面圖；/、 圊丨圖2為顯示習用的散熱加強型四列爲平封裝的剖面 圖3為顯示本發明第一實施例之電特性详& 平封裝的剖面圖； 幵性增進型四列扁 圖4為顯示本發明第二實施例之電特性声& $ 平封裝的剖面圖； 孖性增進型四列扁 圖5為顯示用於組裝本發明之第—眘 進型四列扁平封裝之程序二㈣第及實"例之電特性增 進型ΓΛ顯示\於組裝本發日m實施例之電特性增 歹j扁平封裝之程序的流程圖。 _4269 26 V. Description of the invention (4) The surface is bonded to the second main surface of the die pad, and a plurality of diaphragms are arranged on at least part of the first surface of the heat dissipation element to prevent short circuit between the heat dissipation element and the plurality of leads. : Speaking of the body 'In the integrated circuit according to the second embodiment of the present invention, the package may be a plastic four-row flat package. The material of the plurality of diaphragms used in the integrated circuit package of the embodiment of the present invention is amine = the product of the second embodiment of the second embodiment and the plurality of leads " point 1: the contact surface of the multiple diaphragm can be Essentially, the above and other objects, advantages, and features of the present invention will be more clearly understood from the following detailed description of the preferred examples with reference to the drawings, wherein: FIG. 1 is a cross-sectional view showing a conventional four-row flat package; / 、 圊 丨 FIG. 2 is a cross-sectional view showing a conventional heat-reinforced four-row flat package, and FIG. 3 is a cross-sectional view showing details of the electrical characteristics of the first embodiment of the present invention. 4 is a cross-sectional view showing the electrical characteristics of the second embodiment of the present invention & $ flat package; flatness-enhancing four-column flat FIG. 5 is a procedure for assembling the first-careful four-column flat package of the present invention The electric characteristic enhancement type ΓΛ of the second embodiment is shown in the flowchart of the procedure for assembling the electric characteristic enhancement of the embodiment of the present invention and the flat package. _
^ 426926 五、發明說明（5) 符號說明 100 四 列 扁 平 封 裝 101 模 製 塑 膠 包 封 體 102 引 線 103 半 導 tub 體 晶 粒 104 黏 合 劑 110 晶 粒 焊 墊 111 接 合 線 200 四 列 扁 平 封 裝 201 模 製 塑 膠 包 封 體 202 引 線 203 晶 粒 204 黏 合 劑 205 内 部 引 線 210 晶 粒 焊 墊 211 接 合 線 212 散 熱 元 件 213 支撐 腳 300 四 列 扁 平 封 裝 301 模 製 塑 膠 包 封 體 302 引 線 303 晶 粒 304 黏 合 劑^ 426926 V. Description of the invention (5) Symbol description 100 Four-column flat package 101 Molded plastic encapsulation body 102 Lead 103 Semiconducting tub body die 104 Adhesive 110 Die pad 111 Bonding wire 200 Four-row flat package 201 mold Plastic encapsulation body 202 lead 203 die 204 adhesive 205 internal lead 210 die pad 211 bonding wire 212 heat sink 213 support foot 300 four-row flat package 301 molded plastic encapsulation body 302 lead 303 die 304 adhesive
五、發明說明（6) 3 0 5 内部引線 310 晶粒焊墊 311 接合線 312 散熱元件 313 支撐腳 314 絕緣材料 400 四列扁平封裝 401 模製塑膠包封體 402 引線 4 0 3 晶粒 4 0 4 黏合劑 405 内部引線 410 晶粒焊墊 411 接合線 412 散熱元件 413 支撐腳 414 隔膜 414 絕緣材料 較佳實施例之詳細說明 以下參考圖3說明本發明第一實施例的電特性增進型 QFP 300 。 如圖3所示，本發明第一實施例的電特性增進型QFP 3 0 0與習知的散熱加強型QFP 2 0 0同樣具有：一模製塑膠包V. Description of the invention (6) 3 0 5 Internal leads 310 Die pads 311 Bonding wires 312 Heat dissipation elements 313 Support feet 314 Insulation material 400 Four-row flat package 401 Molded plastic encapsulation body 402 Leads 4 0 3 Die 4 0 4 Adhesive 405 Internal lead 410 Die pad 411 Bonding wire 412 Heat dissipation element 413 Supporting leg 414 Diaphragm 414 Detailed description of a preferred embodiment of an insulating material The following describes a QFP 300 with improved electrical characteristics according to a first embodiment of the present invention with reference to FIG. 3 . As shown in FIG. 3, the electrical characteristic-enhancing QFP 3 0 0 of the first embodiment of the present invention and the conventional thermally enhanced QFP 2 0 0 also have: a molded plastic bag
第10頁 426926 五、發明說明（7) 封體301、一引線框，其具有一晶粒焊墊31()及複數引線 302、一半導體晶粒3〇3、一層黏合劑3〇4用以結合半導體 晶粒303與晶粒焊墊31〇、複數接合線311、及一丟入式散 熱兀件312 ’其結合於晶粒焊墊31〇之與半導體晶粒3〇3結 合面相反的表面上。此丢入式散熱元件312具有複數支撐 腳313 ’其外表面露出於周遭空氣中。因此，晶粒3〇3所產 生的熱可經由吾入式散熱元件312而流通至模製塑膠包封 體301及散發至周遭空氣中。 本發明第一實施例的電特性增進型qFP 3〇〇與習知的 散熱加強型QFP 200的相異處在於：丟入式散熱元件312的 上方塗覆有一層絕緣材料’，如圖3所示，層絕緣材料係 用以防止散熱元件312與内部引線3〇5之間的短路。由於此 層絕緣材料314的塗覆，使得散熱元件31 2與内部引線3 (引線30 2位於模製塑膠包封體3〇ι内的部分）之間的距離可 以保持於較習知之QFP 200者更小的距離。因此，由於散 熱元件31 2與内部引線3 0 5之間的距離較小，故散熱元件 312能有效減低内部引線305的電感值，達到電感值下降約 20%。因此，散熱元件312可以大大地增進QFp 3〇〇的電特 性。 本發明第一實施例之電特性增進型QFp 3〇〇中，所使， 用的絕緣材料31 4可以是任何適用的介電材料例如聚醯亞 胺樹脂（polyimide resin)、環氧樹脂（ep〇xy resin)等。 此外’顯然可以將本發明第一實施例的散熱元件3丨2與内 部引線305再進一步縮小距離，甚至使絕緣材料314實質上Page 10 426926 V. Description of the invention (7) A sealing body 301, a lead frame, which has a die pad 31 () and a plurality of leads 302, a semiconductor die 303, and a layer of adhesive 304 for The semiconductor die 303 is combined with the die pad 31o, a plurality of bonding wires 311, and a drop-type heat dissipation element 312 ', which is bonded to the surface of the die pad 31o opposite to the bonding surface of the semiconductor die 303. on. The drop-in heat dissipation element 312 has a plurality of supporting legs 313 'whose outer surfaces are exposed to the surrounding air. Therefore, the heat generated by the die 303 can be circulated to the molded plastic encapsulation body 301 through the self-contained heat dissipation element 312 and dissipated to the surrounding air. The difference between the electrical characteristic-enhancing qFP 300 of the first embodiment of the present invention and the conventional heat radiation-enhanced QFP 200 is that a layer of insulating material is coated on top of the drop-type heat dissipation element 312, as shown in FIG. As shown, the layer of insulating material is used to prevent a short circuit between the heat dissipation element 312 and the internal lead 305. Due to the coating of this layer of insulating material 314, the distance between the heat dissipating element 31 2 and the inner lead 3 (the part of the lead 30 2 located in the molded plastic encapsulation body 30) can be maintained at a more familiar QFP 200 Smaller distance. Therefore, since the distance between the heat dissipating element 31 12 and the internal lead 305 is small, the heat dissipating element 312 can effectively reduce the inductance value of the internal lead 305, and the inductance value decreases by about 20%. Therefore, the heat dissipation element 312 can greatly improve the electrical characteristics of QFp 300. In the QFp 300 with improved electrical characteristics of the first embodiment of the present invention, the insulating material 314 used may be any suitable dielectric material such as polyimide resin, epoxy resin (ep Xy resin). In addition, it is obvious that the distance between the heat dissipation element 3 丨 2 and the internal lead 305 of the first embodiment of the present invention can be further reduced, and even the insulating material 314 is substantially
第11頁 426926 五、發明說明（8) 與内部引線305互相接觸，此可更進—步增進QFp 的電 特性。 以下參考圖4說明本發明第二實施例的電特性增進型 QFP 400 。 如圖4所示，本發明第二實施例的電特性增進型QFp 400與本發明第一實施例的QFP 3〇〇同樣具有：一模製塑膠 包封體401、一引線框，其具有一晶粒焊墊41〇及複數引線 402、一半導體晶粒403、一層黏合劑404用以結合半導體 晶粒403與晶粒焊墊410、複數接合線4Π、及一丟入式散 熱元件412，其結合於晶粒焊墊41〇之與半導體晶粒4〇3結 合面相反的表面上《此丟入式散熱元件412具有複數支樓 腳413 ’其外表面露出於周遭空氣中。因此，晶粒jog所產 生的熱可經由丟入式散熱元件412而流通至模製塑穆包封 體401及散發至周遭空氣中。 本發明第二實施例的QFP 400與本發明第一實施例的 QFP 300的相異處在於：丟入式散熱元件412的上方置有一 層隔膜（spacer)414，如圖4所示，此層隔膜係用以防止散 熱元件412與内部引線405之間的短路。由於此層隔膜414 的存在，使得本發明之QFP 400的散熱元件412與内部引線 405 (引線402位於模製塑膠包封體401内的部分）之間的距 離可以保持於較習知之QFP 200者小的距離。因此，由於 散熱元件412與内部引線405之間的距離較小，故散熱元件 41 2能有效減低内部引線4 0 5的電感值，達到電感值下降約 20%。因此’散熱元件412可以在避免短路的情況下，大大Page 11 426926 V. Description of the invention (8) The inner leads 305 are in contact with each other, which can further improve the electrical characteristics of QFp. Hereinafter, a QFP 400 with improved electrical characteristics according to a second embodiment of the present invention will be described with reference to FIG. 4. As shown in FIG. 4, the QFp 400 with improved electrical characteristics of the second embodiment of the present invention is the same as the QFP 300 of the first embodiment of the present invention: a molded plastic encapsulation body 401, a lead frame, which has a The die pad 41 and the plurality of leads 402, a semiconductor die 403, a layer of adhesive 404 are used to combine the semiconductor die 403 and the die pad 410, a plurality of bonding wires 4Π, and a drop-type heat dissipation element 412. The surface of the die bonding pad 41o, which is opposite to the bonding surface of the semiconductor die 403, has a plurality of legs 413 ', and its outer surface is exposed to the surrounding air. Therefore, the heat generated by the die jog can be circulated to the molded plastic encapsulation body 401 and dissipated to the surrounding air through the throw-away heat dissipation element 412. The difference between the QFP 400 according to the second embodiment of the present invention and the QFP 300 according to the first embodiment of the present invention lies in that: a layer of a spacer 414 is placed above the throw-in heat dissipation element 412, as shown in FIG. 4, this layer The diaphragm is used to prevent a short circuit between the heat dissipation element 412 and the inner lead 405. Due to the existence of this layer of membrane 414, the distance between the heat dissipation element 412 of the QFP 400 of the present invention and the internal lead 405 (the part of the lead 402 located in the molded plastic encapsulation body 401) can be maintained at a more familiar QFP 200 Small distance. Therefore, since the distance between the heat dissipating element 412 and the inner lead 405 is small, the heat dissipating element 412 can effectively reduce the inductance value of the inner lead 405, and the inductance value decreases by about 20%. Therefore, the heat dissipation element 412 can greatly
第12頁 426926Page 12 426926
五、發明說明 地增進QFP 400的電特性。 本發明第二實施例之電特性增進型QFP 400中，所使 用，隔琪414可以是任何適用的介電材料例如聚酿亞胺等 所製造的介電膜。此外’顯然可以將本發明第—實施例的 散熱几件412與内部引線4〇5再進一步縮小距離，甚至使隔 膜414實質上與内部引線4〇5互相接觸，此可更進一步押進 QFP 400的電特性。 曰 圖5為顯示用於組裝本發明第—實施例之電特性增進 型四列扁平封裝之程序的流程圖β在步驟5 〇工中，將具有 複數半導體晶粒的一晶片切割成個別的半導體晶粒。在步 驟502中，提供一引線框。在步驟5〇3中，將一半導體晶粒 結合至引線框的晶粒焊墊上。在步驟5〇4中，進行打線接 合，即，以金屬線將晶粒及引線框的引腳接合。在步驟 5〇5中提供一散熱元件。在步驟5〇6中，以絕緣材料塗覆 於散熱元件上方》在步驟5〇7中，將已塗覆絕緣材料的散 熱元件丟入模製腔中。在步驟5〇8中，將已結合半導體晶 粒的引線框也置入模製腔中，並以塑膠模製化合 ^(encapsulate),而使引線框之引腳的一部分突出在模 製化合物外面。此步驟50 8也包含進行封裝的固化。在步 驟5 09中’進行引腳的電鍍，以防止其氧化。在步驟5〇8 中’進行個別的封裝的分離（singulati〇n)，即在模製之 後將相鄰引線框間的引腳切斷。 、 圖6為顯示用於組裝本發明之第二實施例之電特性增 進型四列扁平封裝之程序的流程圖。在步驟6〇1中，將具V. Description of the invention To improve the electrical characteristics of QFP 400. In the QFP 400 having improved electrical characteristics according to the second embodiment of the present invention, the spacer 414 may be a dielectric film made of any suitable dielectric material such as polyimide. In addition, it is obvious that the heat-dissipating pieces 412 of the first embodiment of the present invention and the internal lead 405 can be further reduced in distance, and even the diaphragm 414 substantially contacts the internal lead 405, which can be further pushed into the QFP 400. Electrical characteristics. FIG. 5 is a flowchart showing a procedure for assembling a four-row flat package with improved electric characteristics according to the first embodiment of the present invention. In step 50, a wafer having a plurality of semiconductor dies is cut into individual semiconductors. Grain. In step 502, a lead frame is provided. In step 503, a semiconductor die is bonded to the die pad of the lead frame. In step 504, wire bonding is performed, that is, the die and the lead of the lead frame are bonded with a metal wire. A heat dissipation element is provided in step 505. In step 506, an insulating material is applied over the heat-dissipating element. In step 507, the heat-dissipating element that has been coated with an insulating material is thrown into the molding cavity. In step 508, the lead frame that has been combined with the semiconductor die is also placed in the molding cavity, and encapsulate is molded with plastic, so that a part of the lead frame pins protrude out of the molding compound. . This step 508 also includes curing the package. In step 509, the leads are plated to prevent oxidation. In step 508 ', the individual packages are separated (singulati), that is, the pins between adjacent lead frames are cut off after molding. Fig. 6 is a flowchart showing a procedure for assembling an electric characteristic-increasing four-row flat package of the second embodiment of the present invention. In step 6〇1, will have
第13頁 1 426926Page 13 1 426926
有複數半導體晶粒的一晶片切割成個別的半導體晶粒。在 步驟602巾’棱供—引線框。纟步驟中將一半導體晶 粒結合至引線框的晶粒焊墊上。在步驟6〇4中，進行打線 接合，即，以金屬線將晶粒及引線框的引腳接合。在步驟 605中，k供一散熱元件。在步戰6Q6中，將一隔膜放置於 散熱元件上方。在步驟6〇7中，將具有隔膜的散熱元件丟 入模製腔中。在步驟608中，將已結合半導韹晶粒的引線 框也置入模製腔中’並以塑膠模製化合物將之包封，而使 引線框之引腳的一部分突出在模製化合物外面。此步驟 608也包含進行封裝的固化。在步驟6〇9中，進行引腳的電 鍍’以防止其氧化。在步驟608中，進行個別的封裝的分 離。 以上所述者，僅為了用於方便說明本發明之較佳實施 例’而並非將本發明狹義地限制於該較佳實施例^凡依本 發明所做的任何變更，皆屬本發明申請專利之範圍。例 如，絕緣材料314塗覆於散熱元件312上的範圍，只要能達 到防止散熱元件312與内部引線305之間產成短路即可，故 將絕緣材料314塗覆於散熱元件312的整個表面並非必要。 同理，隔膜41 4所放置的範園也與絕緣材料31 4的情況相 同。A wafer having a plurality of semiconductor dies is cut into individual semiconductor dies. In step 602, the lead frame is provided. In the step (i), a semiconductor wafer is bonded to a die pad of the lead frame. In step 604, wire bonding is performed, that is, the die and the lead of the lead frame are bonded with a metal wire. In step 605, k is provided as a heat dissipation element. In Step 6Q6, a diaphragm is placed above the heat sink. In step 607, the heat-radiating element with the diaphragm is dropped into the molding cavity. In step 608, the lead frame that has been combined with the semiconductor chip is also placed in the molding cavity and is encapsulated with a plastic molding compound, so that a part of the lead frame pins protrude outside the molding compound. . This step 608 also includes curing the package. In step 609, electrode plating is performed to prevent oxidation. In step 608, the individual packages are separated. The above is only for the convenience of describing the preferred embodiment of the present invention, and is not intended to limit the present invention to the preferred embodiment narrowly. Any changes made in accordance with the present invention are patents of the present invention. Range. For example, the range in which the insulating material 314 is coated on the heat dissipation element 312 is only required to prevent a short circuit between the heat dissipation element 312 and the internal lead 305, so it is not necessary to coat the entire surface of the heat dissipation element 312 with the insulating material 314. . Similarly, the fan garden where the diaphragm 41 4 is placed is also the same as that of the insulating material 31 4.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088117266A TW426926B (en) | 1999-10-05 | 1999-10-05 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088117266A TW426926B (en) | 1999-10-05 | 1999-10-05 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW426926B true TW426926B (en) | 2001-03-21 |
Family
ID=21642523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088117266A TW426926B (en) | 1999-10-05 | 1999-10-05 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW426926B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602050B2 (en) | 2005-07-18 | 2009-10-13 | Qualcomm Incorporated | Integrated circuit packaging |
| US10063024B2 (en) | 2015-06-01 | 2018-08-28 | Foxconn Interconnect Technology Limited | Electrical connector having improved insulative housing |
-
1999
- 1999-10-05 TW TW088117266A patent/TW426926B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7602050B2 (en) | 2005-07-18 | 2009-10-13 | Qualcomm Incorporated | Integrated circuit packaging |
| US10063024B2 (en) | 2015-06-01 | 2018-08-28 | Foxconn Interconnect Technology Limited | Electrical connector having improved insulative housing |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10734250B2 (en) | Method of manufacturing a package having a power semiconductor chip | |
| US7061080B2 (en) | Power module package having improved heat dissipating capability | |
| TWI323506B (en) | Packaged device | |
| US7323769B2 (en) | High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package | |
| US6133634A (en) | High performance flip chip package | |
| JP6509885B2 (en) | DC-DC converter having terminal of semiconductor chip | |
| KR101208332B1 (en) | Clip structure for semiconductor package and a semiconductor package using the same | |
| US7221055B2 (en) | System and method for die attach using a backside heat spreader | |
| US8013440B2 (en) | Enhanced thermal dissipation ball grid array package | |
| US10727151B2 (en) | Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package | |
| US7944044B2 (en) | Semiconductor package structure having enhanced thermal dissipation characteristics | |
| JPH08213536A (en) | Down set lead-frame having semiconductor-die attaching pad exposed to one-surface of package,and its manufacture | |
| JPH07169882A (en) | Molded integrated circuit package | |
| JPH0677357A (en) | Improved semiconductor package, improved method for packaging of integrated circuit device and method for cooling of semiconductor device | |
| US9397018B2 (en) | Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit | |
| JP2982126B2 (en) | Semiconductor device and manufacturing method thereof | |
| WO2006002158A2 (en) | Semiconductor package having integrated metal parts for thermal enhancement | |
| US9117786B2 (en) | Chip module, an insulation material and a method for fabricating a chip module | |
| JPH03268351A (en) | Semiconductor device | |
| US20140374891A1 (en) | Semiconductor device with heat spreader and thermal sheet | |
| TW426926B (en) | Integrated circuit package | |
| US20130001758A1 (en) | Power Semiconductor Package | |
| TWI399837B (en) | Semiconductor device and method for manufacturing a semiconductor device | |
| TW201131722A (en) | Package for semiconductor devices | |
| JPH0338057A (en) | Flagless lead frame, and package using it, and manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |