A： B* 五、發明説明（ 技術領域·’ 經濟部中央梯準局員工消f合作社印掣 本發明是有關一種使用雙線圈感應耦合電漿蝕刻反應 室製造積體電路的方法，特別是有關於一種在雙線圈感應 耦合電漿蝕刻反應室之中，調整積體電路之絕對尺寸均勻 度的方法。 發明背景： 在現行積體電路的製造技術之中，所使用的積體電路 基底為六吋或八吋矽晶圓，整個面積相當的大，因此’在 各種製程技術中，必須注意到整個矽晶圓上所有半導體元 件的製造情況。舉例來說，在膜層的電漿蝕刻製程，在矽 晶圓中央與邊緣，會因為電漿密度的不同，而具有不同的 触刻速率。依照一般半導體姓刻設備的結構設計’在《夕晶-圓中央的電漿，比起在矽晶圓邊緣上的電漿，具有較大的 密度，使得矽晶圓的中央區域與邊緣區域具有不同的蝕刻 速率。依照上述的情況，在積體電路製造的蝕刻製程中， 會因為蝕刻速率不均勻的緣故，造成半導體元件製造的不 確定性。例如在二氧化矽層甲形成接觸窗的蝕刻製程中， 對利用電漿蝕刻二氧化矽層，而因為電漿密度不均勻的原 因，造成中央區域的渠溝與邊緣區域的渠溝，具有不同的 姓刻深度（Etching depth)。 先 閱 讀 背 1¾ 之 注 jk- 事. 項 填 % 本 頁 本紙張尺度適用中國國家標隼（CNS ) A4规格（210X297公荩） 經濟部中央樣準局負工消f合作社印^ 厶269'2 . A7______ B7五、發明説明（） 以下將參考第一圖至第三圖，說明蝕刻二氧化矽層以 形成接觸窗的製程，解釋因電漿密度不均勻造成蝕刻深度 不同的情況。請參閱第一圖，提供一半導體基材100，作 為積體電路的基底，接著在半導體基材100上形成二氧化 矽層110,作為積體電路的絕緣材料或介電材料，然後形 成一底部抗反射塗覆（Bottom antireflective coating, BARC)120覆蓋在二氧化矽層110的表面。形成一光阻圖 案130，覆蓋在底部抗反射塗覆120之上，並曝露出欲蝕 刻的底部抗反射塗覆120區域。 請參閱第二圖，使用電漿蝕刻製程，蝕刻底部抗反射 塗覆120’曝露出二氧化矽層110的表面。請參閱第三圖， 使用電漿蝕刻製程，蝕刻二氧化矽層110，在二氧化矽層 110之中形成接觸孔，形成半導體基材100的接觸孔。在 第三圖的剖面示意圖之中，中央接觸孔140與邊緣接觸孔 150形成在二氧化矽層110之中。依照習知的電漿蝕刻技 術而言’由於中央區域具有較高的電漿密度，在中央區域 會具有較高的蝕刻速率，所以中央接觸孔140的蝕刻深度 B1，會大於邊緣接觸孔150的蝕刻深度B2。因此，利用 習知的電漿蝕刻技術，進行積體電路的蝕刻製程，會造成 矽晶圓之中央區域與邊緣區域具有不同的蝕刻深度。 根據先進的半導體電漿蝕刻設備的設計，在電漿蝕刻 設備之中使用三個電漿功率源，一個偏壓電漿功率源裝設 —____ 3本紙張尺度適用令國國榡準（CNS〉Λ4規樁（210x297公~ (对先閱讀背而之注意事項再填“Η本頁) 訂 A2B9 A 2 · AT H7 五、發明説明（） 在反應室的底部，另兩個電漿功率源為内側電漿功率源與 外侧電漿功率源，裝設在反應室的上方，用來調整反應室 之中的電漿密度。 請參閱第四圖，顯示半導體電漿蝕刻設備的剖面示意 圖，整個電漿蝕刻設備為一個反應室主體200，在反應室 主體200的上方具有一個加熱裝置205，對反應室主體200 進行加熱動作。在加熱裝置205的上方具有一個冷卻裝置 206，用來冷卻整個反應室主體200。在反應室主體200的 下方具有一個靜電吸盤250，在電漿蝕刻製程中’用來放 置矽晶圓。在此電漿蝕刻設備之中，一直流偏壓源210連 接於靜電吸盤250，而一地線230連接反應室主體200， 一内側功率源221連接在反應室主體200的中央區域，一 外側功率源220連接在反應室主體200的邊緣區域。在進 行電漿蝕刻製程時，將蝕刻反應氣體輸入反應室主體200 之中，然後利用内侧功率源221與外側功率源220控制蝕 刻反應氣體所形成電漿的運動方式，在矽晶圓的表面上方 形成非等向性的運動方式，對矽晶圓上的薄膜進行電漿轟 擊。 依照上述的電漿蝕刻設備，形成於反應室之中的電 漿，是受控制於反應室主體上方的内側功率源與外側功率 源，利用這兩個電漿功率源來控制整個電漿的運動方式。 一般而言，電漿蝕刻設備是適用於大尺寸矽晶圓，必須注 n I. . I - _-1 «- fin II I II —:I -I I X. - U3. ,·515 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局舅工消費合作社印敦 Δ2.69 ^ ^ # at 〜 ------ - Η 7 五、發明説明（） * ~~一-- 思到電漿在矽晶圓表面的均勻性，以求得蝕刻速率的一致 性與蝕刻圖案之絕對尺寸的均勻度。 在前面的討論之中，是敘述有關渠溝在電漿蚀刻反應 室之中的蝕刻深度，會因為在渠溝在矽晶圓上的不同位 置，造成蝕刻深度的不一致，如第三圖所示的蝕刻深度ΑΙ 與A2’這將會使得製造出來的積體電路具有較差的可靠 度。這種因為位置的不同，造成钱刻速率與姓刻深度不同 的情况’可以藉由調整電漿钮刻反應室的電聚功率源，使 得在矽晶圓表面具有均勻的電漿密度，來解決上述的問 題。一般而言，在一般的實驗過程之中，將内側功率源與 外側功率源調整為某種比例’換言之，當内側功率源相較 於外側功率源約為某個比例時，會使得電漿密度趨於均 勻，使得矽晶圓表面具有均勻的蝕刻速率。 經濟部中央標準局貝x消费合作社印製 但是，利用上述的方法雖可以解決蝕刻速率不一致的 問題’而積體電路的蝕刻圖案會因為電漿在反應室之中的 運動方式’使得矽晶圓之中央區域與邊緣區域的蝕刻前後 絕對尺寸差異不一致，所形成的積體電路會具有較差的可 靠度。因此，需要一種在雙線圈感應耦合電漿蝕刻反應室 中改善積體電路之絕對尺寸均勻度的方法，並使得矽晶圓 表面具有均勻的蝕刻速率，以提高積體電路的可靠度與圖 案轉移的準確性。 5A: B * V. Description of the invention (Technical field · 'Employees of the Central Ladder Standard Bureau of the Ministry of Economic Affairs, Cooperative Cooperative Press' The present invention relates to a method for manufacturing integrated circuits using a dual coil inductively coupled plasma etching reaction chamber, in particular The invention relates to a method for adjusting the absolute size uniformity of an integrated circuit in a dual-coil inductively coupled plasma etching reaction chamber. BACKGROUND OF THE INVENTION: In the current integrated circuit manufacturing technology, the integrated circuit substrate is used. It is a six-inch or eight-inch silicon wafer, and the entire area is quite large. Therefore, in various process technologies, it is necessary to pay attention to the manufacturing of all semiconductor components on the entire silicon wafer. For example, plasma etching of the film layer The process, in the center and edge of the silicon wafer, will have different engraving rates due to the difference in plasma density. According to the structure design of the general semiconductor device, the plasma in the center of the "Xijing-circle, compared to the The plasma on the edge of the silicon wafer has a large density, so that the central region and the edge region of the silicon wafer have different etching rates. According to the above situation, In the etching process of circuit manufacturing, the uncertainty of semiconductor device manufacturing will be caused by the uneven etching rate. For example, in the etching process of forming a contact window with a silicon dioxide layer, the plasma etching of the silicon dioxide layer is performed. And due to the uneven plasma density, the trenches in the central area and the trenches in the edge area have different Etching depths. Read the note jk- affixed to the back 1¾ first. Paper size is applicable to China National Standard (CNS) A4 (210X297). Central Office of the Ministry of Economic Affairs, Labor and Consumer Affairs Cooperative Association ^ 269'2. A7______ B7 V. Description of the invention () The following will refer to the first figure to The third figure illustrates the process of etching the silicon dioxide layer to form a contact window, and explains the different etching depths caused by the uneven plasma density. Please refer to the first figure to provide a semiconductor substrate 100 as the substrate of the integrated circuit Then, a silicon dioxide layer 110 is formed on the semiconductor substrate 100 as an insulating material or a dielectric material of the integrated circuit, and then a bottom anti-reflection coating is formed. (Reflective coating, BARC) 120 covers the surface of the silicon dioxide layer 110. A photoresist pattern 130 is formed to cover the bottom anti-reflection coating 120 and expose the area of the bottom anti-reflection coating 120 to be etched. See also In the second figure, a plasma etching process is used to etch the bottom anti-reflection coating 120 'to expose the surface of the silicon dioxide layer 110. Please refer to the third figure, using a plasma etching process to etch the silicon dioxide layer 110, A contact hole is formed in the silicon layer 110 to form a contact hole of the semiconductor substrate 100. In the schematic cross-sectional view of the third figure, the central contact hole 140 and the edge contact hole 150 are formed in the silicon dioxide layer 110. According to the conventional As for the plasma etching technology, 'because the central region has a higher plasma density and a higher etch rate in the central region, the etching depth B1 of the central contact hole 140 will be greater than the etching depth B2 of the edge contact hole 150. . Therefore, using the conventional plasma etching technology to perform the etching process of the integrated circuit will cause the central region and the edge region of the silicon wafer to have different etching depths. According to the design of advanced semiconductor plasma etching equipment, three plasma power sources are used in the plasma etching equipment, and one bias plasma power source is installed —____ 3 This paper is applicable to the national standard (CNS> Λ4 gauge pile (210x297mm ~ (For the precautions for reading first, then fill in the "Η" page) Order A2B9 A 2 · AT H7 V. Description of the invention () At the bottom of the reaction chamber, the other two plasma power sources are The inner plasma power source and the outer plasma power source are installed above the reaction chamber to adjust the plasma density in the reaction chamber. Please refer to the fourth figure, which shows a schematic cross-sectional view of a semiconductor plasma etching equipment. The slurry etching equipment is a reaction chamber main body 200, and a heating device 205 is provided above the reaction chamber main body 200 to heat the reaction chamber main body 200. A cooling device 206 is provided above the heating device 205 to cool the entire reaction chamber. Main body 200. There is an electrostatic chuck 250 below the main body 200 of the reaction chamber, and is used to place silicon wafers in the plasma etching process. In this plasma etching equipment, a DC bias source 210 Connected to the electrostatic chuck 250, a ground wire 230 is connected to the reaction chamber main body 200, an inner power source 221 is connected to the central region of the reaction chamber main body 200, and an outer power source 220 is connected to an edge region of the reaction chamber main body 200. During the slurry etching process, the etching reaction gas is input into the reaction chamber body 200, and then the inner power source 221 and the outer power source 220 are used to control the movement of the plasma formed by the etching reaction gas to form a non-equivalence over the surface of the silicon wafer. Plasma bombardment of the thin film on the silicon wafer by directional motion. According to the above plasma etching equipment, the plasma formed in the reaction chamber is controlled by the inner power source and the outer side above the main body of the reaction chamber. The power source uses these two plasma power sources to control the movement of the entire plasma. Generally speaking, plasma etching equipment is suitable for large-size silicon wafers, which must be noted. I.. I-_-1 «- fin II I II —: I -II X.-U3., · 515 (Please read the precautions on the back before filling out this page) Central Standards Bureau, Ministry of Economic Affairs, Consumers Cooperative, India Δ2.69 ^ ^ # at ～- ------ Η 7 V. Description of the invention () * ~~ 1-Considering the uniformity of the plasma on the surface of the silicon wafer, in order to obtain the uniformity of the etching rate and the uniformity of the absolute size of the etching pattern. In the description of the etching depth of the trench in the plasma etching reaction chamber, the etching depth will be inconsistent due to the different positions of the trench on the silicon wafer, as shown in the third figure. A2 'This will make the fabricated integrated circuit have poor reliability. This situation caused by the difference in the position and the depth of the money engraving rate can be adjusted by the plasma button engraving reaction chamber The power source makes a uniform plasma density on the surface of the silicon wafer to solve the above problems. Generally speaking, in the general experiment process, the inner power source and the outer power source are adjusted to a certain ratio. In other words, when the inner power source is about a certain ratio compared to the outer power source, the plasma density will be increased. It tends to be uniform, so that the surface of the silicon wafer has a uniform etching rate. Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and the Consumer Cooperative, but using the above method can solve the problem of inconsistent etching rates. The absolute size difference between the central area and the edge area before and after the etching is not the same, and the formed integrated circuit will have poor reliability. Therefore, a method for improving the absolute size uniformity of integrated circuits in a dual-coil inductively coupled plasma etching reaction chamber is required, and the surface of the silicon wafer has a uniform etching rate to improve the reliability and pattern of the integrated circuits. Accuracy of transfer. 5
本紙張尺度適用中國國家榡準（CNS )厶4現格（2!Ox2V7^TT A7 η 7 Λ269、2 . 五、發明説明 發明簡要說明與目的： 改善籍揭露種在雙線圈感應_合電㈣刻反應室 ===尺寸均勻度的方法.至少包含· ®基材，料-«MS在半f縣材之上；定義 〜圖案至膜層之上；在雙線圈感應_合電隸刻反應 至之㈣光阻圖案’調整反應室的内側電漿功率源與外 側電装功率源，以使得光阻㈣在晶圓邊㈣域賴刻後 2對尺寸’大於在中央區域的絕對尺寸；在雙線圈感應麵 σ電漿触刻反應室之巾㈣膜層，並使用光關案作為敍 刻罩幕，調整反應室的内側電漿功率源與外側電漿功率 源’使得膜層的中央區域與邊緣區域具有相同的蝕刻前後 絕對尺寸差異與触刻速率。 圖式簡單說明： 第一圖係顯示半導體晶圓的剖面示意圖，在半導體晶圓 上覆蓋一二氧化矽層/底部抗反射塗覆，在表面利 用光阻定義兩個區域； 第二圖係顯示半導體晶圓的剖面示意圖，利用電漿蝕刻 技術，對以蝕刻露出的底部抗反射塗覆； 第三圖係顯示半導體晶圓的剖面示意圖’利用電衆钮刻 本紙張尺度適用中國國家標準（CNS) Α4岘格（2l〇_xM7'i># > (請先閱請背而之注念事項4填艿本頁 裝.This paper standard is applicable to China National Standards (CNS) 厶 4 (2! Ox2V7 ^ TT A7 η 7 Λ269, 2. V. Description of the invention Brief description and purpose of the invention: To improve the disclosure of double coil induction_ 合 电Engraving reaction chamber === method of dimensional uniformity. At least contains a ® substrate, material-«MS on top of semi-f county material; definition ~ pattern to the film layer; double coil induction _ helili The photoresist pattern of the photoresist is adjusted to adjust the inner plasma power source and the outer electrical power source of the reaction chamber, so that the photoresist will be 2 pairs of sizes larger than the absolute size in the central region after being etched in the wafer edge area; On the double-coil induction surface, the σ plasma touches the membrane layer of the reaction chamber, and uses the light-off case as a narrative mask to adjust the inner plasma power source and the outer plasma power source of the reaction chamber to make the film layer The central area and the edge area have the same absolute size difference and etching rate before and after etching. The diagram is briefly explained: The first diagram is a schematic cross-sectional view of a semiconductor wafer, which is covered with a silicon dioxide layer / bottom anti-reflection Coating, using photoresist to define two on the surface The second picture shows a cross-sectional schematic diagram of a semiconductor wafer using plasma etching technology to apply anti-reflection coating to the bottom exposed by etching; the third picture shows a cross-sectional schematic diagram of a semiconductor wafer 'engraving this paper with electric buttons Standards apply Chinese National Standard (CNS) Α4 Dange (2l0_xM7'i ># >
*1T 經濟部中央樣準局員工消費合作社印聚 Λ 7 Β7 4269 ^ 丨—. 五、發明説明（ 技術，蝕刻二氧化矽層’在其中形成兩個渠溝； 以及 第四圖係顯示本發明之雙線圈感應耦合電漿蝕刻反應室 的剖面示意圖。 發明詳細說明： 本發明係揭露一種在雙線圈感應耦合電漿触刻反應室 改善積體電路之絕對尺寸均勻度的方法，提供一半導艎基 材，·形成一膜層覆蓋在半導體基材之上；定義一光阻圖案 至膜層之上；在雙線圈感應耦合電漿蝕刻反應室之中蝕刻 光阻圖案’調整反應室的内側電漿功率源與外侧電漿功率 源，以使得光阻圖案的蝕刻後絕對尺寸，在中央區域與在 邊緣區域具有較小的差異；在雙線圈感應耦合電漿蝕刻反 應室之中蝕刻膜層，並使用光阻圖案作為蝕刻罩幕，調整 反應室的内側電漿功率源與外側電漿功率源，使得膜層的 中央區域與邊緣區域具有相同的絕對尺寸差異與蝕刻速 率〇 在本發明之中，蝕刻光阻圖案係利用氧氣、碳氩氣體 與氬氣作為反應氣體，在雙線圈感應耦合電漿蝕刻反應室 之中，產生均向性蝕刻電漿，以調整該光阻圖案的絕對尺 寸，並調整雙線圈感應耦合電漿蝕刻反應室的内側電漿功 本紙張尺度適用中囡國家標準（CNS ) Α4坭格（210X2^7公哲） (誚先閲讀背面之注念事項再填朽本頁) .裝 、1Τ 經濟部中夬標準局员工消費合作社印鉍 經濟部中央標準局貞工消費合作社印製 4269 1 2 · .匕 6 9'2 / a 7 B7 五'發明説明（） 率與外側電漿功率，使得光阻圖案的t央區域與邊緣區 域，具有相同的電漿密度。 請參閱第四圖，顯示半導體電漿蝕刻設備的剖面示意 圖，整個電漿蝕刻設備為一個反應室主體200，在反應室 主體200的上方具有一個加熱裝置205，對反應室主體200 進行加熱動作。在加熱裝置205的上方具有一個冷卻裝置 206，用來冷卻整個反應室主體200。在反應室主體200的 下方具有一個靜電吸盤250，在電漿蝕刻製程中，用來放 置矽晶圓。在此電漿蝕刻設備之中，一直流偏壓源210連 接於靜電吸盤250，而一地線230連接反應室主體200， 一内側電漿功率源221連接在反應室主體200的中央區 域，一外側電漿功率源220連接在反應室主體200的邊緣 區域。在進行電漿蝕刻製程時，將蝕刻反應氣體輸入反應 室主體200之中，然後利用内側電漿功率源221與外侧電 漿功率源220控制蝕刻反應氣體所形成電漿的運動方式， 在矽晶圓的表面上方形成非等向性的運動方式，對矽晶圓 上的薄膜進行電漿轟擊。 請參閱第一圖，提供一半導體基材100,作為積體電 路的基底，接著在半導體基材1〇〇上形成二氧化矽層110， 作為積體電路的絕緣材料或介電材料，然後形成一底部抗 反射塗覆(BARC)120覆蓋在二氧化矽層110的表面，以減 少在微影製程之中底層圖案的光線反射。形成一光阻圖案 8 本紙張尺度適州中國國家榡孪（CNS ) A4ML格（210X29D>^ ) ~ (誚先間讀背而之注意事項咚填艿本頁) 經濟部_央標丰局負工消斧合作社印製 4269 1 2 . A7 ___________»7 五、發明説明（） 13〇’覆蓋在底部抗反射塗覆120之上，並曝露出欲餘刻 的底部抗反射塗覆120區域。 請參閱第二圖’利用雙線圈感應耦合電漿蝕刻反應室 的電漿蝕刻方式’蝕刻底部抗反射塗覆丨2〇,曝露出二氧 化矽層110的表面，在此步驟之中，是利用雙線圏感應耦 合電漿蝕刻反應室的點燃電漿（Striking)製程，在開始電漿 餘刻製程時’利用氧氣與氬氣的混合氣體作為姓刻反應氣 體’形成混合氣體電漿以蝕刻底部抗反射塗覆12(^當辞 刻底部抗反射塗覆120時，調整雙線圈感應耦合電漿蝕刻 反應室的電漿功率源’使得矽晶圓表面上的電漿密度具有 均勻性。由於氧氣與氬氣所形成的蝕刻反應電漿，對光阻 圖案130的均向性蝕刻反應。位於矽晶圓之中央區域的中 央接觸孔140，所得到的絕對尺寸，小於在石夕晶圓之邊緣 區域的邊緣接觸孔150所得到的絕對尺寸。 在本發明之一具體實施例之中，調整雙線圈感應耦合 電漿姓刻反應至的電激功率源，使得内側電楽功率源與外 側電漿功率源能夠維持一個固定比例，來達到上述的效 果。 請參閱第三圖，使用主要電漿蝕刻製程，以光阻圖案 130作為蝕刻罩幕’蝕刻二氧化矽層11〇，在二氧化矽層n〇 之中形成接觸孔，形成半導趙基材100的接觸孔，並調整 9 (請先間讀背面之注意事項再填涔本芬)* 1T The Consumer Cooperative Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs, Yin Ju Λ 7 Β7 4269 ^ 丨. 5. Description of the Invention (Technology, etching the silicon dioxide layer 'to form two trenches therein; and the fourth figure shows the present invention Cross-section schematic diagram of a dual-coil inductively coupled plasma etching reaction chamber. Detailed description of the invention: The present invention discloses a method for improving the absolute size uniformity of integrated circuits in a dual-coil inductively coupled plasma etching reaction chamber. Guide the substrate to form a film covering the semiconductor substrate; define a photoresist pattern onto the film; etch the photoresist pattern in the dual-coil induction coupling plasma etching reaction chamber to adjust the reaction chamber Inside plasma power source and outside plasma power source, so that the absolute size of the photoresist pattern after etching has a small difference in the central area and in the edge area; in the dual-coil induction coupling plasma etching reaction chamber The film layer is etched, and a photoresist pattern is used as an etching mask. The inner plasma power source and the outer plasma power source of the reaction chamber are adjusted so that the central area and the edge area of the film layer have Have the same absolute size difference and etching rate. In the present invention, the etching photoresist pattern uses oxygen, carbon argon gas, and argon as the reaction gas in the double-coil inductively coupled plasma etching reaction chamber. Plasma etched plasma to adjust the absolute size of the photoresist pattern, and adjusted the inner plasma work of the dual-coil inductively coupled plasma etching reaction chamber. The paper size applies the Chinese National Standard (CNS) Α4 坭 Grid (210X2 ^ (7 Gongzhe) (read the notes on the back before filling out this page). Installed, printed by 1T China Consumer Standards Cooperative Bureau of the Ministry of Economic Affairs, printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by Zhengong Consumer Cooperative, 4269 1 2 ·. Dagger 6 9'2 / a 7 B7 Five 'invention description () rate and outer plasma power, so that the central area and edge area of the photoresist pattern have the same plasma density. Please refer to the fourth figure, which shows the semiconductor power A schematic cross-sectional view of a slurry etching device. The entire plasma etching device is a reaction chamber body 200, and a heating device 205 is provided above the reaction chamber body 200 to heat the reaction chamber body 200. During heating There is a cooling device 206 above the set 205 for cooling the entire reaction chamber body 200. Below the reaction chamber body 200 is an electrostatic chuck 250, which is used to place silicon wafers during the plasma etching process. Here the plasma In the etching equipment, a DC bias source 210 is connected to the electrostatic chuck 250, a ground wire 230 is connected to the reaction chamber body 200, an inner plasma power source 221 is connected to the central area of the reaction chamber body 200, and an outer plasma power The source 220 is connected to the edge region of the reaction chamber body 200. During the plasma etching process, an etching reaction gas is input into the reaction chamber body 200, and then the inside plasma power source 221 and the outside plasma power source 220 are used to control the etching reaction. The plasma movement mode of the gas forms an anisotropic movement mode above the surface of the silicon wafer, and plasma bombards the thin film on the silicon wafer. Referring to the first figure, a semiconductor substrate 100 is provided as a substrate of an integrated circuit, and then a silicon dioxide layer 110 is formed on the semiconductor substrate 100 as an insulating material or a dielectric material of the integrated circuit, and then formed. A bottom anti-reflection coating (BARC) 120 covers the surface of the silicon dioxide layer 110 to reduce light reflection of the underlying pattern during the lithography process. Forming a photoresist pattern 8 paper sizes China National Twin (CNS) A4ML grid (210X29D > ^) ~ (诮 Notes for reading before and after 咚 Fill in this page) Ministry of Economic Affairs_ 阳 标 丰 局Printed by Gongxiao Axe Cooperative 4269 1 2. A7 ___________ »7 V. Description of the invention () 13 'is covered on the bottom anti-reflection coating 120, and the bottom anti-reflection coating 120 area to be etched is exposed. Please refer to the second picture, "Plasma etching method using dual coil inductively coupled plasma etching reaction chamber" to etch the bottom anti-reflection coating 20, exposing the surface of the silicon dioxide layer 110. In this step, it is Using the two-line 圏 induction coupling plasma etching reaction chamber to ignite the plasma (Striking) process, when starting the plasma plasma etching process, 'using a mixed gas of oxygen and argon as the reaction gas to form a mixed gas plasma for etching Bottom anti-reflection coating 12 (When the bottom anti-reflection coating 120 is etched, the plasma power source of the dual-coil induction coupling plasma etching reaction chamber is adjusted to make the plasma density on the silicon wafer surface uniform. Due to the etching reaction plasma formed by oxygen and argon gas, the isotropic etching reaction on the photoresist pattern 130. The absolute size of the central contact hole 140 located in the central region of the silicon wafer is smaller than that on the Shixi wafer The absolute size obtained by the edge contact hole 150 in the edge area of the edge area. In a specific embodiment of the present invention, the electric power source to which the double-coil inductively coupled plasma reacts is adjusted so that the inner electrode The power source and the outer plasma power source can maintain a fixed ratio to achieve the above effect. Please refer to the third figure, using the main plasma etching process, using the photoresist pattern 130 as an etching mask to etch the silicon dioxide layer 11. , Forming a contact hole in the silicon dioxide layer n0, forming a contact hole of the semiconductor substrate 100, and adjusting 9 (please read the precautions on the back first and then fill in this fen)
A7 II7 4269 1 2 . 五、發明説明（ 反應的内側電漿功率源與外側電漿功率源，在矽晶圓表面 產生均勻的電漿密度。在第三圖的刮面示意圖之中，中央 接觸孔140與邊緣接觸孔150形成在二氧化矽層110之中。 利用電漿點燃步驟對光阻圖案130的均向性蝕刻製 程，使得渠溝150在触刻後的絕對尺寸（Critical dimension after etching inspection)大於渠溝140的在触刻後的絕對尺 寸。因此’會因為在渠溝150的蝕刻後絕對尺寸補償動作， 在進行二氧化矽層110的主要蝕刻製程之後，渠溝140與 渠溝150會具有相同的絕對尺寸差異（Criticai dimension bias) 〇 因此’在雙線圈感應耦合電漿蝕刻反應室，調整反應 室的内側電漿功率源與外側電漿功率源，以改善積體電路 之絕對尺寸均勻度，是在反應室的電漿點燃步驟中，利用 氧氣與氬氣對光阻圖案進行均向性蝕刻製程，使得矽晶圓 之邊緣區域的蝕刻圖案，比起中央區域的蝕刻圖案，具有 較大的絕對尺寸，並且在主要蝕刻製程中，利用光阻圖案 作為姓刻罩幕’使得在矽晶圓上的蝕刻圖案具有相同的絕 對尺寸與被蚀刻速率。 本發明以較佳實施例說明如上，而熟悉此領域技藝 者，在不脫離本發明之精神範圍内，當可作些許更動潤飾， 其專利保護範圍更當視後附之申請專利範圍及其等同領域 10 ---：--.---i------IT------ (¾先閱讀背曲之注意事項再填寫本頁) 經濟部中央標準局負Η消費合作社印装 4269 1 2 . 五、發明説明（） 而定。 (請先閱請背面之注意事項再填寫本頁) 裝_A7 II7 4269 1 2. V. Description of the invention (The inner plasma power source and outer plasma power source of the reaction produce a uniform plasma density on the surface of the silicon wafer. In the schematic diagram of the scraped surface in the third figure, the central contact The hole 140 and the edge contact hole 150 are formed in the silicon dioxide layer 110. The isotropic etching process of the photoresist pattern 130 is performed by using a plasma ignition step, so that the absolute dimension of the trench 150 after touching (Critical dimension after etching) inspection) is larger than the absolute size of the trench 140 after the etching. Therefore, because of the absolute size compensation action after the etching of the trench 150, after the main etching process of the silicon dioxide layer 110, the trench 140 and the trench 150 will have the same absolute dimension difference (Criticai dimension bias). Therefore, in the dual-coil induction coupling plasma etching reaction chamber, adjust the inner plasma power source and the outer plasma power source of the reaction chamber to improve the integrated circuit. The absolute size uniformity is the process of isotropically etching the photoresist pattern using oxygen and argon in the plasma ignition step of the reaction chamber, so that the edge area of the silicon wafer The etching pattern has a larger absolute size than the etching pattern in the central area, and in the main etching process, the photoresist pattern is used as the engraved mask to make the etching pattern on the silicon wafer have the same absolute size. And the etching rate. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some minor modifications without departing from the spirit of the present invention, and the scope of patent protection should be regarded as the attached application. Patent Scope and Equivalent Fields 10 ---: --.--- i ------ IT ------ (¾Please read the notes of the back song before filling this page) Central Bureau of Standards, Ministry of Economic Affairs Printed by negative consumer cooperatives 4269 1 2. V. Invention description () It depends. (Please read the notes on the back before filling this page)
-1T 經濟部中央標準扃員工消资合作社印裝-1T Central Standard of the Ministry of Economy
1A 1L 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2!0X297公筇）1A 1L The size of this paper is applicable to Chinese National Standard (CNS) Λ4 specification (2! 0X297mm)