趣濟部智慧財產局員工消費合作社印製 426882 五、發明説明（ 發明領域： 本發明係關於積體電路微影製程中疊對修正之方 法’更特别的是，一種系統化修正疊對誤差而使晶圓上 各層積體電路圖索精準確對準之方法。 發明背景： 積體電路製程係將多層次結構架構在一半導體基材 上’各層薄膜在沉積後需以微影配合蝕刻製程以形成各 電路圖案。不僅電路圖案之線寬必須符合規格，二層電 路圏案間疊對的準確度也非常重要。特别是在當下之製 程已近乎完全步入深次微米時代，當層（current layer) 與前層（previous layer)疊對的精確度相對提高，例如， 〇 2 5微米產品，可容忍的疊對誤差將縮減到〇.彳微米以 下’而對於0.1 8微米的產品，可容忍的疊對誤差將更縮 減爲G. 0 7微米以下。囡此，降低疊對誤差的技術將關係 產品良率的高低。 爲了解叠對誤差之大小以作爲修正之參考，習知技術 係在欲製造半導體元件的基材（例如矽晶圓）上形成供步 進機對準的圖形（稱此爲第零層）。此對準圖形通常爲具有 兩個方向以上之條紋所構成（請參考圖_)，並且對準圖形 同時也形成於光罩之上’用以在曝光之前，步進機先利 用光罩及晶圓上之對準圖形將二者對準。因在各薄膜層 上所形成的電路圖案均對準於第零層，所以各層電路圖 案亦能彼此互相對準。此外’在每一曝光機一次曝光 本紙張尺度適用尹國國家標準（CNS > A4規格（210X297厶釐） I ~| I I I 訂 ！ 線 · (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 42688 2 五、發明説明（） 圍（稱之爲像場（image fie丨d)8)之空曠處（如切割道）也同 時加曝大小框’以了解微影製程後之疊對狀泥。 仍請參考圖一，在每一層之每一像場8之電路圖案旁 邊空曠處皆加曝了大框1 0與小框2 0之圖形，其中在當 層（C)之小框c_20之中心被設計成與前層（p)之大框 P _ 1 0之中心重疊，而形成了一個内外框結構（f「a m e - i η -frame)。利用光學方法配合影像處理技巧量測小框中心 對大框中心之偏移即得到二層之間的疊對誤差。 在晶圓上某一點之疊對誤差爲一向量，許多點之疊紂 誤差的集合则形成一向量場。爲了降低叠對誤差，做疊 對修正前，必須先將該向量場分解，求出以下各分量的 大小：像場間之平移、旋轉、非正交、放大（interfield translation , rotation , non-orthogonality, expansion)以 及像場内之平移、旋轉、放大（丨ntrafield translation, rotation, magnification)。 圖二A至圖二C所示即爲傳統方法，在每一層修正 當層與前層之疊對誤差的情形。圖二A中批量（p)之各層 L1、L2、L3…分别有一疊對誤差。請注意，由於疊對誤 差爲當層小框中心點相對於前層大框t心點之位移，因 此係相對層之間的一向量（圖二僅顯示一 X方向分量）， 例如分量1 5係L2相對L1，基準點爲分量1 2之頂端。 圖二B顯示根據批量P在各層的疊對誤差修正下一批量 (P+1)各對應層的疊對的結果，亦即對下一批量（P + 1)， 在L1層修正向量12，在L2層修正向量15,依此類推， 其結果是在L1層已沒有疊對誤差了 ，然而L2層則多了 本紙悵尺度適用中國國家標準（CNS ) A4说格（210><297冬釐） -----„---^--—裝------訂------線 - - (請先閲讀背面之注^項再填寫本頁) Α7 Β7 42688 2 五、發明説明（） π ί 向量依此類椎。圖二c顯示根據批量Ρ + 1在各層的 疊對誤差修正再下一批量（P + 2)各對應層的疊對的結 果。由上圖可看出傳統方法修正效率很差。 對於半導體委託製造廠，在生產線上有許多不同產品 的製程同時在進行，爲防止產品處理的延誤，我們需要 個有效率的疊對誤差修正系統。儘管當前後批量所使 用的步進機、光罩和製程均相同，但由於無可避免的擾 動’使彳于則後批量稍有差異，因此根據前一批量之疊野 誤差所仔·^疊對修正，可能無法使後一批量之疊對誤差 元全爲零的情況時，上述傳統方法的修正效率將更低。 發明目的及概述： 本發明之目的在提升傳統方法對連績多個薄膜層上 之電路圖案的疊對誤差之修正效率。 本發明係一種對連續多個薄膜層上之電路圖案的要 對誤差之系统化修正方法’包含：首先計算—個（p _ 1 )(或 前幾個（P-1、P-2.·.)批量在當層⑴之絶對定位誤差（或其 平均値），做爲當批量（P)在當層⑴之負向回饋疊對修正 的依據’接著，計算當批量（P)在前層（ί_υ之殘餘絶對定 位誤差’做爲當批量（Ρ)在當層⑴之正向回饋叠對修正的 依據’依據上述負向回饋疊對修正與正向回饋昼對修正 乘以一收敛因子後之差値，可用以做爲當批量在當層所 需修正之疊對誤差。 此外每一批量之絶對定位誤差可用以做爲於視步進 本紙張Xj!適用令國國家標準（CNS > ( 21〇X297l着） ----Μ---一I 1¾衣------ΐτ------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4268 B ^ A7 B7五、發明説明（） 據 依 之 性 定 穩 程 製 和 罩 光 ' 機 明 説 單 簡 式 圖 4 下 以 輔 中 字 文 j 明 ί 説 和 之 場 後 像 往 ， 於 形 將 圖 例：準 施述對 實闡之 佳的圓 較細晶 的詳示 明更顯 發做一 本形圖 圖 rnj 歹 係 EBIJ- 之 框 經濟部智慧財產局員工消費合作社印製 圖二A顯示某一批量（P)在各層之疊對誤差（亦即，對 前一層之誤差）； 圖二B顯示利用前一批量（P)之疊對誤差對下一批量 (P+1 )做修正後的結果； 圖二C顯示利用其前一批量（P + 1)之疊對誤差對再 下一批量（P + 2)做修正後的結果； 第三A圖爲某一批量（批量P)做疊對修正前各層之疊 對誤差（對前層）或絶對定位誤差（對第零層）（僅畫出其中 一個分量，例如，像場間之X方向平移爲代表）；及 第三B圖爲下一批量（批量P + 1)依前一批量（批量P) 之絶對定位誤差做疊對修正後之殘餘疊對誤差（對前層） 或殘餘絶對定位誤差（對第零層）。 5-5發明詳細説明： 一如在發明背景所述，當今微影製程情準度的要求 愈來愈嚴格，然而在實際曝光之前，卻又很難預測所形 成的電路圖案相對於前層電路圖案的疊對誤差是多少。 可是一旦曝完光之後，若所量測到的疊對誤差太大，則 ----^---1---裝------訂------線 (請先閣讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家搮準（CNS ) A4说格（210X297么釐） 42688 2 at _______ B7五、發明説明（） 經濟部智慧財產局員工消费合作社印製 必須重做（亦即’將光阻去除後，重新進行微影製程）。因 此如何消除疊對誤差，以提高良率，是業界的一致目標， 更是所有微影製程工程師的職責β 欲消除疊對誤差就需對誤差來源徹底了解，以便提 出解決之方法，本發明將提供上述間題的解決辦法。 爲更容易了解本發明手段，以下之本發明所用相關 術語將先定義説明： 一個批量（lot):係指同一批或者同一個晶圓盒 (cassette)内之晶片進入製程室或者微影室中相等或接 近者均屬之。 第零房之對準圖形：已描述於發明背景’叫同時參考 圖一。 疊對誤差：在每一像場（jmage fie Id)曝光時，在切割 道處所加曝的大小box(盒狀圖案），（或frame(框狀圖 案）），用以監視當層相對於前層偏移的量。例如量度當層 之小box(或小frame)對前層之大box(成大f「ame)之中4 位置之偏移量即爲二屠之叠對誤差。 負向回饋（feedback)疊對修正：係指參考前一個批量 之疊對誤差，修正下一個批量之疊對。這是因爲對相同 的產品，若使用相同的光罩以及以相同的步進機曝光的 晶圓，其疊對誤差應是類似的，以—較#的實施例而言’ 本發明係以前數個（约1至3個）批量在當層之絶對定位 誤差的平均値做爲下—批量之登對修足。 殘餘疊對誤差：係指根據前一批量之要對誤差，修正 下一批量之疊對後，仍剩餘之疊對誤羞。殘餘疊對誤差 (請先閲讀背面之注意事項再填寫本頁) 丨裝. 訂 線· 本紙張尺度適用中國國家橾率（CNS ) A4現樁（210x297冬董） 42688 2 at ___ B7五、發明説明（） 經濟部智慧財產局員工消費合作社印製 的產生最可能的原囡係即使前後批量所使用的步進機、 光罩和製程均相同，但由於無可避免的擾動，使得前後 批量稍有差異，因此根據前一批量之疊對誤差所得之修 正，可能無法使後一批量之疊對誤差完全爲零。 正向回饋（feedforward)疊對修正：係指針對負向回 饋修正後仍有殘餘疊對誤差，而當層之殘餘疊對誤差將 影響與下一層之疊對，因此在該批量下一層之微影製程 時依據前層之殘餘絶對定位誤差以偏移相同之方向做修 正，藉以減少疊對誤差量稱之。 絶對定位誤差（absolute misregistration):係指當層 (current fayer)相對於第零層對準圖形之疊對誤差。因此 絶對定位誤差係以第零層爲基準線。 CV_i[P-1 I:爲批量P-1在第i層圖案曝光時所加入之 疊對修正。 爲批量P-1之第i層圖案相對第丨_1層 圖案之殘餘疊對誤差。依據向量加法的性質， 可以第i層相對於第零層與第i-1層相對於第零層之殘餘 絶對定位誤差之差來表示：即 或0"」，0[卩-1】=〇乂_丨，丨-1[卩-1] + 0乂一丨-1,〇[^13; 依此類推： DV_j,0[P-1 卜DV_j.k[P-1 卜DV_k,0[P-1J ’ DV_i.1,〇[P-1] = DV_i.1J.2[P-1J + DV^i-2.〇[P-1]' DV_2,〇[P-1] = DV_2i1[P-1] + DV_i,〇[P：13 ° 本紙張尺度適用中國國家標準（CNS > A4規格（2丨0Χ297^釐） (請先閱讀背面之注意事項再填寫本頁) i |裝· -訂· 經濟部智慧財產局員工消費合作社印製 42668 2 Α7 _ Β7 五、發明説明（） V一i.o[P-1]:爲批量PM第丨層電路圖案相對於第零層 之要對誤差’即批量p_彳在第i層之絶對定位誤差。 因此根據上述定義，可獲得方程式：Printed by the Intellectual Property Bureau, Consumer Property Cooperative of the Ministry of Interest, 426882 V. Description of the invention (Field of the invention: The present invention relates to a method for correcting overlapping errors in the integrated circuit lithography process. More specifically, a systematic correction of overlapping errors Method for accurately aligning the circuit diagrams of various layers on a wafer. Background of the Invention: The integrated circuit process is to construct a multi-level structure on a semiconductor substrate. After the deposition of each layer of film, a lithography and etching process are required to form it. Each circuit pattern. Not only the line width of the circuit pattern must meet the specifications, but also the accuracy of the overlap between the two layers of circuit files is very important. Especially in the current process, which has almost completely entered the era of deep sub-microns, the current layer ) The accuracy of stacking with the previous layer is relatively improved. For example, tolerable stacking errors will be reduced to less than 0.1 micron for products of 0.25 micron, and for products of 0.1 8 micron, tolerable The overlap error will be reduced to less than G. 0 7 microns. Therefore, the technology of reducing the overlap error will affect the yield of the product. In order to understand the magnitude of the overlap error As a reference for correction, the conventional technology is to form a pattern (called the zeroth layer) for stepper alignment on a substrate (such as a silicon wafer) for which a semiconductor element is to be manufactured. This alignment pattern is usually It is composed of stripes in more than two directions (please refer to Figure _), and the alignment pattern is also formed on the mask. 'Before the exposure, the stepper uses the alignment pattern on the mask and the wafer. Align the two. Because the circuit patterns formed on each thin film layer are aligned with the zeroth layer, the circuit patterns of each layer can also be aligned with each other. In addition, 'once every exposure machine is exposed, the paper size is suitable for Yin National Standards (CNS > A4 Specifications (210X297%) I ~ | III Order! Line · (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 42688 2 V. Invention Note: The open space (called the image fie 丨 d) 8) (such as the cutting road) is also exposed with a size box at the same time to understand the stacked mud after the lithography process. Please also refer to Figure 1 8 electricity per image field in each layer In the open space next to the pattern, the figures of large frame 10 and small frame 20 are exposed, in which the center of the small frame c_20 of the current layer (C) is designed to be the same as the large frame P_1 0 of the previous layer (p). The centers overlap to form an inner and outer frame structure (f "ame-i η -frame). Using optical methods and image processing techniques to measure the offset of the center of the small frame to the center of the large frame, the overlap error between the two layers is obtained. The stacking error at a point on the wafer is a vector, and the set of stacking errors at many points forms a vector field. In order to reduce the stacking error, the vector field must be decomposed before the stacking correction is performed. The size of the following components: interfield translation, rotation, non-orthogonality, expansion, and intrafield translation, rotation, magnification . Figures 2A to 2C show the traditional method. At each layer, the overlap error between the current layer and the previous layer is corrected. Each layer L1, L2, L3 ... in the batch (p) in Fig. 2A has a stack of errors. Please note that because the overlap error is the displacement of the center point of the small frame of the layer relative to the center point of the large frame of the previous layer, it is a vector between the relative layers (Figure 2 only shows an X-direction component), such as component 1 5 System L2 is relative to L1, and the reference point is the top of component 12. Figure 2B shows the result of correcting the overlap of the corresponding layers in the next batch (P + 1) according to the overlap error of each layer in the batch P, that is, for the next batch (P + 1), the vector 12 is corrected at the L1 layer. Correct the vector 15 at the L2 layer, and so on. The result is that there is no overlap error at the L1 layer, but the L2 layer has more paper scales. The Chinese National Standard (CNS) A4 grid (210 > < 297 winter) (Li) ----- „--- ^ --------------------- order ---- (Please read the note ^ on the back before filling in this page) Α7 Β7 42688 2 V. Description of the invention () π ί The vector follows this kind of vertebra. Figure 2c shows the result of correcting the stacking error of each layer according to the batch P + 1 and then the stacking result of the corresponding layer in the next batch (P + 2). From above It can be seen from the figure that the traditional method has a very poor correction efficiency. For a semiconductor commissioned manufacturing factory, there are many different products in the production line at the same time. To prevent product processing delays, we need an efficient overlapping error correction system. Although The stepper, mask and process used in the current batch are all the same, but due to the unavoidable disturbance, it makes the later batch There are differences, so according to the overlap error correction of the previous batch, it may not be possible to make the correction error of the traditional method lower when the overlap error of the next batch is all zero. And summary: The purpose of the present invention is to improve the efficiency of correcting the overlap error of the circuit pattern on multiple thin film layers by the traditional method. The present invention is a system for correcting the error of the circuit pattern on multiple continuous thin film layers. The correction method includes: firstly calculate the absolute positioning error (or average 値) of one (p _ 1) (or the first few (P-1, P-2 ...)) in the current layer, as When the batch (P) is in the negative layer of the current layer, the basis for the correction is corrected. 'Next, calculate the residual absolute positioning error when the batch (P) is in the previous layer (ί_υ) as the batch (P) in the current layer. The basis of the positive feedback stack correction is based on the difference between the negative feedback stack correction and the positive feedback day-pair correction multiplied by a convergence factor, which can be used as the stack error when the batch needs to be corrected at the current level. In addition, the absolute positioning error of each batch can be As a step-by-step paper Xj! Applies to national standards (CNS > (21〇X297l)) ---- M --- I I 1¾ clothing ------ ΐτ ----- -Line (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4268 B ^ A7 B7 V. Description of the invention () According to the stability of the system and cover light The simple form of figure 4 is supplemented by the Chinese character j Ming ί The image of the field of harmony goes to the bottom, and the figure shows the legend: the quasi-description of the circle that is better explained is more detailed than the fine-grained display. Pictogram rnj is the frame of EBIJ- printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 2A shows the overlap error of a batch (P) in each layer (that is, the error to the previous layer); Figure 2B Shows the result of correcting the next batch (P + 1) using the stack error of the previous batch (P); Figure 2C shows the use of the stack error of the previous batch (P + 1) to correct the next batch. (P + 2) The result after making corrections; the third graph A is the overlap error (for the previous layer) of each layer before correction for a batch (batch P) or Absolute positioning error (for the zeroth layer) (only one component is drawn, for example, the X-direction translation between image fields is representative); and the third batch is the next batch (batch P + 1) according to the previous batch ( The absolute positioning error of batch P) is the residual overlapping error (for the previous layer) or the residual absolute positioning error (for the zeroth layer) after being corrected for the overlapping. 5-5 Detailed description of the invention: As stated in the background of the invention, the requirements for the accuracy of today's lithography process are becoming more and more stringent, but it is difficult to predict the formed circuit pattern relative to the previous circuit before the actual exposure. What is the overlap error of the pattern. However, once the exposure is over, if the measured overlap error is too large, then ---- ^ --- 1 --- installation ------ order ------ line (please first Note on the back of the Ge reading, please fill out this page again) This paper size is applicable to China National Standards (CNS) A4 format (210X297 Modi) 42688 2 at _______ B7 V. Description of Invention () Printed by the Intellectual Property Bureau Employee Consumer Cooperatives The system must be redone (that is, 'remove the lithography process after removing the photoresist). Therefore, how to eliminate the overlap error to improve the yield is a consistent goal in the industry, and it is the responsibility of all lithographic process engineers. To eliminate the overlap error, it is necessary to thoroughly understand the source of the error in order to propose a solution. The present invention will Provide solutions to the above problems. To make it easier to understand the means of the present invention, the following terms used in the present invention will be defined and explained first: A lot: means that the wafers in the same batch or in the same cassette enter the process room or lithography room They are equal or close. The alignment pattern of the zeroth room: has been described in the background of the invention 'is also referred to Figure 1. Overlap error: the size of the box (box-like pattern) (or frame (frame-like pattern)) exposed at the cutting track when each image field (jmage fie Id) is exposed, to monitor the current layer relative to the front The amount of layer offset. For example, measuring the offset of the small box (or small frame) in the current layer from the 4 position in the large box (into a large f "ame) of the previous layer is the stacking error of the second slaughter. Negative feedback stacking Correction: Refers to the stacking error of the previous batch, and corrects the stacking of the next batch. This is because for the same product, if the same photomask and the wafer exposed by the same stepper are used, the stacking The error should be similar, in terms of-compared to the # embodiment, the present invention is the average of the absolute positioning errors of the previous several (about 1 to 3) batches at the current level as the next-batches of the pair to repair . Residual stacking error: refers to the error of the previous batch, after correcting the stacking of the next batch, the remaining stacking is still wrong. Residual stacking error (please read the precautions on the back before filling this page) ) Assembling. Threading · This paper size is applicable to China National Standard (CNS) A4 stub (210x297 Dong Dong) 42688 2 at ___ B7 V. Description of invention () The production of printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Possible original systems are steppers used in batches, The photomask and the manufacturing process are the same, but due to the unavoidable disturbance, the front and back batches are slightly different, so the correction based on the stacking error of the previous batch may not make the stacking error of the next batch completely zero. Feedforward overlap correction: After the correction of negative feedback, there is still residual overlap error, and the residual overlap error of the current layer will affect the overlap with the next layer, so the lithography of the next layer in the batch During the manufacturing process, the residual absolute positioning error of the previous layer is used to correct the offset in the same direction, so as to reduce the amount of overlap error. Absolute misregistration: refers to the current layer relative to the zero layer pair. The overlay error of the quasi-graphics. Therefore, the absolute positioning error is based on the zeroth layer. CV_i [P-1 I: is the overlay correction added by the batch P-1 when the i-th layer pattern is exposed. It is the batch P- Residual overlap error of the i-th layer pattern of 1 relative to the 丨 _1 layer pattern. According to the nature of vector addition, the residual absolute positioning error of the i-th layer with respect to the zeroth layer and the i-1th layer with respect to the zeroth layer can be Difference Indication: that is, or 0 " ", 0 [卩 -1] = 〇 乂 _ 丨, 丨 -1 [卩 -1] + 0 乂 一 丨 -1, 〇 [^ 13; and so on: DV_j, 0 [P -1 DV_j.k [P-1 DV_k, 0 [P-1J 'DV_i.1, 〇 [P-1] = DV_i.1J.2 [P-1J + DV ^ i-2.〇 [P- 1] 'DV_2, 〇 [P-1] = DV_2i1 [P-1] + DV_i, 〇 [P: 13 ° This paper size applies to Chinese national standards (CNS > A4 specifications (2 丨 0 × 297 ^ cent) (please first Read the notes on the back and fill in this page) i | Install · -Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 42668 2 Α7 _ Β7 V. Description of the invention () V 一 io [P-1]: It is a batch PM The pairing error of the circuit pattern of the first layer relative to the zero layer is the absolute positioning error of the batch p_ 彳 at the i layer. Therefore, according to the above definition, the equation can be obtained:
Vj.otP-lh-CV—JP-IJ + DVj oP-I]。 發明人發現’大致而言，疊對誤差的來源有三：步 進機（例如，步進機成像透鏡之像差），光罩（例如，光罩 上圖案之定位不準），製程（例如，某些金屬濺鍍會造成晶 圓上對準圖形之偏移）。因此，相同的產品，使用相同的 光罩在栢同的步進機曝光的晶圓，其疊對誤差應是類似 的。所以，爲降低重做率，我們可以根據前—個批量之 誤差，來修正下—個批量之疊對。此即負向回饋 (feedback)疊對修正。於負向回饋疊對修正之後若仍有 殘餘疊對誤差，則若此殘餘疊對誤差仍符合產品規格， 則可不必重做。但因其會影響下一層電路圖案之疊對， 所以在下一層微影製程時，施以正向回鎖疊對修正，亦 即使下一層之絶對定位誤差在某種程度上與當層之殘餘 絶對定位誤差（相對於第零層之殘餘疊對誤差）相同，因而 與下一層之疊對誤差得以減少。 總之，對第P批量，加之於第丨層之疊對修正（含正 向以及負向回饋）爲 Ον — αΡΡ-νΌίΡ-ΙΙ + Ρ^Ον — Μ.οΙΡ-ΐ】， 此處 R 爲介於 0 和 1 之間 的常數 。通常 R 取 0.5 可 以得到最快的收歛。注意在上述公式中，正向回饋疊對 修正項恰與負向回饋疊對修正項差一個負號，表示正向 回饋疊對修正之方向與負向回饋疊對修正之方向相反。 由於像場間之平移（對晶圓中心之平移）、旋轉（對晶 本纸張尺度通用中國國家標率（CNS ) Α4規格（210Χ297么釐） ----’-----—装------訂------線 (請先閣讀背面之注意事項再填寫本頁) 426882 A7 B7 五、發明說明（） 圓中心（旋轉）、非正交（對晶圓中心之非正交）' 擴大（對 晶圓中心4擴大）以及像場内之平移（對像場中心之平 移）、旋轉（對像場中心之旋轉）、擴大（對像場中心之擴 大)各個分量是各自獨立的。因此’各個分量都可以應用 以上關係式做叠對修。 此外纟取前3〜5個批量絶對定位誤差的平均做爲 負向回饋疊對修正項可使正負向回饋疊對修正系統更爲 穩定。即以 (V_i.0[P-1] +VJ 〇[P_2H v—i 〇[ρ·3])/3 或…」〇[p1] + ν」.0[Ρ-2] + ··.+ ν」〇[ρ·5])/5 替代 v—i 〇[ρ ι】。 圖三A至B示以本發明提出之絶對定位誤差的觀念 取代相對層之間的疊對誤差觀念，並同時應用負向回饋 疊對修正與正向回饋疊對修正所得到之連續批量修正的 示意圖，圖三A係批量p做疊對修正前各層之疊對誤差 (對前層）或絶對定位誤差（對第零層）（僅畫出其中一個分 量爲代表，例如，像場間之x方向平移），其基準線爲第 零層之位置。而圖三B係下一批量p + 1依前一批量（批量 P)之絶對·疋位誤差做疊對修正後之殘餘疊對誤差（對前 層）或殘餘絶對定位誤差（對第零層由圖顯示本發明可 以成功地解決了發明背景所述之使用前—批量之當層對 前層之疊對誤差做修正所遭遇收斂效率差的問題。 *由於本發明只須修正當層之絶對定位誤差，因此只 須根據當層之步進機與光罩建立絶對定位誤差的資料庫 (而不須根據當層以及前層之步進機及光罩建立資料 庫），這對資料量的縮減及系統效率的提昇有非常大的幫 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公爱） > I i I— n »^i 1· I t . I I (請先閲讀背面之·注意事承再填寫本頁) 訂： 經濟部智慧財產局員工消費合作社印製 42688 2 A7 -------- B7 -一 五、發明說明（） 助。 進一步而言，每一批量之絶對定位誤差可用以監視 步進機、光罩和製程上之穩定性做爲是否開啓正負向回 镇疊對修正系統之參考。當疊對誤差超出規格以外時， 微影技術工程師首先必須關閉正負向回饋疊對修正系统 並對步進機、光罩和製程做檢查，待疊對誤差過大之問 題（即正負向回馈疊對修正系統失敗）澄清後’才可再開啓 正負向回饋修正系統。 如熟悉此技術之人員所瞭解的’以上所迷爲本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脱離本發明所揭承之精神下所完成之等效 故變或修飾，均應包含在下述之_請專利範固内。 --------- ----------—訂·------- 線 (請先閲讀背面之注意事货再填寫本頁) 經濟部智慧財產肩員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱〉Vj.otP-lh-CV—JP-IJ + DVj oP-I]. The inventors found that, in general, there are three sources of stacking errors: stepper (for example, the aberration of the stepper's imaging lens), reticle (for example, the positioning of the pattern on the reticle is inaccurate), and manufacturing processes (for example, (Some metal sputters can cause alignment patterns to shift on the wafer). Therefore, for the same product, the stacking error of wafers exposed on the same stepper by the same mask should be similar. Therefore, in order to reduce the redo rate, we can correct the overlap of the next batch according to the error of the previous batch. This is the negative feedback overlap correction. If there is still a residual overlap error after the correction of the negative feedback overlap, if the residual overlap error still meets the product specifications, it is not necessary to redo. However, because it will affect the overlay of the circuit pattern of the next layer, a positive back-lock overlay correction will be applied during the next lithography process, even if the absolute positioning error of the next layer is to some extent the same as the residual of the current layer. The positioning error (relative to the residual overlap error of the zeroth layer) is the same, so the overlap error with the next layer is reduced. In short, for the P-th batch, plus the pairwise correction (including positive and negative feedback) for the first layer, it is Ον — αΡΡ-νΌίΡ-ΙΙ + Ρ ^ Ον — Μ.οΙΡ-ΐ], where R is the medium Constant between 0 and 1. Usually R is 0.5 for the fastest convergence. Note that in the above formula, the correction term of the positive feedback stack pair is just a negative sign from the correction term of the negative feedback stack pair, which indicates that the direction of the positive feedback stack pair correction is opposite to the direction of the negative feedback stack pair correction. Due to the translation between the image fields (translation to the center of the wafer), rotation (common to the Chinese paper standard (CNS) A4 specification (210 × 297 mol%) for crystal paper sizes) ----'------- installation ------ Order ------ line (please read the notes on the back before filling this page) 426882 A7 B7 V. Description of the invention () Circle center (rotation), non-orthogonal (for wafer Non-orthogonal of the center) 'Enlargement (enlargement of wafer center 4) and translation within the image field (translation of center of image field), rotation (rotation of center of image field), enlargement (expansion of center of image field) The components are independent of each other. Therefore, the above relations can be used for each component to perform the stacking repair. In addition, the average of the first 3 to 5 batches of absolute positioning errors is used as the negative feedback stack. The correction term can make the positive and negative feedback stacks. It is more stable to the correction system. That is, (V_i.0 [P-1] + VJ 〇 [P_2H v—i 〇 [ρ · 3]) / 3 or ... ”〇 [p1] + ν” .0 [P- 2] + ··. + Ν ″ 〇 [ρ · 5]) / 5 instead of v—i 〇 [ρ ι]. Figures 3A to B show the continuous batch correction obtained by replacing the concept of overlap error between opposite layers with the concept of absolute positioning error proposed by the present invention, and applying negative feedback stack correction and positive feedback stack correction simultaneously. Schematic diagram, Figure 3 A series of batches of p before the correction of the stacking error (for the previous layer) or absolute positioning error (for the zeroth layer) of each layer (only one component is represented, for example, x between image fields) Direction translation), with its baseline at the zeroth level. And Figure 3B is the next batch p + 1 based on the residual batch error (for the previous layer) or residual absolute positioning error (for the zeroth layer) of the previous batch (batch P). The figure shows that the present invention can successfully solve the problem of poor convergence efficiency encountered in the correction of the stack-to-layer error of the current layer before the batch described in the background of the invention. * Since the present invention only needs to modify the absolute of the current layer Positioning error, so you only need to build a database of absolute positioning errors based on the stepper and photomask on the current floor (not on the basis of steppers and photomasks on the current floor and the front layer). The reduction and the improvement of system efficiency can greatly help the paper size to comply with China National Standard (CNS) A4 specification (21〇X 297 public love) > I i I— n »^ i 1 · I t. II (Please (Read the notice on the back, and then fill out this page first.) Order: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, 42688 2 A7 -------- B7-15. Description of Invention (). , Absolute positioning error of each batch can be used to monitor stepper, photomask The stability in the process is used as a reference to determine whether the positive-negative back-to-back stacking correction system is turned on. When the stacking error is outside the specification, the lithography technical engineer must first turn off the positive-negative feedback stacking correction system and stepper, light Check the hood and process, and wait until the problem of too large stack error (that is, the positive and negative feedback stack fails to correct the system) is cleared before you can turn on the positive and negative feedback correction system. As the person familiar with this technology understands, This is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other equivalent alterations or modifications made without departing from the spirit disclosed by the present invention shall be included in the following _Please patent Fan Gone. --------- ------------ Order · ------- Line (Please read the notice on the back before filling in this page ) Printed by the Ministry of Economic Affairs, Intellectual Property, Consumer Cooperatives, Paper Size Applicable to Chinese National Standard (CNS) A4 (210 X 297 Public Love)