TW426858B - Sense amplifier circuit of semiconductor memory device - Google Patents

Abstract

This invention is about the sense amplifier circuit of semiconductor memory device, in which four NMOS transistors are added to the conventional sense amplifier circuit. The gates of two NMOS transistors are connected with the write-in enable signal and the gates of the other two NMOS transistors are connected with the first node, which is connected with the bit line, and the second node, which is connected with the complementary bit line, respectively. Through the feedback formed by these four newly added NMOS transistors, two NMOS transistors are conductive and are grounded during the write-in cycle such that the voltage level of sense amplifier is promptly pulled down to low level for the purpose of increasing the latch speed of sense amplifier. Therefore, the executing efficiency of memory can be increased and, at the same time, the occurred problem of incomplete data write-in can be avoided.

Description

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The invention is printed by the Consumer Cooperative of the Zou Intellectual Property Bureau. The present invention relates to a sense amplifier (amplifier), and more particularly to a method for accelerating the speed of the latch of the sense amplifier and increasing the execution efficiency of the memory. Sense amplifier circuit of semiconductor memory element = It is well-known that a sense amplifier is constructed in a semiconductor memory element such as a dynamic random access memory (DRAM), which is connected to a bit line of a memory cell array, and can be Read the data from the selected memory cell and enlarge the data. Please refer to Figure}, which shows a circuit diagram of a conventional sense amplifier = The sense amplifier 10 is composed of two NMOS transistors 12, 1.4 and two PMOS transistors 1.6, 18. The connection relationship is as follows: Figure 丨. The sense amplifier 10 is connected to bit line pairs BL and BLB of a memory cell array (not shown), and is used to read and amplify the stored data in the selected memory cell. The following bit lines are called Complementary bit line BLB. In addition, the sense amplifier 10 is connected to the data line pair DL and DLB through NMOS transistors 20 and 22, respectively. The following data line DLB is referred to as a complementary data line DLB. The switching state of the above NMOS transistors 20 and 22 is determined by the voltage level provided by the row address signal COL. In addition, the symbols NSA and PSA in the figure represent relative sensing amplification enable signals. Conventionally, during the write operation of the sense amplifier 10, the complementary data line DLB needs to reach a low level to enable the sense amplifier 10 to latch. When the operating voltage decreases, during the write cycle, the complementary data line DLB is difficult to reach the low level defined by the sense amplifier 10 quickly due to the influence of the pass gate, as described in (Please read the precautions on the back before (Fill in this page)

* ---- II Ί Order --- I--II This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4 S 6 2 I \\ Γ. Dc / 1) (J A7 4 S 6 2 I \\ Γ. Dc / 1) (J A7 Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. # (2) 1 As shown in the figure, it will cause incomplete data writing. 3 Yes In view of this, the present invention proposes a sense amplifier circuit of a semiconductor memory element. Four NMOS transistors are added to the traditional sense amplifier circuit, of which two NMOS transistors have gates connected to write enable signals, and the other two The gates of the NMOS transistors are respectively connected to the first node and the second node connected to the bit line and the complementary bit line, and the feedback formed by the four newly added NMOS transistors is used to make the During a write cycle, the two NMOS transistors are turned on and connected to ground in order to quickly pull down the voltage level of the sense amplifier to a low level to achieve the purpose of increasing the latching speed of the sense amplifier. The proposed sense amplifier circuit of a semiconductor memory element, during a write cycle, The voltage level of the sense amplifier is quickly pulled down to a low level quickly, so that the latching speed of the sense amplifier is increased, which not only increases the memory execution efficiency, but also avoids the problem of incomplete data writing. To make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 shows FIG. 2 is a circuit diagram of a conventional sense amplifier; FIG. 2 is a circuit diagram of a sense amplifier according to a preferred embodiment of the present invention; and FIG. 3 is a diagram showing a sense amplifier of the present invention during a write cycle The waveforms of the relevant signals at this time. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling out this page) --- I 11 1.1 Order ·· -------- ^ 1 'Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 ^ 621 ^ t'. Doc / 1) 0 6 ^ ^ 26¾ ^-V. Description of the invention (3) Numbering of drawings Explanation: 丨 0, 3 0: Sense Amplifier 12, 14 20, 22, 32, 34, 36, 38, 40, 42, 48, 50: NM0S transistor 16 '18, 44, 46: PM0S transistor embodiment Please refer to FIG. 2 for an example according to the present invention A circuit diagram of a sense amplifier according to a preferred embodiment. The sense amplifier 30 proposed by the present invention is composed of six NMOS transistors 32, 34, 36, 38, 40, and 42 and two PMOS transistors 44, 46. The connection relationship is shown in FIG. 2. The sense amplifier 30 is connected to bit line pairs BL and BLB of a memory cell array (not shown) to read data stored in the selected memory cell and amplify the data. In addition, the sense amplifier 30 is connected to the data line DL and the complementary data line DLB through NMOS transistors 48 and 50, respectively. The switching states of the NMOS transistors 48 and 50 are determined by the voltage level provided by the row address signal C0L. In addition, the symbols NSA and PSA in the figure represent relative sensing amplification enable signals, for example: NSA is a low-level ground signal, PSA is a high-level voltage signal, GND represents ground, and WE represents writing An enable signal is used to determine the switching states of the NMOS transistors 38 and 40. Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a waveform diagram showing related signals of the sense amplifier of the present invention during a write cycle. According to the design architecture of the present invention, during the write cycle, the write enable signal WE is at a high level (hlgh). At this time, the NMOS transistor 38 and 40 will be formatted. (210 X 297 mm) (Please read the notes on the back before filling this page) ---- I --- I ^ ------- II 1 _ 4Μίι2ΐ \\ ί 'doc / 006 Α7 5 Explanation (β) is turned on, and the row address signal COL rises to a high level, so that the data DATA is written into the sense amplifier 30 via the data line DL and the complementary data line DLB. For example, when the data line DL and the complementary data line DLB are written to the nodes N1 and N2 in the sense amplifier 30 with the level "1" and the level "0", respectively, the node N2 will be In addition to the discharge at the level "0", the voltage level of the node N1 is also turned on by the data line DL because the data line DL is at the level "Γ, so that the NMOS transistor 36 is turned on, thereby accelerating the node N2 to a low level. Low level, so the NMOS transistor 42 is off, so the voltage level of node N1 is "1". Among them, the voltage level of node N1 is equivalent to the voltage level of bit line BL, and the voltage level of node N2 Equivalent to the voltage level of the complementary bit line BLB, as shown in Figure 2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). In other words, the present invention is a traditional sense The test amplifier 10 (as shown in FIG. 1) is added with four NMOS transistors 36, 38, 40, and 42. The gates of the NMOS transistors 38 and 40 are connected to write the enable signal WE, so that during the write cycle, NM0S transistors 38 and 40 are turned on and connected to ground GND to amplify the sense The voltage level of the device 30 is quickly pulled down to a low level, so that the latching speed of the sense amplifier 30 is increased, which will increase the execution efficiency of the memory. Therefore, since the present invention has NMOS transistors 36, 38, 40, and 42 The formed feedback, so during the writing cycle, the voltage level of the sense amplifier 30 can be connected to the grounded NM0S transistors 38 and 40 by being turned on, and quickly pulled to a low level, so that the sense amplifier 30 The latching speed is relatively fast. In summary, the advantages of the present invention are that the paper size can be quickly applied during the writing cycle. The Chinese paper standard (CNS) A4 (210 X 297 mm) A7 4 862i \ s r.doc / 0i) (> 6 G ^ ^ V. Description of the invention (f) Quickly pull down the voltage level of the sense amplifier to a low level, which increases the latching speed of the sense amplifier, which not only increases memory The implementation efficiency of the system can also avoid the problem of incomplete data writing. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art will not depart from the present invention. Within the spirit and scope of Various changes and modifications, so the protection scope of the present invention shall be determined by the scope of the attached patent application. --------- I-JI ·---n ^ 1-1-*- rDJ_ n If--IIII (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 This paper size applies to China National Standard (CNS) A4 (210 X 297)

Claims (1)

η ft ac A ABCD Printed by the Consumers ’Cooperative of the Ministry of Economic Affairs and Smart Production Bureau VI. Patent application scope 1.-A sense amplifier circuit for semiconductor memory elements, including: a first NMOS transistor whose source is connected to a A complementary data line whose gate is coupled to a first node;-a second NMOS transistor whose drain is coupled to the drain of the first NMOS transistor, whose gate receives a write enable signal and whose source Grounded; a third NMOS transistor whose source is grounded and whose gate receives the write enable signal; a fourth NMOS transistor whose drain is coupled to the drain of the third NMOS transistor, which The gate is coupled to a second node, the source of which is connected to a data line;-the fifth NMOS transistor, the drain of which receives a first sensing amplification enable signal, and the gate is coupled to the second node, Its source is connected to the data line and the first node; a sixth NMOS transistor, its drain receives the first sensing amplification enable signal, its gate is coupled to the first node, and its source is connected to The complementary data line and the second node; a first PMOS transistor, whose drain receives A second sense amplification enable signal, a gate of which is coupled to the second node, a source of which is connected to the data line and the first node; and a second PMOS transistor, the drain of which receives the second sense The signal is substantially energy-efficient, its gate is coupled to the first node, and its source is connected to the complementary data line and the second node. 2. The sense amplifier circuit of the semiconductor memory element described in item 1 of the scope of the patent application, further comprising a seventh NMOS transistor, configured in the sense -t -----. IIT ----- -Print · (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) ¾ Id JII8 \\ | 6 ^ 2 4SA ABICD Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative, the patent application range amplifier circuit and the data line, the drain of the seventh NM 0 S transistor is coupled to the first node, and its gate receives a row of address signals and its source Connected to the data line a 3. The sense amplifier circuit of the semiconductor memory element described in item 1 of the scope of patent application, further comprising an eighth NMOS transistor disposed between the sense amplifier circuit and the complementary data line The drain of the eighth NMOS transistor is coupled to the second node, its gate receives a row of address signals, and its source is connected to the complementary data line. 4. The sense amplifier circuit of the semiconductor memory device described in item 1 of the scope of patent application, wherein the semiconductor memory device includes a dynamic random access memory. 5. The sense amplifier circuit of the semiconductor memory device according to item 1 of the scope of the patent application, wherein the first sense amplification enable signal includes a low-level ground signal. 6. The sense amplifier circuit of the semiconductor memory device described in item 1 of the scope of the patent application, wherein the second sense amplification enable signal includes a high-level voltage signal. 7. The sense amplifier circuit of the semiconductor memory element according to item 1 of the scope of patent application, wherein the voltage level of the first node is equivalent to the voltage level of the bit line. According to the sense amplifier circuit of the semiconductor memory element described in item 1 of the scope of the patent application, the voltage level of the second node is equivalent to the voltage level of the complementary bit line. (Please read the precautions on the reverse side before filling out this page) — Packing _ Order This paper size applies the Chinese National Standard (CNS) A4 specification (210X2? 7cm)