TW425706B - Dynamic random access memory with capacitor and its fabrication method - Google Patents

Abstract

This invention provides the fabrication method of dynamic random access memory that has simple geometry pattern active region, self-aligned crown-shaped capacitor and, bit line and polysilicon plug formed at the same time. First, a semiconductor substrate having active regions is provided, in which plural insulation regions are used to isolate from the other active regions. Gate and inter connection are formed individually on semiconductor substrate and insulation region, additionally, the corresponding source region and drain region are formed on substrate. A silicon nitride layer is deposited on substrate to protect the insulation layer stated above from etching damage. After forming an opening in the insulation layer to expose substrate, the silicon nitride layer is stripped to remain cylinder insulation material on the gate. A polysilicon layer is deposited to connect the exposed source and drain regions, in which the second silicon nitride layer is deposited on this polysilicon layer. A mask layer is used to etch the second silicon nitride layer and the polysilicon layer until the cylinder insulation material so as to form a bit line. This polysilicon layer is made to remain in between cylinder insulation materials such that plural polysilicon flattop plugs connected with the source/drain regions are formed, in which the polysilicon flattop plug located below the bit line constitutes the bit line contact. A mask layer is used to etch the second insulation layer to form plural contact openings so as to expose the polysilicon flattop plug on both sides of bit line. After that, crown-shaped capacitor is formed at the contact opening stated above.

Description

425 7 0 6 V. Description of the invention (1) The present invention relates to a method for manufacturing a dynamic random access memory (DRAM), and in particular to an active area having a simple geometric pattern, Manufacturing method of self-aligned corona capacitor and dynamic random access memory with bit line and polycrystalline silicon plug formed at the same time. Dynamic random access memory (DRAM) has been widely used in electronic components. Most DRAM devices are based on silicon. A typical memory cell usually contains a MOS field effect transistor, and its source is Connected to a storage capacitor. In the traditional manufacturing method of DRAM capacitors, the pattern definition of a contact window is needed as a node of the capacitor, and the pattern definition of the polycrystalline silicon layer is used as the lower plate of the capacitor. However, with the shrinking of the DRAM line width, the aspect ratio of the contact window will increase, which will reduce the effective area of the capacitor. In addition, the traditional s-shaped active area of DRAM has a twisted bit defined. Difficulties occur in the yuan line. Therefore, in the manufacturing technology of DRAM, there is an urgent need to improve the complex active area, contact technology, and capacitor. In U.S. Patent Nos. 4,966, 870 and 5,94 4,682, Barber et al. And Cronin et al. Use a two-stage etching step to make borderless contacts, which are applied to silicon oxide to silicon nitride ^ High Etch Select Ratio. In U.S. Patent No. 5,25,008, Sandhu et al. Used a conductive layer as an etch stop for self-aligned contacts. In U.S. Patent No. 5 '466, 636, Cronin et al. Disclose another method of making a frame contact. In U.S. Patent No. 5,49,104, Ue et al. Used a conductive layer as a protective etch stop layer to make a fin capacitor.

Page 5 425706 V. Description of the Invention (2) In U.S. Patent No. 5,491,103, Ahn et al. Disclosed a method for manufacturing a crown capacitor and bit line contact. Therefore, the main object of the present invention is to provide an efficient and quite manufacturable process for the manufacture of DRAM integrated circuit components. Another object of the present invention is to provide a method for manufacturing a DRAM device having an active region having a simple geometry. Another object of the present invention is to provide a method for manufacturing a DRAM device having a self-aligned crown capacitor. It is still another object of the present invention to provide a method for manufacturing a DRAM device having a bit line and a polycrystalline silicon plug formed at the same time. According to the above method, a crown capacitor is prepared according to the above method of a dynamic region and a self-aligned silicon plug. First, an insulating region is provided and a siliconized layer is formed on the surface of the insulating region substrate to cover the surface of the domain; The purpose further includes providing a simultaneous quasi-coronary capacitor and a dynamic random access memory. The DRAM provided by the present invention has: a simple and a semiconductor with an active region formed at the same time to isolate other active regions A method for forming a source region corresponding to a plurality of gates and a drain electrode, a first nitride-nitride-silicon nitride sidewall layer for the gate, interconnects, and etch-back portions, and a surface residue of the insulating region are respectively formed on the top. What pattern bit line and substrate of DRAM should be deserved. Then pole and plural. After that, the semiconductor-based silicon layer is composed of bit lines and complex methods that are mainly composed of the above-mentioned early geometric patterns. Component manufacturer Active area, self-aligned polycrystalline silicon plug. The main active region is connected by a plurality of 'in the semiconductor substrate, and a first nitrogen substrate is deposited thereon, and a first nitrided sand layer is connected to the gate electrode and the electrode. Insulated area Inner wiring line, half-connected

Page 6 425706 to deposit a first insulating layer over the substrate and form a photoresist mask on this first insulating layer i. Etching: J removes the portion of the first insulating layer that is not covered by the photoresist mask to form a columnar insulator above each gate and each interconnector, where the etching step is performed at The first insulation layer is performed under the condition that the first nitride layer is highly selective, so as to use the first silicon nitride layer to protect the above-mentioned insulating area during the process. After that, the portion of the first silicon nitride layer not covered by the photoresist mask is removed to expose the source and drain regions in the semiconductor substrate. Deposit a polycrystalline silicon layer over the substrate 'and connect the exposed source and drain regions, and deposit a metal silicide layer over this polycrystalline silicon layer' and deposit a second silicon nitride layer over This polycrystalline silicon layer. Secondly, the second silicon nitride layer and the polycrystalline silicon layer are etched with a mask layer until the columnar insulators are waited to form a bit line, and the polycrystalline silicon layer is left on the columnar insulators. To form a plurality of polycrystalline silicon platform plugs connected to the above source / drain regions, wherein the polycrystalline silicon platform plugs located below the bit line can form bit line contacts. In this step, The corners of these columnar insulators are exposed. After the corners exposed by the columnar insulators are etched, the sidewalls of the bit line form a second sidewall layer, and the second sidewall layer is formed at the corners of the columnar insulators. on. First deposit a second insulating layer and then etch the second insulating layer with a cover layer to form a plurality of contact openings to expose the polycrystalline silicon platform plugs. Then, the second insulating layer and the contact openings are exposed along the second insulating layer. A first conductive layer is deposited as a lower electrode of the capacitor. Depositing a third insulating layer on the surface of the first conductive layer, and grinding the third insulating layer 'until the first conductive layer on the upper surface of the second insulating layer is removed to expose the second insulating layer; and then the third insulating layer is removed and Exposed second

425706 ^ ------ 5. Description of the invention (4) 'layer. A capacitor dielectric layer is deposited on the surface of the first conductive layer, and a deposition-conductive layer is overlaid on the capacitor dielectric layer to serve as an electrode on the capacitor 'to complete the manufacturing process of the present invention. In addition, according to another object of the present invention, the present invention further provides an active region with a single geometric pattern, a self-aligned coronal capacitor, and dynamic random access with bit lines and polycrystalline silicon plugs formed in the same manner. Memory. Fundamentally, the DRAM component of Ming includes: an active area on a semiconductor substrate, the active area is obtained by isolating other active areas from a plurality of insulating areas; a plurality, a gate and a plurality of interconnects are respectively located on the semiconductor substrate and the The insulating region, and the corresponding source and drain regions are formed in the substrate; a plurality of gasified rock sidewall layers are located on the sidewalls of the gates and the interconnects; a plurality of complex crystal platform plugs To connect the above source and drain regions; a meta-line 'covers one of the polycrystalline stone platform plugs with a crown-shaped capacitor and covers the bit-line and poly-crystalline silicon platform plugs; The first conductive layer is connected to the polycrystalline silicon platform plug on both sides of the bit 7L line, and forms the lower electrode of the capacitor. The polycrystalline silicon platform plug constitutes the node of the capacitor; a capacitive dielectric layer is overlaid on the first A conductive layer; and a second conductive layer overlying the capacitor dielectric layer to form an upper electrode of the capacitor to complete the dynamic random access memory with a valley device of the present invention. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings FIG. 1 is Top view of a DRAM according to a preferred embodiment of the present invention.

Page 8 425706 V. Description of the invention (5) Figures 2 to 18 are a series of cross-sectional views illustrating the manufacturing process of a preferred embodiment of the present invention. Figures 11A and 11B are schematic cross-sectional views taken along different cuts based on the top view of Figure 1. EXAMPLES The process of manufacturing a DRAM device according to the present invention will be described below with reference to Figures 2 to 18. The top view of the prepared DRAM device is shown in Figure 1. It has an active region with a simple geometric pattern and a self-aligned crown capacitor. And having a bit line and a polycrystalline silicon plug formed at the same time. First, please refer to FIG. 2. The first step is to form a dielectric insulator on the semiconductor substrate 10 to isolate the active area on the substrate. The semiconductor substrate used preferably has a (100) lattice orientation. Shi Xi substrate. Since the above isolation process is a conventional step, for the sake of simplicity, only a part of the dielectric insulator is shown in the figure, and its process is not described in detail. First, a field oxide layer 12 'is formed on a semiconductor substrate or a shallow trench isolation (STI) can be used instead of the field oxide layer. Secondly, a gate oxide layer 14 ′ of a desired thickness is formed on the silicon substrate 10 by a thermal oxidation method, and then a low-pressure chemical vapor deposition (LPCVD) method is used to comprehensively cover the substrate with a thickness of about 500 to 1500 angstroms.复 晶 硅 层 16。 Multiple crystal silicon layer 16. Next, a layer of metal silicide (s i 丨 丨 c 丨 de) 8 is deposited on the polycrystalline silicon layer 16 and its material is, for example, titanium silicide, tungsten silicide, copper silicide, and the like. A layer of silicon nitride (capping 1 ay er) with a thickness of about 1500 to 2500 angstroms is deposited on the metal silicide. Afterwards', the lithography and anisotropic etching techniques are used to define the above-mentioned layers 14, 16, 18, and 20 as required gates 25 and word lines 27,

Page 9 425706_ V. Description of the invention ¢ 6) * As shown in Figure 2. The source / drain structure of the MOS field effect transistor can be formed in the following steps. Figures 2 to 18 use integrated circuit elements forming NMOS as an example. However, those skilled in the art can also manufacture β-produced elements or CMOS elements in accordance with the method of the present invention. As is known to those skilled in the art, a DRAM memory cell is composed of an N-channel field effect transistor and a capacitor, and its peripheral electrical I is usually composed of a CMOS element. Lightly doped source / drain regions (not shown) may be formed by ion implantation. After the lightly doped source / drain structure is completed, a dielectric spacer is then fabricated. In the process of this embodiment, a sidewall layer of a silicon nitride material is formed. When etching, the silicon nitride sidewall layer plays an important role in protecting the field oxide (F0X) or STI. As shown in FIG. 3, a silicon nitride layer 32 is deposited on the substrate to a thickness of about 400 to 1,000 angstroms. Referring to FIG. 4, the silicon nitride layer 32 is etched back to a thickness of about 300 to 900 angstroms, and a silicon nitride sidewall layer 34 is formed on the sidewalls of the gate 25 and the word line 27. And a layer of nitrided silicon nitride film μ ^ silicon nitride film 32 is left on the surface at the horizontal position, the thickness of which is about 50 ~ 150 angstroms, depending on the uniformity of the film thickness and the consistency of the etching rate. Thereafter, heavily doped source and non-electrode regions are formed by ion implantation in a conventional manner. Please refer to FIG. 5, and deposit an insulating layer having a thickness of about 4,000 to 10,000 angstroms on the substrate, for example, a tetraethoxysilane layer (TE0s) or a borophosphosilicate broken glass layer ( BPSG); and then planarizing by chemical mechanical polishing (CMp) or etch-back to obtain a flat surface. Please refer to Fig. 6. After coating the photoresist material on the insulating layer 40, apply it.

4 2 5 7 0 6 V. Description of the invention (7) Defined as a platform-shaped plug photoresist mask 42, and then under the remaining conditions of silicon oxide / nitride as the ratio of plutonium, 'name the insulation layer 4 0 The appropriate gas engraving gas includes CA, CHA, C0, 〇2 'and Ar, can use a reactive ion etching (RIE) machine, with an RF power of 1000 ~ 1 800 watts, at 30 ~ 50mT Etching under a pressure condition of rr, the etching selectivity of silicon oxide to silicon nitride is about 20 · 1. After the engraving is completed, a columnar oxide 40 is left over each gate and interconnect. After this etching step, 'the silicon nitride film 32 still remains on the surface of the substrate' as shown in FIG. 6 ', therefore, FOX or 5? 1 oxide can be protected from the damage of the etching. After that, referring to FIG. 7, under the etching condition that the silicon nitride / silicon oxide is a high selective ratio, the remaining silicon nitride film 32 on the substrate is removed, and is located on the horizontal surfaces of the gate electrode 25 and the word line 27 at the same time. On the silicon nitride film 3 2 — and removed. The last name engraving conditions here are the same reaction chaos as the first money engraving, but the operation is performed under the conditions of 200 ~ 800 watts and 30 ~ 200mTorr '. The etching selection ratio of silicon nitride to silicon oxide is about 4 〇: 1. In this way, the silicon nitride film 32 can be completely removed without damaging the underlying oxides. Referring to Fig. 8, after removing the photoresist mask, a polycrystalline silicon layer 44 having a thickness of about 30004000 angstroms is deposited on the substrate. This polycrystalline silicon layer is further engraved with a thickness of about 900 angstroms to make it remain on the insulating layer 40, as shown in FIG. Next, a layer of metal silicide 50, such as osmium hafnium, is deposited on the polycrystalline silicon layer 44. Then, a cover layer with a thickness of about 1,500 to 2500 Angstroms is deposited on the flat metal oxide compound 50, and the material may be silicon nitride or nitrogen oxide.

d257 〇 6 V. Description of the invention (8) After etching, a part of the silicon nitride layer is etched away, leaving the part shown in FIG. 10. Referring to FIG. 11A, along the opening of the silicon nitride layer, the polycrystalline spar layer 44 and the metal silicide 50 are etched to form bit lines 55 and 57. Meanwhile, no additional etching is required here. The contact plug 46 of the capacitor is naturally formed. In the top view of Figure 1, we can see the distribution of bit lines 55'57. In the figure, the area 48 where the rectangular contact plug 44 overlaps the bit line 55 naturally forms a bit line contact. Figure 丨 丨 β shows the cross section 沿着 along the contact plug direction in Figure 1. In this figure, we can see that the bit line 5 5 is in contact with the bit line 4 8 at the same time. After that, a shallow etching of silicon oxide is performed to etch away the corners 5 8 exposed by the columnar oxide 40 to ensure that the polycrystalline silicon plug contacts 4 6 and 4 8 are not connected together. Please refer to FIG. 12 'to deposit another silicon nitride layer or silicon oxynitride layer on the substrate, and then etch it back by anisotropic etching to form nitrogen on the sidewalls of bit lines 5 5 and 5 7 Silicon sidewall layer 60. As shown in the figure, the formed sidewall layer 60 will be superimposed on the corners of the previously etched columnar oxide β, and then, as shown in FIG. 13, 'the substrate surface is covered with a layer having a thickness of about 7000 to 15000 angstroms. Borophosphosilicate glass (BPSG) 64 or spin-on-glass (SOG) 'is then planarized by heat flow or etch-back. Referring to FIG. 14, a grid-lock capacitor mask 66 'is covered on the BPSG layer to etch the BPSG layer 64 along the mask pattern until the platform plug 46 is exposed to form a self-aligned contact opening 78. Referring to FIG. 15, a conductive layer 68 ′ is formed on the substrate along the existing contour surface as the lower electrode of the crown capacitor; the material of the conductive layer may be

Page 12 425706 V. Description of the invention (9)-It is polycrystalline silicon, tungsten, titanium nitride, etc., and has a thickness of about 300 ～ 丨 〇 〇 〇 angstrom. After that, the conductive layer 68 is completely covered with an oxide layer or a photoresist layer or an organic polymer layer having a thickness of about 50,000 to 10,000 angstroms. Referring to FIG. 16, the oxide layer 62 is polished by the CMP method, while the conductive layer 68 above the BPSG layer 64 is removed, and finally a part of the surface of the second insulating layer 64 is exposed. The exposed BPSG layer 64 and the oxide layer 72 are removed, as shown by the 17th circle. Next, an insulating layer 76 having a high dielectric coefficient is deposited along the contoured surface of the lower electrode. The material of the insulating layer is, for example, tantalum oxide (τ & 205), barium strontium titanate (BST), phosphorus zirconium titanate (PZT), 'silicon oxide / silicon nitride / silicon oxide (0N0), etc., and its thickness is about 3 〇 ~ 2 0 0 Angstroms. After that, a second conductive layer is deposited as the upper electrode plate, and the material thereof may be polycrystalline silicon, tungsten, titanium nitride, or a combination thereof with a thickness of about 50 angstroms. In this way, the lower electrode 68, the capacitor dielectric layer 76, and the upper electrode 80 constitute a coronal valley device 'and the polycrystalline stone platform plug 46 serves as a capacitor node. ° So far, I have completed the production of interconnects and DRAM memory cell capacitors. Figure 1 shows a top view of a completed DRAM cell, and Figure 18 is a schematic cross-sectional view taken along the 18-18 direction in Figure 1. In Figure 1, '55 and 57 represent bit lines, 25 represents word lines perpendicular to the bit lines, and dashed lines in the figure represent openings of capacitors 68/76/80 78 ° formed according to the process of the present invention. DRAM, with simple active area 'self-aligned crown capacitor, and bit line and complex formed at the same time

Page 13 Λ257 0 6 V. Description of the invention (ίο) Crystal plugs. Please refer to FIG. 1 and FIG. 18 at the same time. The following will describe the structure of the DRAM device made by the present invention. The active region of the DRAM element on the substrate 10 is formed by isolating the other active regions of the substrate with the insulating region 12. The gate 25 and the interconnect 27 are formed on the substrate 10 and the insulating region 12, respectively, and the source and drain regions are formed in the semiconductor substrate. D is formed on the sides of the gate 25 and the interconnect 27. There are silicon nitride sidewall layers 34. The complex crystal platform plug 46 is connected to the source electrode; and the pole region 36, and the bit line μ covers a complex crystal ... insert in the center. The capacitor is isolated from the bit line 55 by a silicon nitride layer 52. The first conductive layer 68 is in contact with the polycrystalline silicon platform plug 46 on both sides of the bit line 55, and constitutes the lower electrode of the capacitor: wherein the polycrystalline silicon platform plug 46 is a node of the capacitor. The conductive layer 80 covers the surface of the capacitor dielectric layer as an upper electrode of the capacitor, thereby completing a DRAM element having a crown-shaped capacitor. Although the present invention has been disclosed as above with a preferred embodiment, the bran ::: the present invention 'anyone skilled in the art' * does not depart from the 2 essence of the present invention ::: range β 'when various changes and embellishments can be made, so this The scope of protection shall be determined by the scope of the attached patent application. ’,

Page U

Claims (1)

^ 425706 VI. Scope of Patent Application 1. A method for manufacturing a dynamic random access memory (DRAM) with a capacitor, including the following steps: Provide a semiconductor substrate with an active area, the active area is formed by a plurality of insulating areas The active regions are isolated; a plurality of gates and a plurality of interconnects are formed on the semiconductor substrate and the insulating regions, respectively, and corresponding source regions and drain regions are formed in the substrate; -The first photoresist is the first amount of material; the & layer is a high-nitrided second etched part,-the polycrystalline deposits a first nitride layer and the first nitrided surface part of the insulating region. In the above, the first layer is left; on the layer; the interconnect layer in the edge layer is in the first row, the area is borrowed; the 'parallel connection' in the bottom of the silicon layer is not covered by the above gate, interconnect, semiconductor A silicon layer, a wall layer, and a domain surface remaining on the base gate and the interconnected gates' interconnects, a silicon nitride layer; a photoresist mask, forming a pillar, an insulating layer, and The upper part of the process starts with In the remaining part, the source and the semiconductor substrate deposited on the side wall of the etched-back line are deposited to form a covered insulating-nitride stone, which is covered by the second curtain and the silicon nitride side of the electrodeless region and At this moment, the insulating layer of the insulating layer covers the curtain, and is removed in each gate. The silicon layer of the remaining selection ratio protects the etch, and is removed to expose the silicon layer, which covers the first insulation, the first insulation electrode, and each etch step. Under the condition, the above-mentioned insulating region of the photoresist mask on the first nitrogen semiconductor-based substrate is introduced; the source silicon dinitride layer overlies the polycrystalline silicon layer; Page 15 425706 6. The scope of the patent application uses a masking layer to etch the second silicon nitride layer and the polycrystalline silicon layer until the columnar insulators are used to form a bit line and make the polycrystalline The Shi Xi layer remains between the columnar insulators to form a plurality of polycrystalline silicon platform plugs connected to the source / non-electrode region, and the polycrystalline silicon platform plugs located below the bit line are formed. That is, a bit line contact is formed, and the corners of the branch-shaped insulators are exposed; the corners exposed by the column-shaped insulators are left; a second sidewall layer is formed on the sidewall of the bit line, and the first Two side wall layers are formed on the corners of the etched columnar insulator; a second insulating layer is deposited to cover the substrate; the second insulating layer is etched with a cover layer to form a plurality of contacts ^ 1 : 1 to expose the polycrystalline silicon platform plugs; deposit a first conductive layer 'as the lower electrode of the capacitor along the periphery of the second insulating layer and the contact opening; deposit a third insulating layer over Surface of the first conductive layer, and grind the second insulating layer until the first Removing the first conductive layer on the upper surface of the insulating layer until the second insulating layer is exposed; removing the third insulating layer and the exposed second insulating layer; a deposition-capacitance dielectric layer covering the first conductive layer; and ^ A second conductive layer is deposited on the capacitor dielectric layer to serve as an electrode on the capacitor to complete the manufacture of the dynamic random access memory with the capacitor. 2. The manufacturing method according to item 1 of the patent application scope, wherein the insulating region includes a field oxide. No. 16 True 425706 6. Scope of patent application 3 ‘The manufacturing method described in item 丨 of the scope of patent application, wherein the insulated region includes a shallow trench insulation. 4. The edge-making method as described in item [Scope of the patent application], wherein the thickness of the first silicon nitride layer is 400 to 1000 angstroms. 5. The method of making a house as described in item 1 of the scope of the patent application, wherein the first gasified fossil layer is 50 to 150 angstroms as far as possible after passing through the above part. 6. The edge-making method according to item 1 of the scope of patent application, wherein the first insulating layer includes tetraethoxysilane (TEOS). 7. The manufacturing method according to item 1 of the scope of patent application, wherein the first insulating layer comprises borophosphosilicate glass (BPSG). 8. The manufacturing method according to item 1 of the scope of the patent application, wherein the first insulating layer is planarized by a chemical mechanical polishing method. 9. The manufacturing method as described in item No. 17 of the scope of patent application, wherein the first insulating layer is flattened with a button inscription. 10. The manufacturing method as described in item 1 of the scope of the patent application, wherein the first etching system uses C4F8, CH2F2, CO, 02, Ar and other gases at an rf power of 1000 to 1 800 watts and 30 to 50 mTorr The etching is performed under a pressure of about 200 to about 1 in a silicon oxide to silicon nitride etching selection ratio. Π. The manufacturing method described in item 1 of the scope of patent application, wherein the second name is engraved with gas such as < ^ 8, (: 1 ^ 2, (: 0, 02, eight 1 ^, etc.) between 200 and 800 The etching power is performed under the RF power of 30 watts and a pressure of 30 to 200 mTorr, in which the etching selection ratio of silicon nitride to silicon oxide is about 40: 1. The manufacturing method described in item 1 of the scope of patent application, which includes more Page 17 425706 VI. Application for Patent Park includes depositing a layer of metal silicide on the surface of the polycrystalline silicon layer. 13. The manufacturing method according to item 1 of the patent application scope, wherein the second sidewall layer comprises silicon nitride. 1 4. The manufacturing method according to item 1 of the scope of patent application, wherein the second sidewall layer includes silicon oxynitride. 15. The manufacturing method according to item 1 of the scope of the patent application, wherein the second insulating layer includes a layer of borophosphosilicate glass having a thickness of 7000 to 10,000 angstroms. The surface of the borophosphosilicate glass layer is flattened by heat flow. 1 6. The manufacturing method according to item 1 of the scope of the patent application, wherein the second insulating layer includes a layer of spin-on glass (SOG) having a thickness of 7000 to 10,000 angstroms, and the spin-on glass layer passes through a part of the Etching back planarizes its surface. 17. The manufacturing method according to item 1 of the scope of patent application, wherein the first conductive layer includes one of polycrystalline silicon, tungsten, and titanium nitride. 18_ The manufacturing method according to item 1 of the scope of patent application, wherein the third insulating layer includes a layer of silicon oxide having a thickness of 5000 to 10,000 angstroms. 19. The manufacturing method according to item 1 of the scope of patent application, wherein the capacitor dielectric layer includes an oxide button (Ta205), a titanate gill (BST), a phosphorous titanate (P2T), and silicon oxide / silicon nitride. / Silicon oxide (〇 叩), and the thickness is 30 ~ 200 Angstroms. 20. The manufacturing method according to item 1 of the scope of patent application, wherein the second conductive layer includes one of polycrystalline silicon, tungsten, and titanium nitride, and has a thickness of 500 to 1,500 angstroms. 21. —Dynamic Random Access Memory (DRAM) with capacitor Page 18 425706 VI. Manufacturing method for patent application scope, including the following steps: h. Provide a main area with active area and separate the other active areas from each other;… The active area is composed of a complex pole and a bottom area respectively. Forming a plurality of gate regions; opening a corresponding source region in the substrate> and depositing a -ditride-nitride layer on the above-mentioned ㈣ substrate and the surface of the insulation region; ? —Nitride fragmentation [to the gates and the interconnecting wall layers, and the first silicon nitride layer remaining on the surface of the above-mentioned gates and interconnects; " rough surface area; depositing a first An insulating layer is coated on the substrate; a photoresist mask is formed on the first insulating layer; If Yun 2 ϋ f · etched to remove the M of the first insulating layer that is not covered by the photoresist mask J: A pillar-nitrogen ::: is formed above each gate and each interconnect. The etching step is based on the condition that the first-insulating layer has a surname etch ratio of about 20: 1 to the nitrogen layer. The next step is to use the first silicon nitride layer to protect the above-mentioned insulating area during the engraving process; the second step is to remove the portion of the first nitride layer that is not the photoresist mask f disk to expose A source region of the semiconductor substrate; wherein the remaining step is performed under the condition that the first nitride layer and the first insulating layer have a surname ratio of about 40: 1; depositing a complex crystal A silicon layer covers the substrate and connects the exposed source and drain regions; 4257 〇 6. Apply for a patent. Deposit a metal silicide layer on the polycrystalline silicon layer; deposit a second silicon nitride layer on the metal silicide layer; use a mask layer to etch the second silicon nitride Layer, the metal silicide layer, and the polycrystalline silicon layer until the columnar insulators are formed, thereby forming a bit line, and leaving the polycrystalline silicon layer on the columnar insulators to form A plurality of polycrystalline silicon platform plugs that are connected to the source / drain regions described above, wherein the polycrystalline silicon platform plugs located below the bit line constitute bit line contacts, and the columnar insulation is exposed. Corners of objects; etched corners exposed by the columnar insulators; forming a second sidewall layer on a side wall of the bit line, and the second sidewall layer is formed on the etched columnar insulator At the corners; s depositing a second insulating layer overlying the substrate; engraving the second insulating layer with a mask layer to form a plurality of contact openings to expose the polycrystalline silicon platform plugs on both sides of the bit line A plug; depositing a line along the outline of the second insulating layer and the contact opening A conductive layer is used as the lower electrode of the capacitor; a third insulating layer is deposited on the surface of the first conductive layer, and the third insulating layer is ground until the first conductive layer on the upper surface of the second insulating layer is removed ' Until the second insulating layer is exposed; removing the third insulating layer and the exposed second insulating layer: depositing a capacitor dielectric layer overlying the first conductive layer; and depositing a second conductive layer overlying the capacitor The dielectric layer is used as the electrode on the valley device to complete the manufacture of the dynamic random access memory with a capacitor. Page 20 425706 6. Scope of patent application 22. The manufacturing method as described in item 21 of the scope of patent application, wherein the insulating region includes a field oxide. 2 3. The manufacturing method according to item 21 of the scope of patent application, wherein the insulation region includes a shallow trench insulation. 24. The manufacturing method as described in item 21 of the scope of patent application, wherein the thickness of the first silicon nitride layer is 400 to 1000 Angstroms. 25. The manufacturing method as described in item 21 of the scope of the patent application, wherein the thickness of the first silicon nitride layer after the partial etch-back is 50 to 150 angstroms. 2 6. The manufacturing method according to item 21 of the scope of patent application, wherein the first insulating layer includes tetraethoxysilane (TEOS). 27. The manufacturing method of claim 21, wherein the first insulating layer comprises borophosphosilicate glass (BPSG). 2 8. The manufacturing method according to item 21 of the scope of patent application, wherein the first insulating layer is planarized by a chemical mechanical polishing method. 29. The manufacturing method as described in claim 21, wherein the first insulating layer is planarized by etch-back. 30. The manufacturing method as described in item 21 of the scope of patent application, wherein the first etching is using C4F8, CH2F2, (: 0, 02, Ar and other gases) at an RF power of 100 to 1 800 watts, 30 Etching is performed at a pressure of ~ 50mTorr. 3 1. The manufacturing method described in item 21 of the scope of patent application, wherein the second etching is performed using a gas such as C4F8, CH2F2, CO, 02, Ar, etc. RF power, etching at a pressure of 30 ~ 200mTorr. 3 2. The manufacturing method described in item 21 of the scope of patent application, wherein Page 21 425706 VI. Patent application scope The second sidewall layer includes a 33. The manufacturing method described in item 21 of the patent application scope, wherein the second sidewall layer includes silicon oxynitride. 34. According to the manufacturing method described in item 21 of the scope of the patent application, the second insulating layer includes a layer of borophosphosilicate glass with a thickness of 10,000 angstroms, and the edge borophosphosilicate slope glass layer is subjected to heat flow to Its surface is flat. 35. The manufacturing method as described in item 21 of the scope of patent application, wherein the first insulating layer includes a layer of spin-on glass (SOG) 'having a thickness of 70,000 to 10,000 angstroms, and the spin-on type The glass layer is partially etched back to flatten its surface. 36. The manufacturing method as described in item 2 of the patent application range, wherein the first conductive layer includes one of polycrystalline silicon, tungsten, and titanium nitride. 3 7. The manufacturing method according to item 21 of the scope of patent application, wherein the third insulating layer includes an oxide dream having a thickness of 50004 0000 angstroms. The thickness of phosphorous titanate is _, and the thickness includes: 38, The manufacturing method described in item 21 of the scope of patent application, wherein the capacitor dielectric layer includes tantalum oxide (Ta205), barium strontium titanate (BST) Among them (PZT), oxidized crushed / nitride stone / silicon oxide (NO), is 30 ~ 200 angstroms. 3 9. The manufacturing method according to item 21 of the scope of the patent application. The first conductive layer includes a polycrystalline dream, a crane, and titanium nitride, the degree of which is 500 to 1,500 angstroms. 40. — A kind of dynamic random access memory with a capacitor. An active area on a semiconductor substrate ’is the number of active areas obtained by isolating the other active areas. Page 22 425706 6. The scope of the patent application is that a plurality of gates and a plurality of interconnects are respectively located on the semiconductor substrate and the insulation regions, and the corresponding source region and drain region are formed in the substrate; Two siliconized silicon sidewall layers, located on the side walls of the gates and the interconnects; a plurality of polycrystalline silicon platform plugs connecting the source and drain regions; a bit line covering the polycrystalline silicon One of the silicon platform plugs; a capacitor with a crown shape, comprising: a first conductive layer connected to the polycrystalline silicon platform plugs on both sides of the bit line; wherein the polycrystalline silicon platform plugs The plug constitutes the node of the capacitor, and the first conductive layer constitutes the lower electrode of the capacitor; a capacitor dielectric layer is coated on the first conductive layer; and a second conductive layer is coated on the capacitor dielectric layer. The second conductive layer constitutes the upper electrode of the capacitor, and completes the dynamic random access memory with the capacitor. 41. The dynamic random access memory according to item 40 of the scope of the patent application, wherein the bit line includes: a first polycrystalline silicon layer; a metal silicide layer covering the first polycrystalline silicon layer; A silicon nitride layer is covered on the metal silicide layer; and a plurality of silicon nitride sidewall layers are formed on the sidewall of the bit line. 4 2. The dynamic random access memory according to item 40 of the scope of the patent application, wherein the first conductive layer includes polycrystalline silicon, tungsten, and titanium nitride. Page 23-425706 ____ VI. Patent application scope 4 3. Dynamic random access as described in item 40 of the patent application scope, where the capacitor dielectric layer includes an oxide group (Ta205), an acid Barium crane (BST), phosphorous titanate (ρζτ), one of silicon oxide / silicon nitride / silicon oxide (ON), and the thickness is 30 to 200 angstroms. 44. The dynamic random access memory according to item 40 of the scope of the patent application, wherein the second conductive layer includes one of polycrystalline silicon, tungsten, and titanium nitride— 'and has a thickness of 500 to 1,500 angstroms. 1 ^ 9 Page 24