經濟部智慧財產扇員工消費合作社印製 4 2 56 7 6 A7 _ B7 五、發明說明（） 發明领域： 本發明與一種製造半導體元件之方法有關，待别是製 造反及閉罩幕式唯讀記憶體（NAND-type mask r〇Ms) 之方法β 發明背景： 唯讀記憶體（read-only memories; r〇ms)爲非揮發 性且資料儲存不受電源中斷的影響，已廣泛地應用在電腦 與電子工業。近幾年來攜帶式電腦與電信市場的快速發 展’已成爲積體電路技術與設計的主要驅動力，例如筆記 型電腦、行動電話、攜帶式雷射唱盤等等產業皆對高密度 與高速度的唯讀記憶體有大量需求，上述系統用唯讀記^ 體來儲存永久性的程式’以取代傳统可大量儲存的設備。 非揮發性記憶雜的特性使得罩幕式唯讀記憶體易於 大量生產，但無法重複寫入資料，一般來説罩幕式唯讀記 憶體由错存編碼資料的記憶胞（celi)與記憶胞周圍的控制 元件所組成。每一個記憶胞儲存一位元的資料，每個記憶 胞即爲一個η通道電晶體。有兩種形式的記憶體陣列·· 反或閘（NOR type)記憶體、反及閘（NAND type)記憶體， 其中反或閘記憶體是由一組並聯到位元線（bit Hnes)的金 氧半場效電晶體（MOS)所組成，具有高運作速度的優點， 但其缺點爲積禁度低’原因是每一個記憶胞都必須與位元 2 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閒讀背面之注意事項再填寫本頁> ---------訂---------線------------------------ 425676Printed by the Intellectual Property Fan Employee Consumer Cooperative of the Ministry of Economic Affairs 4 2 56 7 6 A7 _ B7 V. Description of the Invention () Field of the Invention: The present invention is related to a method for manufacturing semiconductor components. Memory (NAND-type mask r〇Ms) method β Background of the invention: Read-only memories (read-only memories; r 0ms) are non-volatile and data storage is not affected by power interruptions, has been widely used in Computer and electronics industry. In recent years, the rapid development of the portable computer and telecommunications market has become the main driving force for integrated circuit technology and design. For example, notebook computers, mobile phones, portable laser discs, and other industries have high density and high speed. There is a large demand for read-only memory. The above-mentioned system uses read-only memory to store permanent programs' to replace traditional mass storage devices. The non-volatile memory makes the mask-type read-only memory easy to mass-produce, but it cannot write data repeatedly. Generally speaking, the mask-type read-only memory consists of celi and memory cells that store coded data by mistake. Composed of surrounding control elements. Each memory cell stores one bit of data, and each memory cell is an n-channel transistor. There are two types of memory arrays: NOR type memory and NAND type memory, where the NOR memory is a group of gold paralleled to a bit line (bit Hnes) Oxygen half field effect transistor (MOS) is composed of MOS, which has the advantage of high operating speed, but its disadvantage is that the degree of accumulation is low. The reason is that each memory cell must be connected to bit 2. This paper size is applicable to the Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page > --------- Order --------- Line ------ ------------------ 425676
五、發明說明（） 線形成接觸，而佔用了大面積。反及閘記憶體的結構則是 由串聯的電晶體所組成，且每组串聯的電晶體與位元線間 只需一個接點，如此一來因爲不必每一記憶胞都浪費大面 積來形成接觸，所以面積可以縮小，且積集度得以提昇。 一般來説罩幕式唯讀記憶體包含有不同起始電壓 (threshold voltage)的MOS電晶體，作爲儲存不同資料 之用。典型的兄憶胞是设計在相同的起始電壓下運作的 MOS電晶體，其電路通常爲導通（ON)狀態’而邏輯狀態 設定爲"1"。某些MOS電晶體則提昇其起始電壓，以設 定其電路狀態爲關閉（OFF) ’邏輯狀態爲"〇"。爲符合错 存電路之設計要求，在製造常態關閉（normally "OFF") 的M〇S電晶體時，以植入高劑量的離子至通道區域 (channel region)的方式提昇其起始電壓，如此一來就可 將邏輯"1〃改寫爲邏輯"〇"的狀態。此離子植入區域則稱 爲編碼區（coding regions) » 其他程式化（programming) 的方法還有增加閘氧化層（gate oxide)厚度、選擇性形成 接觸窗（selective through-hole opening) ' 或是以空乏 型（depletion )電晶體取代增強型（enhancement )電 晶體。V. Description of the invention () The lines make contact and occupy a large area. The structure of the anti-gate memory is composed of a series of transistors, and only one contact is needed between each group of series transistors and bit lines, so that each memory cell does not have to waste a large area to form Contact, so the area can be reduced and the degree of accumulation can be improved. Generally speaking, the mask type read-only memory contains MOS transistors with different threshold voltages for storing different data. A typical sibling memory cell is a MOS transistor designed to operate at the same starting voltage. The circuit is usually in the ON state and the logic state is set to " 1 ". Some MOS transistors increase their starting voltage to set their circuit state to OFF and the logic state is " 〇 ". In order to meet the design requirements of the stray circuit, when manufacturing a normally-off (MOS) transistor, the initial voltage is increased by implanting a high dose of ions into the channel region. In this way, the logic "1" can be rewritten into the state of logic "〇". This ion implantation area is called coding regions »Other programming methods include increasing gate oxide thickness, selectively forming through-hole openings, or Replacement enhancement transistors are replaced by depletion transistors.
在標題爲"MASK ROM FOR STORING PLURAL-BIT DAT A〃 的美國專利中（U.S. patent No.5,406,511) > K. Nogami介紹了反或閘、反及閘罩幕式唯讀記憶體佈局 之俯視圖。在標題爲"METHOD FOR FABRICATING 本纸張尺度適用中國國家標準（CNTS)A.丨規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) -線‘ 經濟部智慧財產局員工消費合作社印*'衣 經濟部智慧財產局員工消費合作社印製 425676 A7 B7 五、發明說明（） LARGE CAPACITY NAND TYPE ROM WITH SHORT MEMORY CELL GATE LENGTH"的美國專利中 (U.S.patent No.5,610,092)，K. Tasaka 介紹了傳統的罩 幕式唯讀記憶體製造過程的剖面囷，但是如C.C, Hsue, et al.等人所描述的（參見 U.S, patent No.5,668,031 entitled "METHOD FOR FABRICATING HIGH DENSITY FALT CELL MASK ROM")罩幕式唯讀記憶體晶圓上的電晶體 在製程中會遭遇到數次的高溫製程，由於某些區域（如位 元線）雜質離子的擴散，造成相鄰位元線的間距變窄，將 導致記憶胞間的穿透效應（cell punch-thro ugh )»由於 記憶元件的技術與需求都傾向於提高晶圓積禁度，所以減 少記憶胞的面積、缩減源極與汲極的間距或相鄰位元線的 間距是必須的，雜質區域的穿透效應也囡此愈形嚴重。 発明目的及概述： 本發明提供了一種製造高密度高速之反及閘罩暮式 唯讀記憶體（NAND-typemaskROMs)的方法，本方法使 用抗反射層以增進曝光時圖案轉移的正確性，在字元線的 區域使用多晶矽化金屬（p〇iycide)以降低電阻値，而立 本發明利用熱擴散之方法將摻質驅入矽基板以形成極淺 接面（ultra- shallow junction)之源極與设極，如此降低 了相鄰位元線間的穿速效應。 首先，薄氧化層、重摻雜的矽層以及氮化矽層依序沈 本紙張尺度適用中國國家標準（CNS)A4規格（2i〇 X 297公釐） I n n n I ϋ n I < n I u i -^eJ Hr n n n 1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4256 7 6 A7 B7 五、發明說明（） 積在半導體基板上，經由標準的微影製程及非等向性蚀刻 可將位元線定義出來。以熱氧化法形成閘極氧化層於基板 上’同時將發屠中的雜質驅入於基板中，而形成極淺接面 之源極與汲極。接著沈積一多晶矽層並以化學機械研磨法 回触之，以形成閘極結構，然後植入離子以調整預設編瑪 區之起始電壓，並在多晶矽層上形成. 守电層作爲芋元線 區域，至此記憶體製程即告完成。 國式簡單説明： 本發明的較佳實施例將於往後之說明文字十輔以下 列圖形做更詳細的闡述： 第一圖爲本發明中沈積薄氧化層、重摻雜之矽層在基 板上之半導體晶圓截面圖； 第二圖爲本發明中沈積氮化矽層於基板上之半導體 晶圓截面圖； 第三圖爲本發明中用微影蚀刻製程定義位元線之半 導體晶圊截面圖； 第四圖爲本發明中形成氮化物間隙壁（Spacer)在石夕 層側壁之半導體晶圓截面圖； 第五圖爲本發明中形成閘氧化層於基板上之半導體 晶圓截面圖； 第六圖爲本發明中形成一多晶發層於基板上並實施 離子植入之半導體晶圓截面圖； 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J I II- — — ———— — — — 我--- --- 訂 _111!* -^ · (請先閱讀背面之注意事項再填寫本頁) 425676 A7 B7 五、發明說明（ 第七圖爲本發明中實施化學機械研磨製裎 矽層之半導體晶圓截面圖； 夕叫 (請先閱讀背面之注意事項再填寫本頁) 本發明中使用離子植入法以形成編碼區之 半導體晶圊截面圖； 第九圖爲本發明中形成一導雷層 夺要增並實砲—高溫退火 過之半導體晶圓截面圖；及 第十圖爲本發明中高密度反及閘罩幕式唯 之半導體晶圓俯視圖。 馎肢 發明掸fa説明： 本 閘罩幕 的習知 積法等 反射層 則採用 熱擴散 shall〇' 間的穿 之反及 製程上 氣相沈 化矽抗 字元線 明使用 (ultra- 字元線 發明所要提出的是一種製造高密、高速度 式唯讀έ己憶體的新方法，本方法包含了許多 技術，例如：微影製程、蝕刻製程以及化學 ，將不在此詳細討論。此外，本發明使用氮 以增加曝光製程中光阻圖案轉移的正確性， 多晶矽化金屬製作以降低電阻値，而且本發 之方法將摻質驅入矽基板以形成極淺接面 λγ丨unction)之源極與汲極，因此降低了相鄰 透效應’本發明整個製作過程描述如下。 經濟部智慧財產局員工消费合作社印製 參閲第一圖’一晶向爲<1〇〇>之單晶矽作爲基板2， 其中隔離區域並不標示出來，本圖例中採用場氧化區域來 代表隔離區。典型的記憶體元件包含記憶胞區（cell area) 與由η通道電晶體所組成之週邊元件區，記憶胞區則由 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ4256 7 6 A7 經 濟 部 智 慧 財 M] 員 X 消 費 合 作 社 印 B7 五、發明說明（） 1己憶胞電晶體組成，因此本發明的第—步你θ + ’ ％尺在基板2 上製作電晶體。一薄氧化層4形成於基板2之μ . 上，此薄氧 化層4可以使用熱氧化法製作，採用的溫度约 & Θ爲攝氏800 至1100度。此外，薄氧化層4也可以使用並袖 -、TO已知的氧 化物及製程來形成’例如可以採用低壓化聲 十虱相沈積法 (LPCVD)來製作沈積層，也可以直接利用原生氧化層 (native oxide film)作爲薄氧化層4。以一軺杜由 , 干又1主貫施例而 言’此薄氧化層4的厚度約爲1〇至30埃。 薄氧化層4形成後，沈積一重摻雜的矽層6於薄氡化 層4之上。矽層6可以採用非晶矽或是多晶矽爲材質，分 别在溫度約爲400至560.C以及575至65(TC下，以化學 氣相沈積法形成。然後對矽層6實施—重劑量的離子植入 製程，將的雜質離子對此多晶矽層6進行重摻雜，其 中植入離子的電性與通道的型態相同，通常通道爲η型了 則植入的離子爲磷離子、砷離子或是銻離子。離子植入的 劑量與能量分别爲5xl〇u至5χ1〇16離子/平方公分、 至150keV。此外，也可以採㈣步摻雜的方式，在梦屠 6沈積的同時將雜質離子捧入其中。 如第二圖户斤^一作爲抗反射層之氮化石夕層8形成於 石夕層6之上，以利後續之微影製程，4匕氮切層8可用任 何適當的製程方法來形丨，例如低壓化學氣相沈積法 (LPCVD ) *及增強式化學氣栢沈積法（PECVD )、 公釐） I- -------- '衣— ί11·!------線- (請先閱讀背面之注意事項再填寫本頁) 425676 五、發明説明（ A7 B7 s 呤！:二 補 經濟部智慧財產局員工消費合作社印製 電子迴旋共振化學氣相沈積法（electr〇n cyclotron resonance CVD, ECRCVD )等。此氮化矽層8的厚度約 爲300至1〇〇〇埃’形成溫度約爲填氏3〇〇至8〇〇度的範 圍。以一較〆圭實施例而τ，反應氣體可爲SiH4、ΝΗ3、 Ν2、Ν2〇或是SiH2CI2、ΝΗ3、Ν2、ν2〇。關於抗反射 看的應用’可參考文獻T.P. Ong, et alw " CVD SiNx Anti-Reflective Coating for Sub-0.5 Lithography ' Symposium on VLSI TECH. Dig·, p· 73, 1995 中所介 紹。 參閱第三圖，以光阻塗佈、曝光、顯影等標準的微 影製程形成光阻10於氮化石夕層8之上，作爲敍刻罩幕， 接著以非等向性蝕刻法定義出基板2上的位元線區域3其 中氮化石夕層8是用來改善光阻曝光時圖案轉移的正確 性。對氮化矽層8的蝕刻採用反應性離子蝕刻法（reactive ion etching, RIE)，以含氟化物的電漿氣體如CF4/〇2、 CF4/H2、CHF3或是NF3爲ϋ刻電聚源。另外，對多晶石夕 層6進行乾蝕刻時使用的電漿源爲ci2、BCI3、HBi·、 或是SiC〖4。囷案化之後的矽層6將覆蓋在記憶雜的位元 線區域之上。 參閲第四囷，使用傳統的方法將光阻1〇去除，然後 形成一介電間隙壁12於氮化矽層8與多晶矽層6的侧 堃。此介電間隙壁12可以採用氧化矽或是氣化砂爲材 各紙張尺度逍用中國固家標準（CNS ) A4规格（210X297公釐） I-----------t------111、-----^ (請先閎讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 425676 A7 -----B7 五、發明說明（） 質，以下述方法製作·首先沈積一層介電質於氮化矽層 8，多晶發層6與薄氧化層4之上，並用非等向性触到法 回蝕此介電層，僅保留部份於氮化矽層8與多晶矽層6 之側壁上，以形成介電間隙璧12。在此同時，薄氣化層4 也受到蝕刻，故基板2介於兩位元線區域之間的部份將會 曝露出來。 接著，如同第五圖中所顯示，重行生成一閘極氧化層 14於基板2的暴露區域上，亦即在矽層6之外，介電間 隙壁12之間的區域（兩位元線區域之間）。此閘極氧化層 14的厚度約在至2〇〇埃之間爲宜，可以採用熱氧化 法，在攝氏溫度约800至11〇〇度之間氧化形成。氧化時 的環境可以採用NO或是N2〇，此時生成的閘極氧化層 14將爲氮氧化矽層。先前所產生的蝕刻損傷將在氧化過 程中恢復，而矽層6中所摻雜的雜質離子也將在此一高溫 製程中受到驅入擴散至基板2之中，形成極淺接面。源極 與及極摻雜區域16於焉形成於矽層6之下的基板中、閘 極氧化層14之間的區域。此時薄氧化層4可作爲緩衝區 域之用。 接下來參見第六圖’以化學氣相沈積法，沈積一掺雜 或同步摻雜的多晶矽層18於基板2之上。在對多晶矽廣 進行雜質掺雜時，可以採用POCh或是P2〇s作爲摻質； 而若是進行同步摻雜製程，則可採用PH3或是AsH3作爲 本紙張尺度適用中國®家標準（CNS)A4規格<210x 297公釐） <請先閱讀背面之注意事項再填寫本頁) ^--------訂----------線- ..... 經濟部智慧財1局員工消费合作社印製 42BB76 五、發明説明（ ΓΛί此：t雜的…層18主要將沈積在間極氧化層 .^ 、層6之外，介電間隙壁12之間的區域 作爲閘電極， 』tu场，以 接著採用化學機械研麻、, P—,，蚀多晶(ch一1—-…爲終止層，H18。此…製程以氮化获 份將被去除，同時達成多；：：。：':::層8以上的部 -1匕。回蝕後所餘下的客 18將由石夕層6及.介電間隙辟u工 ‘、土 予以區隔成分立的都俗， 作爲個别電晶體的閘電極。 參閲第八圖，具宭放—此， 的儲存電路製作編碼=Γ 製程’而根據所設計 的邏輯：狀V二吏編碼後的記憶胞成爲永久性 ^ J. , . 貧先形成一光阻層20於基板2In the US patent entitled "MASK ROM FOR STORING PLURAL-BIT DAT A〃" (US patent No. 5,406,511) > K. Nogami introduces a top view of the layout of the read-only memory of the anti-OR gate, anti-gate screen . Under the title " METHOD FOR FABRICATING, this paper size is applicable to China National Standards (CNTS) A. 丨 specifications (210 X 297 public love) (Please read the precautions on the back before filling this page)-Line 'Ministry of Economics Intellectual Property Printed by the Bureau's Consumer Cooperatives * 'Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Clothing and Economy 425676 A7 B7 V. Description of Invention () LARGE CAPACITY NAND TYPE ROM WITH SHORT MEMORY CELL GATE LENGTH " K. Tasaka introduced a profile of the traditional mask-based read-only memory manufacturing process, but as described by CC, Hsue, et al. Et al. (See US, patent No. 5,668,031 entitled " METHOD FOR FABRICATING HIGH DENSITY FALT CELL MASK ROM ") The transistor on the mask read-only memory wafer will encounter several high temperature processes during the process. Due to the diffusion of impurity ions in some areas (such as bit lines), adjacent Narrow bit line spacing will lead to cell punch-thro ugh effect »Because of the technology and demand of memory elements, it tends to increase the wafer ban , The reduced area of the memory cell, the source and drain to reduce the spacing or pitch of adjacent bit line is necessary, the penetration effect of this impurity region is also nan Yu Xing serious.目的 Purpose and Summary: The present invention provides a method for manufacturing high-density, high-speed NAND-type mask ROMs. This method uses an anti-reflection layer to improve the accuracy of pattern transfer during exposure. The area of the word lines uses polycrystalline silicon (Polycide) to reduce resistance 値, and the invention uses thermal diffusion to drive the dopants into the silicon substrate to form an ultra-shallow junction source and By setting the poles, this reduces the penetrating effect between adjacent bit lines. First, a thin oxide layer, a heavily doped silicon layer, and a silicon nitride layer are sequentially deposited on the paper. The paper is sized to the Chinese National Standard (CNS) A4 (2i0X 297 mm). I nnn I ϋ n I < n I ui-^ eJ Hr nnn 1 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4256 7 6 A7 B7 V. Description of the invention () Built on the semiconductor substrate, the standard The lithography process and anisotropic etching can define bit lines. The gate oxide layer is formed on the substrate by a thermal oxidation method, and the impurities in the process are driven into the substrate to form a source electrode and a drain electrode with a very shallow junction. Then deposit a polycrystalline silicon layer and touch it back by chemical mechanical polishing to form a gate structure, and then implant ions to adjust the initial voltage of the pre-programmed region and form it on the polycrystalline silicon layer. The electro-conducting layer is used as a taro element. Line area, the memory system process is completed. Brief description of the Chinese style: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: The first figure is a thin oxide layer and a heavily doped silicon layer deposited on the substrate in the present invention The second figure is a cross-sectional view of a semiconductor wafer in which a silicon nitride layer is deposited on a substrate in the present invention. The third figure is a semiconductor wafer in which bit lines are defined by a lithographic etching process in the present invention. Cross-sectional view; the fourth view is a cross-sectional view of a semiconductor wafer forming a nitride spacer (sider) on the side wall of a stone layer in the present invention; the fifth view is a cross-sectional view of a semiconductor wafer forming a gate oxide layer on a substrate in the present invention The sixth figure is a cross-sectional view of a semiconductor wafer formed with a polycrystalline layer on a substrate and subjected to ion implantation in the present invention; this paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) JI II- — — — — — — — — I --- --- Order _111! *-^ (Please read the notes on the back before filling out this page) 425676 A7 B7 V. Description of the invention (Seventh picture Chemical mechanical polishing in the present invention Section of the semiconductor wafer cross-section; Xi Jiao (Please read the precautions on the back before filling this page) Cross-sectional view of the semiconductor wafer using ion implantation to form the coding region in the present invention; The ninth diagram is formed in the present invention A lightning guide layer is to be increased and fired—a cross-sectional view of a semiconductor wafer annealed at a high temperature; and the tenth figure is a top view of the semiconductor wafer of the high-density anti-reflection screen type in the present invention. The reflective layer such as the conventional product method of the gate cover uses thermal diffusion and the reverse of the diffuser and the vapor deposition silicon anti-character line on the process (ultra-character line invention is to be proposed A new method for manufacturing high-density, high-speed read-only memory. This method includes many technologies, such as lithography, etching, and chemistry, and will not be discussed in detail here. In addition, the present invention uses nitrogen to increase the exposure process. The correctness of the intermediate photoresist pattern transfer is made of polycrystalline silicon silicide to reduce the resistance 値, and the method of the present invention drives the dopants into the silicon substrate to form the source and drain of the very shallow junction (λγ 丨 unction). Therefore, the adjacent transmission effect is reduced. The entire manufacturing process of the present invention is described as follows. Printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, refer to the first picture. A monocrystalline silicon with a crystal orientation of < 1〇〇 > 2, where the isolation area is not marked, the field oxidation area is used to represent the isolation area in this illustration. A typical memory element includes a memory cell area (cell area) and a peripheral element area composed of an n-channel transistor. The area is based on the Chinese paper standard (CNS) A4 specification (210 X 297 mm). Γ4256 7 6 A7 Member of the Ministry of Economic Affairs M] Member X Consumer Cooperative Print B7 V. Description of the invention (1) Cellular crystal Composition, so the first step of the present invention is to make a transistor on the substrate 2 by θ + '% ruler. A thin oxide layer 4 is formed on the substrate 2 of the substrate. The thin oxide layer 4 can be made by a thermal oxidation method at a temperature of about 800 to 1100 degrees Celsius. In addition, the thin oxide layer 4 can also be formed by using oxides and processes known in the art. For example, the deposition layer can be made by using low-pressure acoustic deposition method (LPCVD), or the native oxide layer can be directly used. (native oxide film) as the thin oxide layer 4. According to one embodiment, the thickness of the thin oxide layer 4 is about 10 to 30 angstroms. After the thin oxide layer 4 is formed, a heavily doped silicon layer 6 is deposited on the thin halide layer 4. The silicon layer 6 can be made of amorphous silicon or polycrystalline silicon, and is formed by a chemical vapor deposition method at a temperature of about 400 to 560 ° C and 575 to 65 ° C. Then, a heavy dose of silicon layer 6 is implemented. In the ion implantation process, the impurity ions are heavily doped with this polycrystalline silicon layer 6. The electrical properties of the implanted ions are the same as the type of the channel. Usually, if the channel is η-type, the implanted ions are phosphorus ions and arsenic ions. Or antimony ions. The dose and energy of ion implantation are 5x10u to 5x1016 ions / cm 2 to 150keV. In addition, it can also be doped in a step-by-step manner to deposit impurities during the deposition of Mengtu 6 Ions are trapped in it. As shown in the second figure, a nitride stone layer 8 as an anti-reflection layer is formed on the stone layer 6 to facilitate the subsequent lithography process. The nitrogen cutting layer 8 can be any suitable Process methods, such as low pressure chemical vapor deposition (LPCVD) * and enhanced chemical vapor deposition (PECVD), mm) I --------- '衣 — ί11 ·!- ---- Line-(Please read the notes on the back before filling this page) 425676 V. Description of the invention (A7 B7 s ！: Electron cyclotron resonance CVD (ECRCVD), etc., printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Erbu, etc. The thickness of this silicon nitride layer 8 is about 300 to 1,000. The formation temperature of Angstrom is about 300 to 800 ° F. In a comparative example, τ, the reaction gas may be SiH4, Ν3, Ν2, Ν2〇 or SiH2CI2, Ν3, Ν2, ν2 〇. About the application of anti-reflection see TP Ong, et alw " CVD SiNx Anti-Reflective Coating for Sub-0.5 Lithography 'Symposium on VLSI TECH. Dig ·, p · 73, 1995. Refer to the In the third figure, a photoresist 10 is formed on the nitride layer 8 by a standard lithography process such as photoresist coating, exposure, and development, and is used as a mask. Then, the substrate 2 is defined by anisotropic etching. In the bit line region 3, the nitride nitride layer 8 is used to improve the accuracy of pattern transfer during photoresist exposure. The silicon nitride layer 8 is etched using reactive ion etching (RIE) to contain Fluoride plasma gas such as CF4 / 〇2, CF4 / H2, CHF3, or NF3 are engraved electropolymerization sources. In addition, the plasma source used in dry-etching the polycrystalline silicon layer 6 is ci2, BCI3, HBi ·, or SiC [4]. The silicon layer 6 will cover the memory bit line area. Referring to the fourth step, the photoresist 10 is removed by a conventional method, and then a dielectric spacer 12 is formed on the side of the silicon nitride layer 8 and the polycrystalline silicon layer 6. The dielectric partition wall 12 can be made of silicon oxide or gasified sand for various paper sizes. It can be used in accordance with China Solid Standard (CNS) A4 (210X297 mm) I ----------- t- ----- 111, ----- ^ (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 425676 A7 ----- B7 V. Description of Invention ( ), It is made by the following method. First, a layer of dielectric is deposited on the silicon nitride layer 8, the polycrystalline layer 6 and the thin oxide layer 4, and the dielectric layer is etched back by anisotropic contact method. The remaining portions are on the sidewalls of the silicon nitride layer 8 and the polycrystalline silicon layer 6 to form a dielectric gap 璧 12. At the same time, the thin gasification layer 4 is also etched, so the part of the substrate 2 between the two-element line regions will be exposed. Then, as shown in the fifth figure, a gate oxide layer 14 is re-formed on the exposed area of the substrate 2, that is, the area between the dielectric spacers 12 (the two-bit line area) outside the silicon layer 6. between). The thickness of the gate oxide layer 14 is preferably between about 200 angstroms and can be formed by oxidation using a thermal oxidation method at a temperature of about 800 to 1100 degrees Celsius. The environment during oxidation can be NO or N2O, and the gate oxide layer 14 generated at this time will be a silicon oxynitride layer. The previously generated etching damage will be recovered during the oxidation process, and the impurity ions doped in the silicon layer 6 will be driven into the substrate 2 and diffused into the substrate 2 during this high temperature process to form an extremely shallow junction. The source and gate doped regions 16 are regions between the gate oxide layer 14 in the substrate where the ytterbium is formed under the silicon layer 6. In this case, the thin oxide layer 4 can be used as a buffer area. Next, referring to FIG. 6 ', a doped or synchronously doped polycrystalline silicon layer 18 is deposited on the substrate 2 by a chemical vapor deposition method. In the impurity doping of polycrystalline silicon, POCh or P2Os can be used as the dopant; if the simultaneous doping process is used, PH3 or AsH3 can be used as the paper standard for China® Home Standard (CNS) A4 Specifications < 210x 297 mm) < Please read the notes on the back before filling this page) ^ -------- Order ---------- Line-..... Economy Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property 1 Bureau 42BB76 V. Description of the invention (ΓΛί This: t ... layer 18 will be mainly deposited on the interlayer oxide layer. ^, The area outside layer 6, and the area between the dielectric gap wall 12 As the gate electrode, the "Tu field" is followed by chemical mechanical research, P-, and poly-etching (ch-1 —-... as the termination layer, H18. This process will be removed by nitriding, and at the same time Achieved more ::::: '::: Ministry -1 dagger above layer 8. The remaining guest 18 after etch back will be separated by the stone layer 6 and the dielectric gap. As the gate electrode of individual transistors, refer to the eighth figure, with a put --- this, the storage circuit production code = Γ process' and according to the designed logic: State V Memory cells become permanent after the code ^ J.,. Depleted first forming a photoresist layer 20 on the substrate 2
Si區微：製程將編碼區定義出來，使光阻覆蓋住 ==的：有區域。然後利用光阻層2。作爲離子植 入時的罩幕’將重劑量的雜質離子植入基板： 阻層2〇覆蓋的通道區域之中，形成編碼區22。主中植入 :質=電性與通道的型態相反’以增加電晶㈣起始電 壓。對於η型的通道，所植入的雜热 例如硼離子（Β + )戈是二氟化逛斗 ‘ P3L雜質， ^ ^ . 一 一 離子（BF2 + )。編碼後的記憶 胞則成爲水久性的邏輯"〇"狀態。離子植入㈣量與能量 =5χ10η至5xl〇15離子/平方公分、8〇至通… 此外第八圖中的箭頭方向即爲離子植入的方向。 10 I^"I I— 線—-- (請先聞讀背面之注意事項再填寫本頁) 本纸張適用tug)家榡準（CNS ) （2丨⑴97公董） 42^6 τβ Α7 ---—.____Β7 五、發明説明（） (請先Μ讀背面之注$項再填寫本頁) 如第九囷所示’在光阻層2〇除去後，將字元線區域 (word line regions )24按照下述兩個步驟定義於基板2 之上。首先沈積一導電層於基板2之上，較佳的導電層的 材質爲銦、鎢、銅、始、鎳等金屬，其他金屬矽化物如二 矽化鎢（WSiz )也是適當的選擇β此導電層經微影製程 與非等向性蝕刻之後成爲字元線區域24。 最後’進行一溫度約爲攝氏800度至1100度之高溫 退火製程’編碼區22以及源極與汲極區16中之掺質經此 製程後將被活化’而形成較佳分佈，同時一多晶梦化金屬 也形成於矽層18與位元線區域24之間，使得位元線區域 24的電阻降低，元件的操作速度囡此提昇。另外極淺接 面之源極與汲極也使得後續高溫製程帶來的穿透效應得 以避免9 經濟部智慧財產局員工消費合作社印製 第十圖顯示本發明高密度高速度反及閘罩幕式唯讀 記憶體之俯視圖，區域26表示由閘極電極is與閘極氧化 層14所構築的字元線區域，區域28表示位元線圖案，也 就是前述圖形中標示爲16的區域，A A'截面則顧示於前 述本説明書中的第一圖至第九圖，以作爲本發明各階段製 程説明之輔助參考。 本發明提供一種製造具有高密度高速度特性之反及 閘罩幕式唯讀記憶體的斩方法，使用氮化矽作爲抗反射層 以增加製作閘極時光罩圖形轉移的正確性，如此可増加元 本紙張尺度適用中國國家揉準（CNS ) Α4说格（210X297公釐） 425676 五、發明說明（） 件的積集度而達到高封裝密度。摻質經高溫退火製程後由 矽層6擴散至基板2中，而形成位於兩相鄰閘極間的極淺 接面之源極與汲極，此極淺接面之源極與汲極可以減輕後 績高溫製程所造成的相鄰閘極間之穿透現象。在擴散的同 時，一多晶矽化金屬也形成於多晶矽層18與字元線區域 24之間，使得字元線區域24的電阻降低，元件的操作速 度因此提昇。根據本發明之方法可製作出具有高密度高速 度特性而不會產生穿速現象的反及閘罩幕式唯讀記憶 體。 以上所述僅爲本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脱離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 I - -- *n I- 1 -- n- n t J ϋ n .^1 ^1.-^--^* Hi ^1- n n I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 本纸張尺度適用中固國家標準（CNS)A:i規格（210 X 297公釐）Si area micro: The process defines the coding area so that the photoresist covers ==: there is an area. Then a photoresist layer 2 is used. As a mask for ion implantation, a heavy amount of impurity ions are implanted into the substrate: in the channel region covered by the resist layer 20, a coding region 22 is formed. Implantation in the main: the quality = electrical is opposite to the shape of the channel ’to increase the initial voltage of the transistor. For n-type channels, the implanted heterogeneous heat, such as boron ion (B +), is a difluoride ‘P3L impurity, ^ ^. One ion (BF2 +). The coded memory cell then becomes a state of long-term logic " 〇 ". The amount and energy of ion implantation = 5x10η to 5x1015 ions / cm 2, 80 to 10 ... In addition, the direction of the arrow in the eighth figure is the direction of ion implantation. 10 I ^ " II— LINE —-- (Please read the notes on the back before filling in this page) This paper is suitable for tug) Furniture Standard (CNS) (2 丨 ⑴97 公 董) 42 ^ 6 τβ Α7- ---.____ Β7 V. Description of the invention () (Please read the note on the back side before filling in this page) As shown in the ninth paragraph, after the photoresist layer 20 is removed, the word line area (word line regions) 24 are defined on the substrate 2 according to the following two steps. First, a conductive layer is deposited on the substrate 2. The material of the preferred conductive layer is indium, tungsten, copper, metal, nickel, etc. Other metal silicides such as tungsten disilicide (WSiz) are also appropriate choices. Β This conductive layer After the lithography process and the anisotropic etching, the word line region 24 is formed. Finally, a high temperature annealing process is performed at a temperature of about 800 ° C to 1100 ° C. The dopants in the coding region 22 and the source and drain regions 16 will be activated after this process to form a better distribution. The crystallized metal is also formed between the silicon layer 18 and the bit line region 24, so that the resistance of the bit line region 24 is reduced, and the operation speed of the device is increased. In addition, the extremely shallow junction of the source and the drain also prevents the penetration effect brought by the subsequent high-temperature process. 9 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The tenth figure shows the high density and high speed of the present invention. In the top view of the read-only memory, the area 26 represents the word line area constructed by the gate electrode is and the gate oxide layer 14, and the area 28 represents the bit line pattern, which is the area labeled 16 in the aforementioned figure. A The A 'cross section is shown in the first to ninth figures in the foregoing description, and is used as an auxiliary reference for the process description of each stage of the present invention. The invention provides a chopping method for manufacturing an anti-gate gate type read-only memory with high density and high speed characteristics, using silicon nitride as an anti-reflection layer to increase the correctness of the mask pattern transfer when making the gate, so that it can be increased. The original paper size is applicable to the Chinese National Standard (CNS) A4 grid (210X297 mm) 425676 V. Description of the invention () The degree of accumulation of parts to achieve high packaging density. The dopant diffuses from the silicon layer 6 into the substrate 2 after the high-temperature annealing process, and forms a source and a drain of an extremely shallow junction between two adjacent gates. The source and the drain of the shallow junction can be Alleviate the phenomenon of penetration between adjacent gates caused by subsequent high-temperature processes. At the same time of diffusion, a polycrystalline silicon silicide is also formed between the polycrystalline silicon layer 18 and the word line region 24, so that the resistance of the word line region 24 is reduced, and the operation speed of the device is thereby increased. According to the method of the present invention, an anti-reverse shutter-type read-only memory having high-density and high-speed characteristics without causing the phenomenon of a through-speed can be produced. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application. I--* n I- 1-n- nt J ϋ n. ^ 1 ^ 1 .- ^-^ * Hi ^ 1- nn I (Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives, the paper size applies to the China National Standard (CNS) A: i specification (210 X 297 mm)