4 23 21 6 5351twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（i ) 本發明是有關於一種輸出緩衝器，且特別是有關於 一種可控制上推電阻之輸出緩衝器。 S靑參照第1圖，其所繪示爲習知三態輸出緩衝器之 電路圖。此二態輸出緩衝器50包括致能控制電路20、 反相緩衝器電路3〇與pm〇S上推電晶體40。 致能控制電路20包括反及閘22、反閘24與反或 聞26 ’輸入訊號端以及致能訊號端作爲反及閘22之輸 入端，致能訊號端經過反閘24將致能訊號反相後並與 輸入訊號端作爲反或閘26之輸入端。 反相緩衝器電路3〇包括PMOS電晶體32與NMOS 電晶體34，PMOS電晶體32源極耦接至高電壓源（vdd)， PMOS電晶體32閛極耦接至反及閘22之輸出端’ pM〇s 電晶體32汲極耦接至丽〇s電晶體34汲極，丽〇s電 晶體34鬧極親接至反或閘26之輸出端，NMOS電晶體 34源極耦接至低電壓源（Gnd)，而nm〇S電晶體34汲 極亦作爲此二態輸出緩衝器5〇之亦即有一上推電阻。 而，PM〇S上推電晶體40源極耦接至高電壓源， PMOS上推電晶體4〇閘極耦接至致能訊號端，pM〇s上 推電晶體40汲極耦接至輸出訊號端。 當致能訊號爲低準位時’此三態輸出緩衝器50停 止動作，首先，致能控制電路2〇內之反及閘22之輸出 端爲高準位，同時，反或閘26之輸出端爲低準位，而 反相緩衝器電路3〇內之PM0S電晶體32與NM〇s電晶 體34同時呈現關閉狀態，亦即，在輸出訊號端可視爲 (請先閱續背面之注意事項再填寫本頁)4 23 21 6 5351twf.doc / 008 A7 B7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by Du V. Description of the invention (i) The present invention relates to an output buffer, and in particular to a controllable push-up resistor Output buffer. That is, referring to FIG. 1, it shows a circuit diagram of a conventional three-state output buffer. The two-state output buffer 50 includes an enable control circuit 20, an inverting buffer circuit 30 and a pMOS push-up transistor 40. The enabling control circuit 20 includes an anti-gate 22, an anti-gate 24 and an anti-OR 26 'input signal terminal, and an enabling signal terminal as an input terminal of the anti-gate 22. The enabling signal terminal passes the anti-gate 24 to reverse the enabling signal. After the phase and the input signal terminal as the input terminal of the anti-OR gate 26. The inverting buffer circuit 30 includes a PMOS transistor 32 and an NMOS transistor 34. The source of the PMOS transistor 32 is coupled to a high voltage source (vdd), and the pole of the PMOS transistor 32 is coupled to the output terminal of the inverse gate 22 ' The drain of the pMOS transistor 32 is coupled to the drain of the transistor 34, the transistor 34 is connected to the output of the OR gate 26, and the source of the NMOS transistor 34 is coupled to a low voltage. Source (Gnd), and the drain of the nmOS transistor 34 also serves as the two-state output buffer 50, that is, there is a push-up resistor. In addition, the source of the transistor 40 on the PMMOS is coupled to a high voltage source, the gate of the transistor 40 on the PMOS is coupled to the enable signal terminal, and the drain of the transistor 40 on the pMOS is coupled to the output signal. end. When the enable signal is low level, this tri-state output buffer 50 stops operating. First, the output terminal of the inverting gate 22 in the enabling control circuit 20 is at a high level, and at the same time, the output of the inverting OR gate 26 Terminal is low level, while the PM0S transistor 32 and NM0s transistor 34 in the inverting buffer circuit 30 are turned off at the same time, that is, the output signal terminal can be regarded as (please read the precautions on the back side first) (Fill in this page again)
2 3 21 6 5351twf.doc/008 經濟部智慧財產局員工消費合作社印製 A7 B7_ 五、發明說明（> ) 高阻抗狀態，而由於此時PMOS上推電晶體40開啓， 其可視爲一個上推電阻將輸出訊號端電壓提升至高準 位。 當致能訊號爲高準位時，此三態輸出緩衝器50開 始動作，首先，PMOS上推電晶體40關閉，假設此時輸 入訊號端爲高準位，致能控制電路20內之反及閘22之 輸出端爲低準位，同時，反或閘26之輸出端爲低準位， 所以反相緩衝器電路30內之PMOS電晶體32開啓而 NMOS電晶體34關閉，輸出訊號端即爲高準位。假設 此時輸入訊號端爲低準位，致能控制電路20內之反及 閘22之輸出端爲高準位，同時，反或閘26之輸出端爲 高準位，所以反相緩衝器電路30內之PMOS電晶體32 關閉而NMOS電晶體34開啓，輸出訊號端即爲低準位。 請參照第2圖，其所繪示爲以二個習知三態輸出緩 衝器所構成之匯流排（bus)結構之電路圖。通常多個三 態輸出緩衝器的輸出訊號端耦接在一起並以一個匯流排 結構來p出訊號。所以，在任何的時段都最多只能夠有 一個三態輸出緩衝器動作並使用此匯流排，而其它三態 輸出緩衝器則不能夠動作。 首先，假設此二個三態輸出緩衝器60、150不動作， 則第一與第二致能訊號輸入低準位，此時只有第一 PMOS 上推電晶體140與第二PMOS上推電晶體90開啓，作 爲上推電阻，並將輸出訊號端提升至高準位。 接著，在第二三態輸出緩衝器60動作的情況下， 4 <請先閲讀背面之注意事項再填寫本頁)2 3 21 6 5351twf.doc / 008 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ 5. Description of the invention (>) At this time, the PMOS push-up transistor 40 is turned on, which can be regarded as an on Pushing the resistor raises the voltage at the output signal terminal to a high level. When the enable signal is at the high level, the tri-state output buffer 50 starts to operate. First, the PMOS push-up transistor 40 is turned off. Assuming that the input signal terminal is at the high level at this time, the enable in the control circuit 20 is reversed. The output terminal of the gate 22 is at a low level, and at the same time, the output terminal of the inverse OR gate 26 is at a low level, so the PMOS transistor 32 in the inverting buffer circuit 30 is turned on and the NMOS transistor 34 is turned off. The output signal terminal is High level. It is assumed that the input signal terminal is at a low level at this time, the output terminal of the enabling circuit 22 in the control circuit 20 and the output terminal of the gate 22 are at a high level, and the output terminal of the inverter circuit 26 is at a high level. The PMOS transistor 32 in 30 is turned off and the NMOS transistor 34 is turned on. The output signal terminal is at a low level. Please refer to Figure 2, which shows a circuit diagram of a bus structure composed of two conventional tri-state output buffers. Usually, the output signal terminals of multiple tri-state output buffers are coupled together and p-output signals with a bus structure. Therefore, at most one time, only one tri-state output buffer can operate and use this bus, while other tri-state output buffers cannot operate. First, assuming that the two tri-state output buffers 60 and 150 do not operate, the first and second enable signals are input to a low level. At this time, only the first PMOS push-up transistor 140 and the second PMOS push-up transistor are input. 90 is turned on as a push-up resistor, and the output signal terminal is raised to a high level. Next, when the second three-state output buffer 60 is operating, 4 < Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 2 3 216 - A7 5351twf,doc/008 β7 五、發明說明（） 第一致能訊號輸入低準位，第二致能訊號輸入高準位， 假設此時第二輸入訊號端爲高準位，會使得第二三態輸 出緩衝器內之PMOS電晶體82動作，並由於第一 PMOS 上推電晶體140亦開啓，作爲上推電阻，所以輸出訊號 端會提升至高準位。 最後，在第二三態輸出緩衝器60動作的情況下， 第一致能訊號輸入低準位，第二致能訊號輸入高準位， 假設此時第二輸入訊號端爲低準位，會使得第二三態輸 出緩衝器內之NMOS電晶體84動作而將輸出訊號端拉 至低準位，但是此時由於第一 PMOS上推電晶體140開 啓，作爲上推電阻，所以當輸出訊號端爲低準位時會產 生一條電流路徑，由高電壓源經第一 PMOS上推電晶體 140再經第二NMOS電晶體84流向低電壓源。 假設此第一 PMOS上推電晶體140以及第二NMOS 電晶體84的等效電阻分別爲&與R2，則此電流路徑的 電流大小爲： (高電壓源-低電壓源）/ ( Ri+h) =VDD/ ( Rt+R2) 輸出訊號端電壓爲： (高電壓源-低電壓源）x R2/( R,+R2)=VDDx R2/( 1+Ϊ12) 所以習知三態輸出緩衝器在此條件之下會有無謂的 直流電流產生，其會浪費電功率，再者，此時的輸出訊 號端亦不是理想的低準位。 因此本發明係提供一種可控制上推電阻之輸出緩衝 器，利用一個單穩態電路以及PMOS電晶體，在三態輸 5 ------—^---「'-1-裝--------訂---------tyl (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 23216 - A7 5351twf,doc/008 β7 五、發明說明（G ) 出緩衝器未被致能時，將輸出訊號端電壓上推至高準 位。 本發明係提供一種可控制上推電阻之輸出緩衝器， 利用一個監視電路，使輸出訊號端在高準位時提供一個 上推電阻使輸出訊號端維持在高準位，並在輸出端電壓 變爲低準位時將監視電路內之上推電阻關閉，避免無謂 的直流電流流動以及電功率的損耗。 本發明提出一種可控制上推電阻之輸出緩衝器，其 簡述如下： 三態緩衝器具有致能訊號端、輸入訊號端與輸出訊 號端，並在致能訊號端爲未致能準位時，輸出訊號端呈 現高阻抗狀態，而在致能訊號端爲致能準位時，輸入訊 號端之訊號會傳遞至輸出訊號端。單穩態電路輸入端耦 接至致能訊號端，單穩態電路輸出端正常狀態維持在高 準位，當單穩態電路之輸入端狀態由致能準位轉變爲未 致能準位時，該單穩態電路輸出端輸出特定時間之低準 位，並在特定時間之後單穩態電路輸出端回復爲高準 位。第一 PMOS上推電晶體閘極耦接至單穩態電路輸出 端，第一 PMOS上推電晶體源極耦接至高電壓源，第一 PMOS上推電晶體汲極耦接至輸出訊號端，第一PMOS 上推電晶體係在單穩態電路之輸出端輸出低準位時開啓 第一 PMOS上推電晶體，並將輸出訊號端提升至高準位， 在單穩態電路之輸出端輸出高準位時關閉第一 PMOS上 推電晶體。監視電路之監視端耦接至輸出訊號端，用以 6 (請先閱讀背面之注意事項再填寫本頁) I ----- )-OJk n 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 >= 297公釐） A7 B7 4 2 3 216 ^ 5351twf,doc/008 五、發明說明（匕） 在輸出訊號端爲高準位時提供上推電阻耦接於高電壓源 與輸出訊號端之間，並在輸出訊號端爲低準位時關閉耦 接於高電壓源與輸出訊號端之間的上推電阻。 本發明提出一種可控制上推電阻之輸出緩衝器，其 簡述如下： 三態緩衝器具有致能訊號端、輸入訊號端與輸出訊 號端’並在致能訊號端爲低準位時，輸出訊號端呈現高 阻抗狀態，在致能訊號端爲高準位時，將輸入訊號端之 訊號傳遞至輸出訊號端。單穩態電路輸入端耦接至致能 訊號端，單穩態電路之輸出端正常狀態係維持在高準 位，當單穩態電路之輸入端狀態由高準位轉變爲低準位 時，單穩態電路之輸出端輸出特定時間之低準位，並在 特定時間之後單穩態電路之輸出端回復爲高準位。第一 PMOS上推電晶體閘極耦接至單穩態電路輸出端，第一 PMOS上推電晶體源極耦接至高電壓源，第一 PMOS上 推電晶體汲極耦接至輸出訊號端，第一PMOS上推電晶 體係在.單穩態電路之輸出端輸出低準位時開啓第一 PMOS上推電晶體，並將輸出訊號端提升至高準位，在 單穩態電路之輸出端輸出高準位時關閉第一 PMOS上推 電晶體。監視電路之監視端耦接至輸出訊號端，用以在 輸出訊號端爲高準位時提供上推電阻耦接於高電壓源與 輸出訊號端之間，並在輸出訊號端爲低準位時關閉耦接 於高電壓源與輸出訊號端之間的上推電阻。 本發明提出一種可控制上推電阻之輸出緩衝器，其 ---——— — —--·裝 i -,-.V- (請先閱讀背面之注意事項再填寫本頁) 訂- 經濟部智慧財產局員工消費合作杜印製 私紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐 4 23 216 崎 A7 5351twf,doc/008 五、發明說明（厶） 簡述如下： 反及閘輸入端耦接至輸入訊號端以及致能訊號端。 第一反閘輸入端耦接至致能訊號端。反或閘輸入端耦接 至輸入訊號端以及第一反閘輸出端。PMOS電晶體源極 耦接至高電壓源，而PMOS電晶體閘極耦接至反及閘輸 出端。NMOS電晶體汲極耦接至PMOS電晶體汲極，NMOS 電晶體閘極耦接至反或閘輸出端，NMOS電晶體源極耦 接至低電壓源，並且NMOS電晶體汲極係作爲輸出訊號 端。屬於負緣激發的D型正反器，此D型正反器之時脈 輸入端耦接至致能訊號端，D型正反器之輸入端耦接至 低電壓源，而當D型正反器之設定端接收到低準位時， D型正反器之輸出端輸出高準位。延遲電路係用來控制 特定時間的大小，延遲電路輸入端耦接至D型正反器輸 出端，延遲電路輸出端耦接至D型正反器設定端。第一 PMOS上推電晶體閘極耦接至D型正反器輸出端，第一 PMOS上推電晶體源極耦接至高電壓源，第一 PMOS上 推電晶體汲極耦接至輸出訊號端。第二反閘輸入端耦接 至輸出訊號端。第二PMOS上推電晶體閘極耦接至第二 反閘輸出端，第二PMOS上推電晶體源極耦接至高電壓 源，第二PMOS上推電晶體汲極耦接至輸出訊號端。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明：This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 2 3 216-A7 5351twf, doc / 008 β7 V. Description of the invention () The first consistent energy signal is input at a low level, the second is enabled The high level of the signal input. Assuming that the second input signal terminal is at the high level at this time, the PMOS transistor 82 in the second tri-state output buffer will act, and because the first PMOS push-up transistor 140 is also turned on, as Push up the resistor, so the output signal end will rise to a high level. Finally, when the second tri-state output buffer 60 operates, the first consistent signal is input to the low level, and the second enable signal is input to the high level. Assuming that the second input signal terminal is at the low level, The NMOS transistor 84 in the second tri-state output buffer is activated to pull the output signal terminal to a low level. However, at this time, the first PMOS push-up transistor 140 is turned on as a push-up resistor, so when the output signal terminal When the level is low, a current path is generated, and the high voltage source flows through the first PMOS push-up transistor 140 and then the second NMOS transistor 84 to the low voltage source. Assuming that the equivalent resistances of the first PMOS push-up transistor 140 and the second NMOS transistor 84 are & and R2, respectively, the current magnitude of this current path is: (high voltage source-low voltage source) / (Ri + h) = VDD / (Rt + R2) The output terminal voltage is: (high voltage source-low voltage source) x R2 / (R, + R2) = VDDx R2 / (1 + Ϊ12) So the tri-state output buffer is known Under this condition, there will be unnecessary DC current generated by the device, which will waste electrical power. Moreover, the output signal terminal at this time is not the ideal low level. Therefore, the present invention provides an output buffer capable of controlling the push-up resistor, using a monostable circuit and a PMOS transistor to output 5 in the three states. -------- ^ --- "'-1- 装- ------- Order --------- tyl (Please read the notes on the back before filling out this page) Printed on paper standards for employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, this paper applies Chinese national standards (CNS ) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 23216-A7 5351twf, doc / 008 β7 V. Description of the invention (G) When the buffer is not enabled, the signal terminal voltage will be output The invention provides an output buffer capable of controlling the push-up resistor. The invention uses a monitoring circuit to make the output signal terminal provide a push-up resistor to maintain the output signal terminal at a high level, When the voltage at the output terminal becomes low, the push-up resistor in the monitoring circuit is turned off to avoid unnecessary DC current flow and electrical power loss. The present invention provides an output buffer that can control the push-up resistor, which is briefly described as follows : Tri-state buffer with enable signal , The input signal terminal and the output signal terminal, and when the enable signal terminal is not enabled, the output signal terminal shows a high impedance state, and when the enable signal terminal is the enable level, the signal of the input signal terminal will Passed to the output signal terminal. The input terminal of the monostable circuit is coupled to the enable signal terminal. The normal state of the output of the monostable circuit is maintained at a high level. When the state of the input terminal of the monostable circuit changes from the enabled level to When the level is not enabled, the output of the monostable circuit outputs a low level for a specific time, and after a specific time, the output of the monostable circuit returns to a high level. The first PMOS push-up transistor gate is coupled To the monostable circuit output, the first PMOS push-up transistor source is coupled to the high voltage source, the first PMOS push-up transistor drain is coupled to the output signal terminal, and the first PMOS push-up transistor system is monostable. When the output of the state circuit outputs a low level, the first PMOS push-up transistor is turned on, and the output signal terminal is raised to a high level. When the output of the monostable circuit outputs a high level, the first PMOS push-up transistor is turned off. .Monitoring terminal coupling of monitoring circuit To the output signal end, for 6 (Please read the precautions on the back before filling this page) I -----) -OJk n 1 This paper size applies to China National Standard (CNS) A4 specification (210 > = 297 (Mm) A7 B7 4 2 3 216 ^ 5351twf, doc / 008 V. Description of the invention (dagger) When the output signal terminal is at a high level, provide a push-up resistor coupled between the high voltage source and the output signal terminal, and When the output signal terminal is at a low level, the push-up resistor coupled between the high-voltage source and the output signal terminal is turned off. The present invention provides an output buffer capable of controlling the push-up resistor, which is briefly described as follows: The energy signal terminal, the input signal terminal and the output signal terminal 'and when the enable signal terminal is at a low level, the output signal terminal shows a high impedance state, and when the enable signal terminal is at a high level, the signal of the input signal terminal is passed To the output signal end. The input terminal of the monostable circuit is coupled to the enable signal terminal. The normal state of the output of the monostable circuit is maintained at a high level. When the state of the input of the monostable circuit changes from a high level to a low level, The output of the monostable circuit outputs a low level at a specific time, and the output of the monostable circuit returns to a high level after a specific time. The first PMOS push-up transistor gate is coupled to the monostable circuit output, the first PMOS push-up transistor source is coupled to the high voltage source, and the first PMOS push-up transistor drain is coupled to the output signal terminal. The first PMOS push-up transistor system turns on the first PMOS push-up transistor when the output of the monostable circuit outputs a low level, and raises the output signal terminal to a high level, and outputs it at the output of the monostable circuit. When the level is high, the first PMOS push-up transistor is turned off. The monitoring end of the monitoring circuit is coupled to the output signal end, and is used to provide a push-up resistor when the output signal end is at a high level and coupled between the high voltage source and the output signal end, and when the output signal end is at a low level Turn off the push-up resistor coupled between the high voltage source and the output signal terminal. The present invention proposes an output buffer capable of controlling a push-up resistor, which is equipped with i-,-. V- (Please read the precautions on the back before filling this page) Order-Economy The consumer property cooperation of the Ministry of Intellectual Property Bureau Du printed private paper standards applicable to the Chinese National Standard (CNS) A4 specifications (21 × 297 mm 4 23 216 A7 5351twf, doc / 008 5. Description of the invention (厶) Brief description is as follows: The inverter input terminal is coupled to the input signal terminal and the enable signal terminal. The first inverter input terminal is coupled to the enable signal terminal. The inverter input terminal is coupled to the input signal terminal and the first inverter output terminal. The PMOS transistor source is coupled to a high voltage source, and the PMOS transistor gate is coupled to the inverting gate output. The NMOS transistor drain is coupled to the PMOS transistor drain, and the NMOS transistor gate is coupled to the inverse or Gate output, NMOS transistor source is coupled to a low voltage source, and the NMOS transistor drain is used as the output signal terminal. It belongs to the D-type flip-flop excited by the negative edge, and the clock input terminal of this D-type flip-flop. Is coupled to the enable signal terminal, the input terminal of the D-type flip-flop is coupled to a low voltage source, and When the setting end of the D-type flip-flop receives a low level, the output of the D-type flip-flop outputs a high level. The delay circuit is used to control the size of a specific time. The input of the delay circuit is coupled to the D-type flip-flop. The output terminal of the inverter and the output terminal of the delay circuit are coupled to the D-type flip-flop setting terminal. The first PMOS push-up transistor gate is coupled to the D-type flip-flop output terminal, and the first PMOS push-up transistor source is coupled. To the high voltage source, the first PMOS push-up transistor drain is coupled to the output signal terminal. The second reverse gate input terminal is coupled to the output signal terminal. The second PMOS push-up transistor gate is coupled to the second anti-gate output. Terminal, the source of the push-up transistor on the second PMOS is coupled to the high voltage source, and the source of the push-up transistor on the second PMOS is coupled to the output signal terminal. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier to understand In the following, the preferred embodiments are given in detail, and in conjunction with the drawings, the detailed description is as follows: Brief description of the drawings:
S (請先閱讀背面之注意事項再填寫本頁)S (Please read the notes on the back before filling this page)
-I n i 一DJ -^1 i n I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 3 216 ^ A7 5351twf. cLog/008 37 五、發明說明（9) 第1圖其所繪示爲習知三態輸出緩衝器之電路圖繪 示圖； (請先閱讀背面之注意事項再填寫本頁) 第2圖其所繪示爲以二個習知三態輸出緩衝器所 構成之匯流排結構之電路圖； 第3圖其所繪示爲本發明之可控制上推電阻之輸出 緩衝器電路第一實施例繪示圖； 第4圖其所繪示爲本發明之可控制上推電阻之輸出 緩衝器電路第二實施例繪示圖；以及 第5圖其所繪示爲本發明以二個輸出緩衝器所構成 之匯流排結構之電路圖。 標號說明： 20、320、420、520致能控制電路 22、72、122、322、422、522 反及閘 24、74、124 反間 26 ' 76 ' 126、326、426、526 反或閘 30、330、430、530反相緩衝器電路 32、82、132、332、432、532 PMOS 電晶體 34、84、134、334、434、534 NMOS 電晶體 經濟部智慧財產局員工消費合作社印製 40、90、140 PMOS上推電晶體 50三態輸出緩衝器 60·第二三態輸出緩衝器 150第一三態輸出緩衝器 200、300輸出緩衝器電路 210、310、410、510單穩態電路 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 .doc/008 五、發明說明（s ) 220、340、440、540 第一 PMOS 上推電晶體 230 ' 350、450、550 監視電路 232反閘 234、354、454、554 第二 PMOS 上推電晶體 240三態緩衝器 312 ' 412、512 D型正反器 314、414、514延遲電路 324、424、524 第一反閘 352、452、552 第二反閘 400第一輸出緩衝器電路 500第二輸出緩衝器電路 實施例 請參照第3圖，其所繪示爲本發明之可控制上推電 阻之輸出緩衝器電路第一實施例繪示圖。本發明之可控 制上推電阻之輸出緩衝器電路200包括三態緩衝器240、 單穩態電路210、第一 PMOS上推電晶體22〇與監視電 路 230。 此三態緩衝器240具有輸入訊號端' 輸出訊號端與 致能訊號端。而致能訊號端係用來控制此三態緩衝器240 是否動作。當致能訊號端爲未致能準位時’則此三態緩 衝器240之輸出訊號端呈現高阻抗狀態，當致能訊號端 爲致能準位，則此三態緩衝器240之輸入訊號端的訊號 會由輸出訊號端來輸出。 單穩態電路210輸入端耦接於致能訊號端，此單穩 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） T— I ϋ ϋy^I ·1 一OJ_ 1 tt I HI :V. {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 2 3 2 1 6 A7 5351twf,doc/008 gy 五、發明說明) 態電路210在致能準位轉換爲未致能準位的瞬間會被激 發，並且單穩態電路210會由輸出端輸出一段特定時間 的低準位，並在此特定時間過後輸出端會變更回高準 位，而高準位係爲單穩態電路210初始狀態的準位。 第一PMOS上推電晶體220閘極耦接至單穩態電 路210輸出端，由於第一 PMOS上推電晶體220源極耦 接至高電壓源，汲極耦接至輸出訊號端，所以使得第一 PMOS上推電晶體220在接收到特定時間的之低準位時 能夠開啓，並將輸出訊號端提升至高準位，而在特定時 間之後關閉此第一 PMOS上推電晶體220。 監視電路230包括反閘232與第二PMOS上推電 晶體234。反閘232輸入端（監視電路之輸入端）耦接 至輸出訊號端，反閘232輸出端耦接至第二PMOS上推 電晶體閘極，而第二PMOS上推電晶體234源極耦接至 高電壓源，汲極耦接至輸出訊號端，所以當輸出訊號端 爲高準位時，反閘232輸出低準位，第二PMOS上推電 晶體234開啓（相當於一上推電阻耦接於輸出訊號端與 高電壓源之間），將輸出訊號端提升至高準位。當輸出 訊號端爲低準位時，反閘232輸出高準位，第二PMOS 上推電晶體234關閉（相當於關閉此上推電阻），達到 切斷上推電阻的功效，亦即在輸出訊號端爲低準位時， 由於第二PMOS上推電晶體234關閉，並不會造成無謂 的直流電流流動以及電功率的損耗。而本發明之單穩態 電路210所提供低準位之特定時間之控制，必須要使得 丨 11_1 裝 -----訂-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 2 3 21 6 A7 5351twf.doc/008 37 五、發明說明（~ ) 監視電路230足以將輸出訊號端由高阻抗狀態提升至高 準位。 請參照第4圖，其所繪示爲本發明之可控制上推電 阻之輸出緩衝器電路第二實施例繪示圖。本發明之可控 制上推電阻之輸出緩衝器300包括致能控制電路320與 反相緩衝器電路330、單穩態電路310、第一 PMOS上 推電晶體340與監視電路350。 致能控制電路320包括反及閘322、第一反閘324 與反或閘326,輸入訊號端以及致能訊號端耦接至反及 閘322之輸入端，致能訊號端耦接至第一反閘324輸入 端，而第一反閘324輸出端與輸入訊號端耦接至反或閘 326之輸入端。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 反相緩衝器電路包括PMOS電晶體332與NMOS 電晶體334，PMOS電晶體332源極耦接至高電壓源， PMOS電晶體332閘極耦接至反及閘322之輸出端，PMOS 電晶體332汲極耦接至NMOS電晶體334汲極，NMOS 電晶體334閘極耦接至反或閘326之輸出端，NMOS電 晶體334源極耦接至低電壓源，而NMOS電晶體334汲 極亦作爲此三態輸出緩衝器300之輸出訊號端。 單穩態電路310包括D型正反器312與延遲電路 314，D型正反器312之時脈輸入端係爲負緣激發，其親 接於致能訊號端，D型正反器312之輸入端耦接至低電 壓源，D型正反器312之輸出端耦接至延遲電路314輸 入端，延遲電路314輸出端耦接至D型正反器312之設 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 23 216 A7 5351twf,doc/008 37 五、發明說明（（（） 定端，此設定端在低準位時會由D型正反器312輸出端 產生高準位，而設定端在高準位時並不會影響D型正反 器312輸出端的狀態。 第一 PMOS上推電晶體340源極耦接至高電壓源， 汲極耦接至輸出訊號端，閘極耦接至D型正反器的輸出 端。 監視電路350包括第二反閘352與第二PMOS上 推電晶體354。第二反閘352輸入端（監視電路之輸入 端）耦接至輸出訊號端，第二反閘352輸出端耦接至第 二PMOS上推電晶體354閘極，而第二PMOS上推電晶 體354源極耦接至高電壓源，第二PMOS上推電晶體354 汲極耦接至輸出訊號端。 首先介紹監視電路350，監視電路350在輸出訊號 端爲高準位時，第二反閘352輸出低準位，所以第二 PMOS上推電晶體354開啓（相當於一個上推電阻耦接 於輸出訊號端與高電壓源之間），將輸出訊號端提升至 高準位。當輸出訊號端爲低準位時，第二反閘352輸出 高準位，第二PMOS上推電晶體354關閉（亦即關閉此 上推電阻），達到切斷上推電阻的功效，亦即在輸出訊 號端爲低準位時，由於第二PMOS上推電晶體354關閉， 並不會造成無謂的直流電流流動以及電功率的損耗。 接著介紹此輸出緩衝器300的運作，當輸出緩衝器 300的致能訊號爲高準位，代表輸出緩衝器300開始動 作，此時單穩態電路310輸出高準位，第一 PMOS上推 ----—------裝 --------訂'----i- (請先閱讀背面之注意事項再填寫本頁〕 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 423216 A7 5351twf.d〇c/〇〇8 B7 五、發明說明（/〜） 電晶體340關閉，同時當致能訊號爲高準位時，假設此 時輸入訊號端爲高準位’致能控制電路320內之反及閘 322之輸出端爲低準位，同時，反或閘326之輸出端爲 低準位，所以反相緩衝器電路330內之PM0S電晶體332 開啓而NMOS電晶體334關閉，輸出訊號端即爲高準位。 假設此時輸入訊號端爲低準位’致能控制電路320內之 反及閘322之輸出端爲高準位’同時’反或閘326之輸 出端爲高準位’所以反相緩衝器電路330內之PMOS電 晶體332關閉而NMOS電晶體334開啓，輸出訊號端即 爲低準位。 而當此輸出緩衝器300的致能訊號爲低準位，代表 輸出緩衝器停止動作，在致能訊號由高準位轉變爲低準 位時，由於單穩態電路310的D型正反器312之時脈輸 入端係爲負緣激發，所以D型正反器312動作，其會將 D型正反器312輸入端的低準位送至輸出端，而當輸出 端輸出低準位後，延遲電路314會延遲一個特定時間將 此低準位訊號送至設定端，所以此時D型正反器312輸 出端會被設定爲高準位，亦即，此D型正反器312在動 作之後會有一段特定時間在輸出端爲低準位，而其餘的 狀態都是處於高準位。 當D型正反器312輸出低準位時，第一 pMOS上 推電晶體340開啓，將輸出訊號端提升至高準位。在特 定時間之後當D型正反器312輸出變爲高準位時，由於 監視電路350已經將輸出訊號端提升至高準位，所以第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ 111111--I I -11--111 訂--- - ---— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I 2 3 216 A7 5351twf.doc/008 gy 五、發明說明) 一 PMOS上推電晶體340的關閉並不會影響輸出訊號端 的準位。所以本發明之單穩態電路310所提供低準位之 特定時間控制，必須要使得監視電路350足以將輸出訊 號端提升至高準位。 請參照第5圖，其所繪示爲本發明以二個輸出緩衝 器所構成之匯流排（bus)結構之電路圖。 首先，在第二輸出緩衝器500動作的情況下，第一 致能訊號輸入低準位，而在第一致能訊號狀態轉換時會 使得第一輸出緩衝器400內之單穩態電路410開啓第一 PM0S上推電晶體440，將輸出訊號端提升至高準位， 並在特定時間後由監視電路’450內之第二PMOS上推電 晶體454來維持輸出訊號端之高準位。 而此時第二致能訊號輸入高準位，假設此時第二輸 入訊號端爲高準位，會使得第二輸出緩衝器500內之 PMOS電晶體532動作，所以輸出訊號端依舊維持高準 位。假設此時第二輸入訊號端爲低準位，會使得第二輸 出緩衝器500內之NMOS電晶體534動作而將輸出訊號 端拉至低準位，由於輸出訊號端電壓下降，使得第一與 第二輸出緩衝器內之監視電路關閉其第二PMOS上推電 晶體454與554,所以輸出訊號端爲理想的低電位，不 會有習知不理想的低電位產生，並可解決無謂之電流路 徑會產生直流電流以及電功率的損耗。 最後，假設此二個輸出緩衝器400、500不動作， 則第一與第二致能訊號輸入由高準位轉至低準位時，會 ,----- -------Λί/^ I -1----11 訂—------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 2 321 6 A7 B7 5351twf,doc/008 五、發明說明（K ) (請先閱讀背面之注意事項再填寫本頁) 使得第一或者第二輸出緩衝器400.、500內之單穩態電 路410 ' 510開啓其第一PMOS上推電晶體440、540， 而將輸出訊號端提升至高準位，並在特定時間後由監視 電路450、550內之第二PMOS上推電晶體454、554來 維持輸出訊號端之高準位。 因此，本發明的優點係提出一種可控制上推電阻之 輸出緩衝器，利用一個單穩態電路以及PMOS電晶體， 在三態輸出緩衝器未被致能時，將輸出訊號端電壓上推 至高準位。 本發明的另一優點係提出一種可控制上推電阻之輸 出緩衝器，利用一個監視電路，使輸出訊號端在高準位 時提供一個上推電阻使輸出訊號端維持在高準位，並在 輸出端電壓變爲低準位時將監視電路內之上推電阻關 閉，避免無謂的直流電流流動以及電功率的損耗。 經濟部智慧財產局員工消費合作社印製 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫 離本發明之精神和範圍內，當可作各種之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定 者爲準。 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐）-I ni 一 DJ-^ 1 in I Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4 3 216 ^ A7 5351twf. CLog / 008 37 V. Description of the invention (9) Figure 1 shows the circuit diagram of the conventional three-state output buffer; (Please read the precautions on the back before filling this page) Figure 2 shows the diagram A circuit diagram of a bus structure composed of two conventional tri-state output buffers; FIG. 3 is a diagram illustrating a first embodiment of an output buffer circuit capable of controlling a push-up resistor according to the present invention; FIG. 4 It is a drawing showing a second embodiment of an output buffer circuit capable of controlling a push-up resistor according to the present invention; and FIG. 5 is a view showing a bus structure composed of two output buffers according to the present invention. Circuit diagram. Explanation of symbols: 20, 320, 420, 520 enable control circuits 22, 72, 122, 322, 422, 522 and 24, 74, 124 and 26 '76' 126, 326, 426, 526 and 30 , 330, 430, 530 Inverting Buffer Circuits 32, 82, 132, 332, 432, 532 PMOS Transistors 34, 84, 134, 334, 434, 534 NMOS Transistors Printed by Intellectual Property Bureau Staff Consumer Cooperatives 40 , 90, 140 PMOS push-up transistor 50 tri-state output buffer 60 · second tri-state output buffer 150 first tri-state output buffer 200, 300 output buffer circuit 210, 310, 410, 510 monostable circuit 9 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 .doc / 008 V. Description of invention (s) 220, 340, 440, 540 First PMOS push-up transistor 230 '350 , 450, 550 Monitoring circuit 232 Back gate 234, 354, 454, 554 Second PMOS push-up transistor 240 Three-state buffer 312 '412, 512 D-type flip-flop 314, 414, 514 Delay circuit 324, 424, 524 The first reverse gate 352, 452, 552, the second reverse gate 400, the first output buffer circuit 500, and the second output buffer circuit. Example Please refer to FIG. 3, which illustrates a first embodiment of an output buffer circuit capable of controlling a push-up resistor according to the present invention. The output buffer circuit 200 with controllable push-up resistor of the present invention includes a tri-state buffer 240, a monostable circuit 210, a first PMOS push-up transistor 22, and a monitoring circuit 230. The tri-state buffer 240 has an input signal terminal, an output signal terminal and an enable signal terminal. The enable signal terminal is used to control whether the tri-state buffer 240 operates. When the enable signal terminal is not enabled, the output signal terminal of the tri-state buffer 240 is in a high impedance state. When the enable signal terminal is enabled, the input signal of the tri-state buffer 240 is high. The signal of the terminal will be output by the output signal terminal. The input terminal of the monostable circuit 210 is coupled to the enable signal terminal. The paper size of this monostable circuit applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). T— I ϋ ϋy ^ I · 1-OJ_ 1 tt I HI: V. {Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 3 2 1 6 A7 5351twf, doc / 008 gy V. Description of the invention) The state circuit 210 will be excited at the moment when the enabled level is converted to the unenabled level, and the monostable circuit 210 will output a low level for a certain period of time from the output terminal, and here it is specified After the time has elapsed, the output terminal will change back to the high level, and the high level is the level of the initial state of the monostable circuit 210. The gate of the first PMOS push-up transistor 220 is coupled to the output of the monostable circuit 210. Because the source of the first PMOS push-up transistor 220 is coupled to the high-voltage source and the drain is coupled to the output signal terminal, the first A PMOS push-up transistor 220 can be turned on when a low level is received at a specific time, and the output signal terminal is raised to a high level, and the first PMOS push-up transistor 220 is turned off after a specific time. The monitoring circuit 230 includes an anti-gate 232 and a second PMOS push-up transistor 234. The input of the anti-gate 232 (input of the monitoring circuit) is coupled to the output signal terminal. The output of the anti-gate 232 is coupled to the gate of the second PMOS push-up transistor, and the source of the second PMOS push-up transistor 234 is coupled. To the high voltage source, the drain is coupled to the output signal terminal, so when the output signal terminal is at the high level, the back gate 232 outputs the low level, and the second PMOS push-up transistor 234 is turned on (equivalent to a push-up resistor coupling) Between the output signal terminal and the high voltage source), raise the output signal terminal to a high level. When the output signal terminal is at a low level, the back gate 232 outputs a high level, and the second PMOS push-up transistor 234 is turned off (equivalent to turning off this push-up resistor), which achieves the effect of cutting off the push-up resistor, that is, at the output When the signal terminal is at a low level, since the second PMOS push-up transistor 234 is turned off, it will not cause unnecessary DC current flow and electrical power loss. And the control of the specific time provided by the monostable circuit 210 of the present invention at a low level must be made 11-11 -------- Order -------- (Please read the precautions on the back before filling (This page) This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) 4 2 3 21 6 A7 5351twf.doc / 008 37 V. Description of the invention (~) The monitoring circuit 230 is sufficient to divert the output signal end from The high impedance state is raised to a high level. Please refer to FIG. 4, which is a diagram illustrating a second embodiment of an output buffer circuit capable of controlling the push-up resistor according to the present invention. The output buffer 300 with controllable push-up resistor of the present invention includes an enable control circuit 320 and an inverting buffer circuit 330, a monostable circuit 310, a first PMOS push-up transistor 340, and a monitoring circuit 350. The enabling control circuit 320 includes a reverse AND gate 322, a first reverse gate 324 and a reverse OR gate 326, an input signal terminal and an enable signal terminal are coupled to the input terminal of the reverse AND gate 322, and the enable signal terminal is coupled to the first The input terminal of the anti-gate 324, and the output terminal of the first anti-gate 324 and the input signal terminal are coupled to the input terminal of the anti-or gate 326. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Inverting buffer circuit includes PMOS transistor 332 and NMOS transistor 334. The source of PMOS transistor 332 is coupled to a high voltage source The gate of the PMOS transistor 332 is coupled to the output terminal of the inverse gate 322, the drain of the PMOS transistor 332 is coupled to the drain of the NMOS transistor 334, and the gate of the NMOS transistor 334 is coupled to the output of the OR gate 326 The source of the NMOS transistor 334 is coupled to a low voltage source, and the drain of the NMOS transistor 334 also serves as the output signal terminal of the tri-state output buffer 300. The monostable circuit 310 includes a D-type flip-flop 312 and a delay circuit 314. The clock input terminal of the D-type flip-flop 312 is a negative edge excitation, which is connected to the enable signal terminal. The input terminal is coupled to a low voltage source, the output terminal of the D-type flip-flop 312 is coupled to the input of the delay circuit 314, and the output terminal of the delay circuit 314 is coupled to the D-type flip-flop 312. The paper size is applicable to Chinese national standards (CNS) A4 specification (210 x 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 23 216 A7 5351twf, doc / 008 37 V. Description of the invention ((() Fixed end, this set end is at a low level A high level is generated by the output terminal of the D-type flip-flop 312 at the time, and the state of the output terminal of the D-type flip-flop 312 is not affected when the setting terminal is at the high level. The source of the 340 push-up transistor on the first PMOS is coupled To the high voltage source, the drain is coupled to the output signal terminal, and the gate is coupled to the output terminal of the D-type flip-flop. The monitoring circuit 350 includes a second anti-gate 352 and a second PMOS push-up transistor 354. The second anti-gate The 352 input terminal (input terminal of the monitoring circuit) is coupled to the output signal terminal, and the second reverse gate 352 output terminal is coupled To the second PMOS push the transistor 354 gate, and the second PMOS push transistor 354 source is coupled to the high voltage source, and the second PMOS push transistor 354 drain is coupled to the output signal terminal. First introduce the monitoring circuit 350. When the output signal of the monitoring circuit 350 is at a high level, the second reverse gate 352 outputs a low level, so the second PMOS push-up transistor 354 is turned on (equivalent to a push-up resistor coupled to the output signal terminal and high Between the voltage sources), the output signal terminal is raised to a high level. When the output signal terminal is a low level, the second reverse gate 352 outputs a high level, and the second PMOS push-up transistor 354 is turned off (that is, it is turned off here). Push resistor), to achieve the effect of cutting off the push-up resistor, that is, when the output signal terminal is at a low level, because the second PMOS push-up transistor 354 is turned off, it will not cause unnecessary DC current flow and electrical power loss. Next, the operation of the output buffer 300 is described. When the enable signal of the output buffer 300 is a high level, it means that the output buffer 300 starts to operate. At this time, the monostable circuit 310 outputs a high level, and the first PMOS pushes up- ----------- install -------- Order '---- i- (Please read the precautions on the back before filling this page] This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 423216 A7 5351twf.d〇c / 〇〇8 B7 V. Description of the Invention (/ ~) Transistor 340 is turned off, and when the enable signal is at a high level, it is assumed that the input signal terminal is at a high level at this time. The output of the inverting gate 322 in the circuit 320 is at a low level, and at the same time, the output of the inverting gate 326 is at a low level, so the PM0S transistor 332 in the inverting buffer circuit 330 is turned on and the NMOS transistor 334 is turned off. , The output signal end is the high level. Assume that the input signal terminal is at a low level at this time, 'enable the control circuit 320 and the output of the gate 322 is at a high level. At the same time,' the output of the inverter OR gate 326 is at a high level ', so the inverting buffer circuit The PMOS transistor 332 in 330 is turned off and the NMOS transistor 334 is turned on. The output signal terminal is at a low level. When the enable signal of the output buffer 300 is at a low level, it means that the output buffer stops operating. When the enable signal changes from a high level to a low level, due to the D-type flip-flop of the monostable circuit 310 The clock input terminal of 312 is excited by a negative edge, so the D-type flip-flop 312 operates, which sends the low level of the input of the D-type flip-flop 312 to the output terminal, and when the output terminal outputs the low level, The delay circuit 314 delays this low-level signal to the setting end by a specific time, so the output of the D-type flip-flop 312 will be set to a high-level at this time, that is, the D-type flip-flop 312 is operating After a certain period of time, the output is at the low level, and the rest of the states are at the high level. When the D-type flip-flop 312 outputs a low level, the first pMOS push-up transistor 340 is turned on, and the output signal terminal is raised to a high level. When the output of the D-type flip-flop 312 changes to a high level after a certain time, since the output signal terminal has been raised to a high level by the monitoring circuit 350, the first paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Γ 111111--II -11--111 Order --------- (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs I 2 3 216 A7 5351twf.doc / 008 gy V. Description of the invention) The shutdown of the PMOS push-up transistor 340 will not affect the level of the output signal end. Therefore, the specific time control provided by the monostable circuit 310 of the present invention at a low level must make the monitoring circuit 350 sufficient to raise the output signal terminal to a high level. Please refer to Fig. 5, which shows a circuit diagram of a bus structure composed of two output buffers according to the present invention. First, when the second output buffer 500 operates, the first enable signal is input to a low level, and when the state of the first enable signal is switched, the monostable circuit 410 in the first output buffer 400 is turned on. The first PMOS pushes the transistor 440 up to raise the output signal terminal to a high level, and after a certain time, the second PMOS within the monitoring circuit '450 pushes the transistor 454 to maintain the high level of the output signal terminal. At this time, the second enable signal is input to the high level. Assuming that the second input signal terminal is at the high level at this time, the PMOS transistor 532 in the second output buffer 500 will operate, so the output signal terminal will still maintain the high level. Bit. It is assumed that the second input signal terminal is at a low level at this time, which will cause the NMOS transistor 534 in the second output buffer 500 to operate and pull the output signal terminal to a low level. Because the voltage of the output signal terminal drops, the first and The monitoring circuit in the second output buffer turns off its second PMOS push-up transistors 454 and 554, so the output signal terminal is an ideal low potential, and there is no conventionally undesirable low potential generated, and it can solve the unnecessary current The path generates DC current and loss of electrical power. Finally, assuming that the two output buffers 400 and 500 are inactive, the first and second enable signal inputs will change from a high level to a low level. Λί / ^ I -1 ---- 11 Order -------- (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) 4) 321 6 A7 B7 5351twf, doc / 008 V. Description of the invention (K) (Please read the notes on the back before filling this page) Make the first or second output buffers 400., 500 monostable State circuit 410'510 turns on its first PMOS push-up transistors 440, 540, and raises the output signal terminal to a high level, and after a certain time, the second PMOS push-up transistor 454, 554 to maintain the high level of the output signal. Therefore, the advantage of the present invention is to provide an output buffer capable of controlling the push-up resistor. By using a monostable circuit and a PMOS transistor, when the tri-state output buffer is not enabled, the output signal terminal voltage is pushed up to a high level. Level. Another advantage of the present invention is to provide an output buffer capable of controlling the push-up resistor. Using a monitoring circuit, the output signal terminal provides a push-up resistor when the output signal terminal is at a high level, and the output signal terminal is maintained at a high level. When the output voltage becomes low, the push-up resistor in the monitoring circuit is turned off to avoid unnecessary DC current flow and loss of electrical power. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the spirit and Within the scope, various modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the appended patent application. This paper size applies the national standard (CNS) A4 specification (210 X 297 mm)