TW423079B - A process for manufacturing ic-components to be used at radio frequencies - Google Patents

Abstract

A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas (18). The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer (34). A base region in the active region is defined by a well-defined opening, that is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors. A region of the silicon nitride layer (34) is at the same time used as an efficient dielectric in a simultaneously manufactured capacitor. The NPN-transistor can be provided with a thin side string made of nitride for isolation between an emitter connection and a base connection. In the same semiconductor plate special, deep and shallow substrate connecting terminals can be provided for electrically isolating component areas. Trenches (22) can be used for electrical isolation of component areas and they can at their sidewalls have a laminate of at the bottom oxide (23) and thereon nitride (25) in order to facilitate planarizing etching and in order to act as a diffusion barrier.

Description

r 4 2 3 Ο 7 9 A7 B7 V. Description of the invention (Printed invention collar printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs) The present invention relates to the manufacture of signals suitable for the radio frequency range, and uses silicon-based bipolarity. IC components manufactured by technology are particularly suitable for simultaneously manufacturing vertical NpN transistors, capacitors, and lateral PNP transistors on a silicon substrate, and are suitable for creating deep substrate contacts. BACKGROUND OF THE INVENTION Until now, bipolarity was used Transistors (Bip-transistors) are possible to produce fast bipolar circuits with high packaging density. A is manufactured in such a way that they have two layers of g-acetamide, so they are commonly known as dual polycrystalline silicon transistors. The quasi-or self-alignment technology combined with the electrical insulation provided by the trenches surrounding the transistor (so-called trench insulation). The profile of the conventional trench-insulated bipolar transistor of this type, a dual polysilicon type, The schematic diagram is shown in Figure 丨, which is manufactured using self-alignment technology. In a known process for manufacturing a bi-polycrystalline silicon bipolar transistor, the first polymer The acetamide layer forms a basic connection. If the electrical body is of the NPN type, the polycrystalline silicon layer is strongly doped to the p type. The finally deposited polyacetamide layer (which is strongly doped to the N type and constitutes a Emitter electrode) is physically separated from the first deposited polyethylene layer constituting the base by an electrically insulating layer and insulating side strips, which are also referred to as "spacers." It is used in the manufacture of bipolar transistors. The advantage of the self-aligning method is that the base impedance and the capacitance between the base and the collector can be reduced. In addition, the insulation provided by the trench can be used. The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (2 丨0 × 297mm) _ (Please read the notes on the back before filling in this page) Ding *-· ° Γ4 2 3 〇 7 9 V. Description of the invention (2) The capacitance between the collector and the base is reduced. Therefore The performance of the circuit can be greatly improved. A conventionally known method for manufacturing an NPN-type trench-insulated bipolar transistor will be described in detail later with reference to FIGS. 2 to 6. As a basic material, a p-type single crystal The surface of the silicon substrate 101 is set on a silicon crystal structure On one (100) plane, see Figure 2 ^ bottom diffusion 102 (also known as a 'barrier layer,' which can consist of an ion implanted layer such as arsenic or antimony) defined by lithography Then, a fragment of worm crystal 10 with a thickness of about 2 m is applied on the plane 101. Then, lithography and ion implantation are used to define N-and plane 101. P_area. N_area 104 is made by phosphorus ion implantation, and it is placed directly above the N + -type bottom diffusion layer 102. Another area 105 is located in ~ area ι〇4 In between, it is P-doped and is manufactured by, for example, boron ion implantation, as shown in Figure 2. Then the traditional LOCOS method ("LOCal fragmentation oxidation,") is used to define the active region. See J.A_ Appel et al. At Philips Research

Report, Vol. 25, 1970, pages 118-132, printed by the Consumer Electronics Co., Ltd. of the Central Economic and Technical Bureau of the Ministry of Regional Economics (please read the precautions on the back before filling this page) "Application in semiconductor technology" ◊ Then first apply an insulating cover 1 0 6 'of appropriate material, see Figure 3, and then make a photolithographic layout. Next, silicon 1 is thermally grown in the pores of the cover 1 06. 7 'Make the base region 1 and collector region 1 of the transistor be retained' and form in the area covered by the mask. After the active region is defined in this way (with the oxide layer region) 09 , Separate), this paper size applies Chinese National Standard (CNS) A4 specification (210X297 public director) 1423079 V. Description of the invention (3) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs and then defining the insulation trench by lithography丨 〖〇, and then use isotopic dry contact etching to etch the silicon oxide material 1 〇07 and the matrix material 1 〇 丨 until the trench 11 〇 to achieve the required depth (about 5 to 丨 vm) 'and extend downward Into non-effective p-matrix The walls of the trench 110 are thermally oxidized so that a thin, electrically insulating layer is obtained, and the trench is then filled with an insulating or semi-insulating material, such as silicon oxide or polycrystalline silicon, or It is called polycrystalline silicon or polyvinylamine. The filling material is then etched by dry etching until a flat surface is obtained. This flat surface is then oxidized, especially if the trench is filled with polyethylene. The silicon material in the opening of the trench is oxidized to obtain an insulating layer on the surface of the opening. If the trench is only filled with oxygen at the beginning, no additional oxidation step is required. The result is shown in Figure 3. It can be found that in FIG. 3, the extension of the base region 108 is defined by using the LOCOS method as described above. The disadvantages of this method will be discussed below when a modified process of manufacturing a transistor is discussed. Β Β forms a trench. After slot 10, a collector socket η 2 is defined by lithography, as shown in FIG. 4, that is, a low-impedance boundary is defined between the planar surface of the element in the collector region and the bottom diffusion surface. Connect after The implantation method is doped with a dopant (usually phosphorus) into the opening defined by the lithographic etch. The following process description will be based on the above-mentioned dual polycrystalline silicon type with a self-aligned base-emitter junction. NPN transistor description 'Because this type of component is usually combined with the electrical insulation obtained by the groove. This paper standard applies the Zhongguan standard (CNS) Congxie (21Q > < 297 public envy) (Please read the back of the first Matters needing attention to fill out this page again} Order 14 23 0 Α7 Β7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives V. Description of the invention (4) After the aforementioned active zones 108 and 109 were defined and the collector socket 112 was formed A thin polyethyleneamine layer 113 is deposited with a thickness of several hundred, as shown in FIG. 4. Then, the polyethylenimine 113 is doped with P + by ion implantation of boron, and a thin oxide layer 114 is deposited on the polyethylenimide layer by CVD ("chemical vapor deposition"). After this process, the boron-doped P + -type polyethyleneamine layer will form a commonly known intrinsic pedestal or a basic connection or terminal. The oxide layer 1 14 generated by CVD and the polyethylenamine layer 1 1 3 located below it are patterned in a lithographic manner to define an emitter opening located in the base region 108. 1 5. The parts of the two layers that are not covered by the lithographic etching mask are then removed by a dry etching step such as plasma etching. After the layout of the emitter opening 115 is completed, a thin thermal oxide layer 6 is grown to protect the surface inside the emitter opening, and then an ion-implanted boron is used to form a commonly known essence base 11 7. Therefore, the base of this essence is placed precisely within and below the emitter opening 1 1 5. In order to separate the emitter to be generated from the essence of the matrix, open along the side of the emitter opening 115; # 成 "spacers" or side bars 1 1 8 as shown in Figure 5. It is formed in such a manner that an oxide layer is first deposited on the plane by Cvd, and then an anisotropic dry etching step is used to engrav the surname on the flat surface portion of the plane, which can be accompanied by the layout The step of generating the emitter opening u 5 forms a side strip or spacer n8 of the CVD oxide. After forming the spacer i 18, a thin polyacetamide layer 119 having a thickness of about several hundred nm is formed at ---------------- 1T ---- -. Caution (please read the precautions on the back before filling out this page) -7-

r 4 2 3 ο 7 9 V. Description of the invention (5) A7 B7 Printed on the flat surface by the Pager Consumers Cooperative of the Central Bureau of Quasi-Ministry of Economic Affairs. This layer is implanted with arsenic to become N + type, and an emitter electrode 120 of a transistor will be formed after annealing treatment. After the layer 1 1 9 is laid out and etched to produce an emitter electrode, its structure is as shown in FIG. 5. Usually we will keep the upper polyethylene layer 119 (forming the emitter electrode) on the upper part of the emitter region 10, as shown in Figure 3 'and the upper part of the collector socket 112, where the collector The socket 112 serves as a collector terminal 121. Then the circuit is passivated by a layer such as silicon oxide. As shown in FIG. 6, the contact holes 123, 124, and 125 of the base, emitter, and collector of the transistor are all determined by lithography. After the contact hole is etched, the circuit is sputtered with a metal layer 26, such as aluminum, which will penetrate the contact holes 123, 124 '125' and will form an electrical contact with the outside world. The lithographic etching method and etching are then used to define the conductive layer 丨 26 to generate external contacts 丨 2 ?, U8, 129. The final structure is shown in Figure 6 'and compared with Figure 丨. Figure 1 shows a better picture of the final component, even if the thickness of the layer has been increased in some cases. As mentioned above, the base region 108 is defined by the Loccos * method, as shown in FIG. 3. Then it is best to use a two-layer structure. This structure is composed of a silicon dioxide directly above the single crystal silicon and can be used as a regional oxide mask when thermally growing a so-called field oxide 107. Composition of silicon nitride. When the field is oxidized, the lateral diffusion of this oxygen will be generated along the ^ boundary layer between single crystal silicon and silicon dioxide, and then some oxygen growth will also occur in the nitride (paper scale development (Called Α4 · < 2 敝 297mm (please read the precautions on the back before filling this page)

, 1T

In · I— I: Γ--I.-· I., —I- n 1423079 ^ V. Description of the invention (6) On the edge of the printed layer of the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, see Figure 3130. This oxide 13 is widely known as the "black mouth". Therefore, the extension of the base region can only reach the extent defined by the nitriding and oxidation-mask structure defined by the lithographic name. It can be said that the region is correct It is defined by the "Uzui," which is left after the manufacturing is completed. In order to compensate for the lack of correctness and process variations due to the generation of these, the base region does not need to be very large. Therefore, an unnecessary large capacitance can be obtained between the base and the collector. In addition, ' When a field oxide 1 07 is generated in the N-region 1 0 4, a doping concentration 13 1 (commonly known as 'dopant pUe up') occurs at the field oxide 1. 7 and the boundary of the surface of the single crystal silicon substrate ι〇1 'are shown in Figure 3. When the P + type polyacetamide 丨 13 (which forms the essential base) and the base region outside the side strip 1 18 When contacting 108, it will increase the valley between the base and the collector in the completed NPN transistor, as shown in Figures 3 and 4. SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and therefore Can provide semiconductor elements, especially in bipolar transistors, which have relatively high performance, especially a bipolar NPN transistor with reduced capacitance between its base and collector, and a bipolar PNP transistor A reduction in the capacitance of a cake between its emitter and collector p Another object of the present invention is to provide the above problem Solution 'One of the substrate capacitors (that is, a passive capacitor element on the surface of the substrate) is formed at the same time when the capacitance between the substrate and the collector of the NPN transistor is reduced. This paper size · (Please read first Note the items on the back, please fill out this page again) -ί ,. Order 14 2-(: 7 '' at 14 2-(: 7 ``) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description (7) Another object of the present invention is to provide hollow and deep substrate contacts for electrically insulating the element area on a substrate surface. Another object of the present invention is to provide a transistor, generally referred to as a bipolar device. It is isolated by a trench or a plurality of trenches, wherein the trenches can be produced in an efficient manner. To generate an NPN transistor, a superimposed layer of silicon dioxide and silicon nitride is introduced. The upper end of the active area (collector area) of this Npn transistor. This stack is patterned by lithographic etching so that the base area of the transistor can be defined by the openings in the stacked layer. At the same time, the Apertures defined using micro-etching A lateral PNP transistor to generate the emitter and collector of the transistor. It is also possible to form a matrix capacitor using a silicon nitride layer as a dielectric layer without using any additional masking steps. The capacitance value between the base and the emitter of the bipolar NPN transistor can be reduced. A semiconductor device (which can be an NPN type bipolar transistor) has an active area on the surface of the device. The known method consists of a thick field oxide region. If you can see along the surface of the element, this active area is partially covered by an electrically insulating surface layer, and most of which includes a nitride layer. In this active area The base region is defined by a defined opening in a photolithographic etch in the electrically insulating surface layer. Right the semiconductor device at this time is a pNp-type bipolar transistor era, is the emitter collector region in the component table __- 10- The paper degree is appropriate Public Manager-— (Please read the notes on the back before filling this page)

-1T A7 B7 V. Description of the invention (8 The printed surface of the Central Government Bureau of Standards and Technology Cooperatives of the Ministry of Economic Affairs is surrounded by the thick field oxide region, as seen along the element surface. The emitter region and / or a collector The area can also be determined by a corresponding ^ formula defined by the opening defined by the lithographic etching in an electrically insulating surface layer. Using the lithographic etching defined in these two examples, the electrically insulating surface f will extend beyond and to the surrounding field oxidation A strip of electrically insulating surface layer exists between the base region and the emitter or collector and between each of the emulsion regions closest to this I region under the object region. The electrically insulating surface layer advantageously includes a The upper silicon nitride layer and the lower silicon dioxide layer are stacked. The silicon nitride layer is preferably used as an effective dielectric in a capacitor that is generated at the same time. The trench can be used as an insulating element and can be passed in a conventional manner. It is etched. Next, a stack is added to the wall of the trench. This layer includes a thermally grown silicon dioxide layer at the bottom and a thin silicon nitride layer formed thereon by deposition. Finally, the trench The remaining major part will An electrically insulating or semi-insulating layer, such as a silicon dioxide layer or an undoped silicon layer (such as a single crystal silicon), is filled with β on a flat surface (eg, in a proper deposition method) and then the The silicon nitride layer is used as an etch stop layer in the subsequent planarization etching to flatten the layer and the main part of the trench is filled. In addition, if the material used when filling the trench has impurities, The nitrogen-silicon layer will prevent them from diffusing into the matrix material. 'Such diffusion will also reduce the electrical insulation function of the trenches. _ Brief description of the drawings -11 M-scale scales are applicable to Chinese National Standard (CNS) A4 specifications (210 × 297 Gongchu) (谇 Please read the precautions on the back before filling this page) Order; 423079 A7 B7 Consumption Cooperation by Staff of the Central Bureau of the Ministry of Economic Affairs · Du printed 5. Description of Invention (9) Will now be implemented in the following non-limiting manner The invention is described with reference to examples and drawings, in which: stomach 'FIG. 1 is a cross-sectional view of a bi-polycrystalline silicon transistor having bipolar self-alignment due to the electrical insulating force provided by the trench; FIG. 2 is a view In forming a bottom diffusion layer and After the epitaxial surface layer is a cross-sectional view of the starting material family of the transistor shown in FIG. 丨; FIG. 3 is a cross-sectional view similar to FIG. 2 but after the active area is defined and the trench is insulated; Figure 4 is a cross-sectional view similar to Figure 2 but with the emitter opening and the essential base defined; Figure 5 is similar to Figure 2 with the spacer and the emitter and collector defined 6 is a cross-sectional view similar to FIG. 2 but after the first metal layer is defined; FIG. 7 is a cross-sectional view of a broken layer and a layer disposed thereon, which are mainly used for Generate a NPN transistor with good high frequency characteristics, but also to generate a capacitor and a lateral PNP transistor, the cross-sectional view shows the plane before the bottom diffusion is formed; Figure 8 shows a cross section similar to Figure 7 FIG. 9 shows a state of the plane after the bottom diffusion is formed; FIG. 9 shows a cross-sectional view similar to FIG. 8, but shows a cross-sectional view after the bottom diffusion is formed; and FIG. 0 shows a cross-section similar to FIG. 9. Figure, which shows the -12-This paper scale uses China Home Standard (CNS) A4 Specification (210X297mm) ssi · --------- Γ · _ * ri fur ^ ^^^^ 1 —fltp T1 «(Please read the precautions on the back before filling (This page) r Λ 2 3 0 a? _____ Β7 V. Description of the invention (10) An additional P-doped planar state: Figure 11 shows a cross-sectional view similar to Figure 10, showing deposition on a planar surface A cross-sectional view after epitaxial silicon is shown; FIG. 12 is a cross-sectional view similar to FIG. Η, which shows a planar state when an N-region is selectively formed; FIG. 13 is a cross-sectional view similar to FIG. It shows a cross-sectional view after selective oxidation of the N-region and formation of a self-aligned p_ region; FIG. 14 shows a cross-sectional view similar to FIG. 13, which shows a cross-sectional view after the element area is defined. The different element regions are indicated; 'Figures 15a and 15b show cross-sections similar to Figure 14 but after the field region has been oxidized', which respectively show a region of an NPN transistor and a capacitor and the In a region of a lateral PNP transistor; FIG. 16 is a cross-sectional view similar to FIG. 15 but with a trench defined; FIG. 1 7 is a cross-sectional view similar to FIG. 16 but with a hard cover and barrier layer removed and the inner wall of the trench oxidized; printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Jing first read the note on the back) Please fill in this page again) Figure 18 shows a cross-sectional view similar to Figure 17, which shows a cross-sectional view after filling the trench with a layer of polyethylene; Figure 19 shows a cross-section similar to Figure 18 Figure 20 shows a cross-sectional view after oxidizing the polyethylene in the opening of the trench; Figures 20a and 20b are cross-sectional views similar to Figure 19, showing when used for NPN transistors and a Capacitor area and use -13-This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 2 3 0 7 9 A7 B7 V. Description of the invention (u on the area of a PNP transistor) The flat state when the collector is formed; Figures 2a and 2lb are similar to Figures 20a and 20b, showing cross-sectional views after depositing a silicon-silicon layer and defining an emitter region; Shown as a cross-sectional view similar to FIG. 21, showing a cross-sectional view after delimiting a base region and sedimentary scales 23a and 3b are cross-sectional views similar to FIG. 22, which respectively show cross-sectional views after defining an emitter-base region, an upper capacitor plate, and a puppet, and are used for an NPN transistor and a capacitor. And the area for a lateral PN transistor:

FIG. 24 is a cross-sectional view similar to FIG. 23a, which shows the state of the plane when a matrix is implanted; W FIG. 25a is a cross-sectional view similar to FIG. Figure 25b shows a part of the cross-sectional view of FIG. 24 in forming a changed design; FIG. 25c shows a part according to FIG. 25a The image of the emitter structure was taken with a ~ ^ microscope; the printed electron micrograph of the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed in Figure 25d is an image taken according to the emitter structure mirror of Figure 25b; Polyacetamide layer (please read the notes on the back before filling out this page:> Figure 26a shows the state of the plane when the cross-sectional view similar to that of Figure 25a forms an emitter, which shows before and after etching The graphics and display are used for ~ and crystal-14- This paper size is applicable to Chinese National Standard (CNS) A4 specification (21 × 297 mm) M Printed by the Ministry of Economic Affairs Central Standards Bureau Consumer Consumption Cooperative · 4 230 7 9 a ? ------ B7 V. Description of the invention (12) and Yidian Figure 2 6 bb shows a cross-sectional view of a part of the structure, a part of which appears in Figure 26a 'It also shows the production of low and high resistance resistors; Figure 2 6 c shows a similar Fig. 26a is a cross-sectional view showing a region for a lateral PNP transistor; Figs. 27a and 27b are cross-sectional views similar to Figs. 26a and 26b, respectively, showing the etching applied to a doped to P + Sections after the oxide layer above the polyacetamide layer; Figures 28 & and 2813 show cross-sections similar to Figures 27 & and 2715, respectively, showing drive_in in the emitter and base regions A cross-sectional view after etching and etching to generate additional spacers; FIG. 29 shows a doped appearance of a prepared NPN transistor, the appearance is taken by SIMS; FIG. 30 shows when etching FIG. 28a and 28b The spacer shown in the figure is viewed from the top of the protective cover layer above the resistor. Figure 31 shows the cross-sectional view of Figure 2 7a, which only shows the ό-j ^ 0¾ fa figure. Figures 32a and 32b show cross-sections similar to Figures 2.8a and 28b, respectively, showing the Sectional views after the titanium and titanium nitride; FIG. 33 is a cross-sectional view similar to that of FIG. 3a, showing a cross-sectional view after etching a deep contact hole for electrical connection of a substrate; FIG. 34a Figures 34 and 34b are similar to the cross-sectional views shown in Figure 33, respectively. 15-This paper size applies to the Chinese National Standard (CNS) A4 specification (2 丨 OX2? 7mm) --------- X-- ---- Order ------ points (please read the notes on the back before filling this page) Γ4 2 3 〇 7 9 Α7 Β7 V. Description of the invention (13 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Cross-section view after all contact holes have been etched; Figure 35a shows that the final circuit element contains two transistors, two capacitors, and a -resistor element | new .. Its figure is similar to that shown in Figure 35b The cross-sectional view of FIG. 35a shows that the substantially-reduced circuit elements ^ are substantially the same without separation of the trenches; the final products are taken by an electron microscope as shown in FIG. 36 to each other, in which the deep matrix is connected The dots are filled with tungsten to see the circuit amine resistance and a trench-insulated NPN transistor; and, acetamidine. Figure 37 shows Topview®, which explains how different components are. "The best example of the 4th study" The following will describe the production of different 4 pieces with high performance "These components are all on the substrate at the same time Produced. Some of these diagrams (display-base diagram) are very schematic, but others are shown in the film = image 1 is the best final structure. You can also observe the two: 1 The description below has a defined doping pattern: the material is produced and constructed 'but these corresponding elements can also be produced from the oppositely doped type' material, that is, the first material is doped with a limited ρ and the finite N In some examples, a component made of a doped second material may also be made of a corresponding N-doped first material and a corresponding P-doped second material. &Quot; Figure 7 shows a P-type Silicon plane 丨 spreading at the bottom or 16 papers are fully compatible with Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page} 乂 丁-= ° 旅 2 3 Ο 7 9 V. Description of the invention (14 Α7 Β7 Sectional drawing of the male bureau of the Standards Consumer Cooperative before printing the buried N-type layer. This silicon plane 1 can be composed of a homogeneous, very weakly doped P-type plane, and its basic impedance is 10-20 ohms- Cm 'It can also be described in terms of the ρ-type or the epi plane, where the matrix', which is composed of a P-type (P +) highly doped plane with an impedance of tens of micro-ohm-cm, above which A P-type epitaxial weakly doped layer (P__) has been grown. The P-type of this epitaxial growth basically has an impedance value of ohm · cm. A starting material similar to the last-mentioned example mentioned above Used in bipolar structures, it is disclosed in the literature disclosed by v delta Torre et al. In "MOSAlC V-A Very High Perfance Technology" 'BCTM1991 pages 21_24. According to this document, a A highly doped p + -type substrate with an epitaxial intrinsic layer, that is, a layer without proper doping, and then a structure similar to that described below, such as bottom diffusion, is formed on the surface of this intrinsic layer. ° Using a known method The silicon dioxide protective layer 2 is added on the surface of the bite plane, for example, by a thermal oxidation method. The thickness of this oxide layer 2 is preferably selected to be about 0.8... By applying and patterning a photoresist layer 3 This oxide layer 2 is lithographically etched and patterned: to dissolve or etch away the oxides in these parts that are not protected by the photoresist layer 3, such as _ 7 & + ^ as dry as the garden / not. This oxidation Removal of the material can be carried out by known wet chemistry or by several methods, and then by desiccant method, and then-a known method to remove the photoresist layer 3.-Basically a thickness of several hundred angstroms The thin protective oxide layer 4 is thermally formed (please read the precautions on the back before filling this page) * 1Τ 17- The standard of the private paper applies the Chinese national standard () A4 ^ 72Ϊ〇'χ 297; ^ r423〇7 9 V. Description of the invention (15) The seal of the Beige Consumer Cooperative of the Central Bureau of Standard Vehicles of the Ministry of Economic Affairs is longer than the surface of a flat surface, as shown in Fig. 8. This protective layer is particularly thick, and the silicon dioxide layer 2 applied in advance is quite thick. In the area between the remaining parts of the part, because such a small thickness is not yet noticed / attended in that part. An N + -type bottom diffusion layer or an “N + buried layer” is originally generated. The method is to first do an ion implantation, as shown by the arrow. Arsenic is used in this ion implantation step. The implantation energy is about 50 keV and its doping concentration is about 3 x 10 ions / cm 2. The remainder of the thick oxide layer 2 will serve as a veil during implantation, and then the energy during implantation must be used so that only those impacting, the ions of the oxide layer 4 can penetrate the silicon substrate, as shown in the figure. The cross at 4a of 8 indicates that the other ions are blocked by the thick oxide layer. After the ion implantation is completed, annealing is performed at a still temperature (basically within 30 minutes at 11000) to drive the implanted dopants (that is, arsenic atoms) to generate a bottom diffusion layer 5, as shown in Figure 8. After completing this driving step, the final depth of the N + -type bottom diffusion region 5 ("N + buried layer") is about .5jCZm, as shown in FIG. During the operation of this driver, there is further oxidation on the cut surface at the same time, the silicon atoms on the surface are consumed, so that the thickness of the thin silicon dioxide protective layer bucket is increased to 2000 nm, thereby obtaining a There are more than 6 produced. Due to the consumption of tangential atoms, between the area covered by the previously applied thick oxide layer 2 and the area now thicker and still covered by a relatively thin oxide layer = there will be a step or Cover, and these steps in the subsequent -----____, 18-Standard of this paper (CNS) Α4 · (21 () > < 297g (Please read the precautions on the back before filling in this card) Order g : D23〇79 Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the Invention (16) The process is used as an alignment mask. Naturally, other N-type doping implants can also be used to produce The bottom diffusion layer 5 'is like antimony. However, the use of antimony needs to be annealed at a relatively low drive temperature, which is basically performed at about 125 crc for half an hour. It is used to generate all N + type bottom diffusions that are oxides. After the drive-in operation of 5 leaves from the flat surface, it is best to use a wet chemical method, and then the aforementioned step shape on the surface of the single crystal silicon plane can be seen, as shown in Fig. 10. Next on the flat surface A thin protective oxide layer 7 having a thickness of about 30-4 Onm is generated on the The growth method is best to grow by heat. Then, with the energy of about 0 keV and the doping concentration of about 4 x 1012 ions / cm 2, the ions, preferably boron, are implanted on the entire planar surface, and Additional p-type doping is generated in the region between the + -type bottom diffusion regions 5 as shown by the arrow in Figure 10. The implantation energy and the doping concentration can be adjusted so that these are then implanted into the The boron atoms in the N + -type bottom diffusion regions 5 which have been doped with Kun can be completely blocked and compensated by the doping in these regions, thereby 'the bottom diffusion 5 will continue to be N + type, and The reduction of the content is relatively small or can be ignored. It is worth observing that we can manage and obtain good functioning components without using the above boron implants, by increasing the doping in the original material with very low doping To the extent that it is close to the essence, it becomes a P-type. However, in the last redundant element in this example, the capacitance distributed in the bottom diffusion region 5 of the N + type will be higher. -19- Paper Standards apply to China National Standards (CNS) Α4 specifications (210X 297 PCT) (Please read the notes and then fill in the back of this page)

Printed by the Consumer Standards Department of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China Du 4 ^ 2 3 0 7 9 'a? And certain p-stomach-shaped intermediate regions have also been disclosed in Havemann, US Patent No. 5,374,845, 'see that patent for Figures 2 and 3. . After the completion of the implantation of the better boron ions, when a weak p-doped (ie p-type) region is obtained between 5 I in the bottom diffusion region, all oxide layers are removed from the planar surface again. It is best to 'wet chemically' make the step shape reappear, and use a known method to grow an epitaxial silicon layer 9 on the surface of the substrate, as shown in Figure 丨 丨. Layer 9 is preferably undoped (ie "essential silicon"). If necessary, this layer can be doped during the epitaxial growth to form an N-type. In this example, the content of the doped layer is basically ι X 10 / cm3. In the aforementioned US patent of Havemann, the corresponding epitaxial layer is very slightly doped, and its impedance is greater than 10 ohm-cm, but it can also be said to be essentially essential, that is, undoped. However, the homogeneously doped epitaxial layer will make the subsequent connection between the substrate and the surface at the so-called "upper and lower contacts" difficult. "When the epitaxial growth, the temperature used makes the former Receptor atoms in the sub-implanted P-type region diffuse into the matrix 1 and form the epitaxial layer 9 at the same time, so that the N + type may not exist at the junction of the matrix i and the epitaxial silicon layer 9 A P-type buried region 8 is formed at the position of the bottom diffusion layer 5, as shown in FIG. Once again, the epitaxial layer 9 has a stepped shape on the outer surface. As will be described later, the epitaxial layer 9 will be selectively doped to individually form N- and P-type regions (known as "N_holes and -20- National Standard (CNS) A4 specification (210X297 metric whole (please read the precautions on the back first, then fill in this page)

V. Description of the Invention (IS) Printed by the Consumer Cooperative of the Sample Procurement Bureau in the Ministry of Economic Affairs). In the N-type region (directly above the N + -type bottom diffusion layer 5), a bipolar transistor and a capacitor will be formed. On the middle portion, 'the p-region' will exist after forming the connection path or region as a connection between the surface or the circuit or element formed on the substrate 1. After the growth of the epitaxial layer 9 ′, a thin barrier oxide layer 10 (preferably formed by thermal oxidation) is produced on the wafer surface, as shown in FIG. The thickness of this oxide layer is approximately 40 nm. Above the barrier oxide layer 10 is a thin silicon nitride layer, which has a thickness of approximately 130 nm, and is deposited by the LPC VD method ("low-wish chemical vapor deposition method"). This nitride layer 丨 丨 is formed by applying a photoresist layer Π 'and patterning it by lithography. The nitride layer on the portion not protected by the photoresist layer 1 1' is engraved with a surname. As shown in FIG. I 2, and these parts include the area of the device, only the silicon dioxide layer 10 is left. The nitrogen-silicon layer 1 is preferably etched away by a suitable dry etching process. The etching process can selectively remove only the nitride layer but leave the oxide layer 10 under the nitride layer. Next, the arrow shown in FIG. 12 is shown. As shown, an ion implantation step is performed thereon to generate the above-mentioned N-type or N-region 13 (referred to as "N-hole") in the crystalline silicon layer 9 below the thin oxide. A silicon layer 10 is used as a protective layer on the surface of the epitaxial layer 9. In a preferred embodiment, the ion implantation step (see FIG. 13) used to form the N_region 3 is preferably performed by Approx. 45 OkeV energy and approximately 1.5X1012 ions / cm² of phosphorus implantation. But (Please read the precautions on the back before filling out this page) I l ^ ntn, -Λ. ▲ -21-This paper's dimensions apply China National Standard (CNS) A4 specification (210X: 297 mm) fA23〇 ^ 9 V. Description of the invention (19) A7 B7 n ^ i * 11— mi Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs. There is another form of doping in the N-region 13, and this implantation condition can be modified. After the incorporation, the photoresist layer 1 ′ is used in a known way. After removal, the thin oxide layer 10 in the opening of the nitrided layer 11 will be thickened by the ampoule formation, so that after growth, an approximately 450 nm-thick oxide layer 12 can be obtained, as shown in Fig. 13. The implanted heterozygote in the aforementioned implant is osmium phosphorus in the best example of Ben X. As mentioned earlier, during this oxidation step, L will diffuse into the crystalline layer 9 so that the fabrication of the N region 13 has been completed. Part f. Diffusion of some of these dopants will occur during subsequent steps including high temperatures. The remaining u part of the nitride layer (which is used as a barrier layer during thermal oxidation of the planar surface of silicon) will This causes the oxide to grow only in the areas where the nitride layer 丨 i has not been removed during this thermal growth, that is, in those areas that have been implanted. After oxidation, the nitride layer 丨 丨 is completely from the plane Removal is best by a wet chemical method. A thin oxide layer 10 below it is retained, and a stepped shape is formed on the edge of the thicker silicon oxide region 12, which is then used to generate the aforementioned p _-Type or p_-region (known as "P-hole") as a protective layer 〇 The energy in this ion implantation step can be adjusted so that ions can only pass through the area with the thin oxide layer 10 on its surface, and be blocked by the area with the thick oxide layer 丨 2 on its surface ^ A self-aligned p-region 14 or P-hole can be obtained with the aforementioned implanted N-region 13. In a preferred embodiment, this is used to form a p_region 丨 4 22 This paper size applies Chinese national standards (CNS) A4 specification (ZIOXM7). (Please read the precautions on the back before filling out this page.) 乂. Order lA23〇 " ^ 9 at V. Description of the invention (20) Occupied by the Ministry of Economic Affairs of the Central Bureau of Standards and Communications The cooperative printed ion implantation method implants boron with an energy of about 50 keV and about 2 x 10 " _2 X 1014 ions / cm2. However, this implantation condition can also be changed if another type of dopant is desired in the P-region 14. After the implantation step is completed, annealing is performed at a high temperature (basically at about 1000. (: 4 hours) to drive the implanted dopants to obtain the team and? Regions 13, 14 required Diffusion depth "The structure after annealing is shown in Figure 丨 3. The above-mentioned process for generating N_ and p_ regions has also been described in Havemann's US patent. After driving in, all the oxidized regions are It is best to remove by wet chemical contact, that is, a region with a thin oxide layer 10, a region with a thick oxide layer 12 and possibly additional oxide layers (this oxide layer can be made previously to drive implanted atoms Found on a planar surface during annealing). After the oxide layer is removed, a stepped shape appears on the surface of the silicon wafer. Then, the known loc method is used to define the effective opening for the component to be manufactured, Therefore, it is best to first apply a thin layer of barrier layer 15 'on the entire surface of the plane by thermal oxidation-as shown in Figure 14. Above this oxide layer 15 is deposited-a thicker oxide layer 16, the thickness of which is basically The upper limit is 200 nm, preferably LPCVD The nitride layer 16 is formed by applying a photoresist layer 17 and patterning it to define the element area. The nitride layer 16 is patterned by photolithography. The nitride layer 16 is not a photoresist layer 1 7 The protected part is etched away, as shown in Figure 14. The nitride layer 6 is best removed by an appropriate dry last engraving process. This etching process is long and can selectively remove only nitrogen-23. This paper is universal China National Standard (CNS) A4 Specification (2) 0 > 7297 mm) (Please read the notes on the back before filling out this page] Order * d23〇f A7 B7 V. Description of Invention (21) Central Government Bureau of Economic Affairs, Ministry of Economic Affairs Negative work consumer co-operative layer and thin barrier oxide layer left under it] 5. Figure 14 shows three separate N_regions, where a lateral NPN transistor is formed from left to right, A capacitor and a vertical NPN transistor. Then the silicon nitride layer 16 covers approximately the area of the base connection, collector and emitter of the lateral PNP transistor to be formed, and some of the electrode connections will be formed In one area, an electrode connection and a dielectric are formed in the capacitor in another area. Layer, and an active area for the vertical NPN transistor and an area for collector connection. After the nitride layer 16 in the opening of the photoresist layer is etched off, the photoresist layer will be known as a The method is to remove the silicon oxide layer 18 (the so-called field oxide) having a thickness of about 60 nm in the opening of the nitride layer 16 by thermal growth on it. In a preferred embodiment, 'The field oxide 18 is preferably grown under a substantially humid atmosphere. (: The appearance of the nitride layer 16 (which acts as a barrier layer during the thermal oxidation of the silicon surface) The silicon oxide will only grow in the area where the nitride layer has been removed. Since some silicon in the opening of the nitride layer 6 will be consumed when it is converted into silicon dioxide, the field oxide 1 8 will be partially recessed in the surface of the substrate or on the front surface of the epitaxial layer 9, called "semi-recessed". The results are shown in Figures 15a and 15b, where Figure 15a shows that capacitance and NPN are to be generated therein. The region of the transistor, and Figure 5B shows the region in which the lateral PNP transistor is to be generated. In the following figure, it can also be seen how the area of the field emulsion 18 grows at the edge of the gasification layer 16. -24-The ft dimension of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 5. Description of the invention (22 :) Staff consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 衽After the field oxidation is printed, the nitride layer 16 and the silicon oxide layer 15 are preferably removed by wet chemistry and then thermally grown thereon—a silicon oxide layer 15 having a thickness of about 30 nm is called κ〇〇〇 I. Oxidation layer. This layer can only be seen in the area between the field oxides 18 and then deposit a thin barrier layer 19 of polycrystalline silicon or polycrystalline silicon type material (its thickness is about 0 nm) on a flat surface, as shown in Figure 丨6 shown. In the preferred embodiment, the polyacetamide layer is obtained by LPCVD deposition. However, the barrier layer 19 is preferably made of another material, and this text is equivalent to a silicon type such as microcrystalline silicon or amorphous silicon. The upper part of the barrier layer 19 of polyethylene is a silicon dioxide layer 20, which is basically produced by deposition and has a thickness of about 250 nm. In a preferred embodiment, the oxide layer 20 is deposited by a thermal decomposition LPCVD method of TEOS (tetraethyl-orthosilicte). After this deposition, the oxide layer 20 is densified by an annealing process. Basically, it is in a humid atmosphere at 800C for 3 hours. The oxide layer 20 can also be made of LT0-oxide ("low temperature oxide") or pECVD_ oxide ("plasma-enhanced chemical vapor deposition,") because the purpose of this oxide layer is only Used as a hard mask in subsequent steps including etching the trench, this can also be seen in US Patent No. 4,958,213 to Eklund et al. However, 'the known process uses a gasification layer to replace the oxide layer 20. Next The structure is lithographically engraved. First, a photoresist layer 21 is applied and an opening is made in it to define a deep electrical insulation trench around the individual component and / or component group to be manufactured (referred to as Groove), see {Please read the notes on the back before filling this page)

'1T -25- Applicable to Chinese national standards (CNS > M specifications (2I0X297 public meal d23〇79) as far as possible paper size) 5. Description of the invention (23) Figure 16. In this preferred embodiment, the setting is useful to generate The openings of the trenches, so that they are placed above the area of the field oxide layer 8 and fully or partially overlap the p_area or p_ 8-14 and the N-area or N-hole 1 3 The broken surface of the connection (mainly 5 of these areas are placed inside the shame layer 9). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) In the protected position, the upper oxide layer 20, the lower polyethylene barrier layer Η and the bottom field oxide layer 18 will be etched away and reach the surface of the epitaxial silicon layer 9 downward. ^ Etching process ( It consists of several steps) (to remove individual materials) is best done by dry etching. After etching, the photoresist layer 2 is removed by a known method, and then according to the layout, Deep etching is performed by etching the epitaxial layer 19 down to the silicon substrate. Slot 22 'The layout is defined by an opening, which was just created on the top oxide layer 2 by lithography last before the opening. This oxide layer 2 is used as a mask layer during the trench etching step. _Hard cover. In the preferred embodiment, the grooves 22 are about 1 " m wide and about 6_5 vm deep. They are generated in such a way that their sidewalls are almost perpendicular to the surface of the worm crystal layer 19 And the way it is generated is that when the trench penetrates downwards and is terminated by a weak circular form at the bottom, it can be made very narrow, as shown in Figure 16. Its purpose is to help the next Polyethylenimine fills or inserts the trench 22 and helps reduce the mechanical tension in the substrate 1, that is, in order to reduce the tension of the substrate to prevent cracking in the deep trench 22, the deep trench 22 forms an indicator of cracking This type of groove has also been disclosed in Swedish Patent No. -26- This paper size applies to Chinese National Standard (CNS) A4 specification (210x29 · 7) Fog 423〇79 A7B7 V. Description of the invention Standard Bureau employee consumer cooperative printed 9701934-3, its name For, "Integrated circuit element and its manufacturing method". In a preferred embodiment, according to the above discussion, the starting material is composed of a commonly known epi-wafer or epitaxial wafer, that is, the matrix contains- The highly doped? + -Type silicon plane 'basically has an impedance value of tens of microohm-cm, and a weakly doped P-type fragment layer that has been epitaxially grown thereon. The grown shame layer is basically The thickness is about 6 # m 'The impedance value is about! 0_2 ohm-cm. Therefore, the depth of the trenches 22 will allow them to reach down to the p + -type highly doped I-second material, see The above cited references are published by V. delta Torre et al. This makes the high electric field along the lower portion of the trench 22 critical, and thus prevents leakage current from flowing through the surface of the envelope of the trench 22. Since the P-region 14 and the N-region 13 are separated by trenches, and the components are to be produced in the far N-region, good electrical insulation can still be formed between the different components to be fabricated. In a p-type weakly doped matrix (its basic impedance value is 10-20 ohm-cm), after the etching used to generate the trench 22, another ion implantation step is performed to increase The critical% of electricity below the lower portion of the trench 22, that is, what is commonly known as "trench channel termination". It is then preferable to implant boron atoms at an energy of about 20 keV and a doping concentration of 5X 1013 ions / cm 2 at a "tilt angle" of 0 ° C, as described in the aforementioned U.S. patent to Eldund et al. The energy and doping concentration in this implantation step may be changed according to the conditions in the process step of generating the trench 22. The manufacturing process for a weakly doped matrix in this example has been simplified-27- This paper size applies to Chinese national standards (CNS specifications (210 > < 297 mm) (Please read the precautions on the back before filling this page) Order i423〇79 A7 i423〇79 A7 Printed B7 by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The description of the invention (25) is briefly described in the literature of PC, Hunt et al. Its name is "Process HE: Used for analogy And Digitally Applied Highly Enhanced Trench Insulation Bipolar Technology ", Proceeding of IEEE 1988, Custom and Integrated Circuits Conference, New York, May 16-19. After the trench etch is completed, the oxide layer 20 remains A portion ("hard mask") is etched away. Then, the polyamine layer 19 under it serves as an etch stop layer. Next, the polyamine layer 19 is selected by using an etchant or an etching condition. It is removed, leaving a field oxide portion directly below the polyacetamide, and the silicon dioxide layer 15 b is not affected. As a result, the thickness uniformity of the field oxide can be maintained. This etching step is best done after the trench The etching of 22 is performed directly in a multi-chamber system or a “cluster system” by dry etching. After etching the trench 22 and removing the silicon dioxide hard mask 20 and the polyethylene barrier layer 19 and After the silicon dioxide layer 15 b, the planar surface is thermally planarized at about 900 ° C in a humid atmosphere. Then, the wall of the trench 22 is also oxidized, and the oxide layer on the wall of the trench The final thickness of 23 will be about 3 Onm, as shown in Figure 17. Therefore, a barrier oxide layer 24 is obtained on the upper surface of the wafer. This layer is grown simultaneously with the oxide layer 23 on the trench wall by thermal oxidation. Its thickness is about 3 nm, as shown in FIG. 17, and is formed on the surface of the plane, in particular, the area of the active region (referred to as KO-oxide) of the component to be constituted. Then on this barrier oxide layer 24 -28-The paper ruler Qi Cai Guan Jiaxian (CNS) Α4 size (210X297 public epidemic) ---------. 乂 ------ il ------ Travel (Please read first Note on the back, please fill out this page again} f4 2 3 Ο 7 9 A7 B7 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ) A thin silicon nitride layer 25 (preferably formed by LPCVD) is deposited, as shown in FIG. 18 "on top of it, another oxide layer 26 is also deposited, preferably using a TEOS decomposition method (also using LPCVD). Because Because LpcvD can be used to achieve uniform deposition, the surface layer corresponding to the nitride layer 25 and the oxide layer 25 obtained therefrom can also be found along the envelope surface and bottom of the trench 22. Finally, the thickness of the wafer is about}. 5 V twisted, undoped microcrystalline silicon or a thick layer 27 of electronic semi-insulating polyvinylamine (also using LPCVD), so that all The trench 22 can be completely filled with this silicon layer. Microcrystalline silicon is used in the preferred embodiment because it gives a good degree of filling. After the microcrystalline silicon or polyethylenimine layer 27 is deposited, this layer can be removed from all the upper or outer surfaces of the plane by dry etching, as shown in Figure 丨 7, so that the material from this silicon layer will only remain on Trenches 2, 2 and 2 In the preferred embodiment, when the "square-shaped oxide layer 26" of the microcrystalline silicon layer is exposed on the upper part of the plane or on the outer surface part Yaba, the step of engraving is terminated. Therefore, it is possible to avoid excessively engraving the microcrystalline silicon of the filling material of the trench 22. After this step, it is found that the trench 22 is not completely filled. After the etching is completed, the silicon wafer is heated in a humidity of about 95 ° td. Guang-V Then the upper surface of the crushed layer 27 (filling the groove 22) is emulsified, so that a dioxide insulation layer 28 (called "oxide cap") having a thickness of about 0.4 m is formed in the groove. The opening is shown in Fig. 19. The nitride layer 15 of the present invention serves as-it can prevent the other parts of the plane from being further oxidized. ^ Θ -29 〇Χ29Τ ^ (Please read the notes on the back before filling in this page j-* 17 丨 · ^ r4 23〇79 a? £ ________ B7 (27) The thin oxide layer 26 printed on the upper surface and the nitrided layer 25 below the oxide layer 26 printed on the upper surface by the Consumer Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs are then removed by dry etching. This dry etching step reaches the nitrogen The layer immediately below the formation layer 25 is stopped, that is, the field oxide region 18 and the barrier oxide layer 24 are exposed as soil. The trench 22 is also filled with an electrically insulating material, such as silicon oxide. Therefore, if Without the microcrystalline silicon layer 27, the thicker oxide layer 26 can be used instead to 'completely fill the trench 22, such as using the SACVD method ("sub-atmospheric chemical vapor deposition method"). This silicon oxide layer consists of A suitable dry etching process is etched away until a flat surface is formed in the opening of the trench 22. Those who are involved in this planarization step will also remove the nitrogen silicon layer 25 directly below the silicon oxide layer ( In the flat or horizontal part), the nitrogen-silicon layer functions as the same etch stop layer in this etching step. In this example, thermal oxidation is not required to form the insulating layer 28. The nitrogen-silicon layer 25 remains in the trench In the groove 22, It is used as a diffusion barrier layer to prevent possible impurities in the filling material. At the beginning, it was mentioned that the bottom diffusion layer of N + is known as a low impedance collector electrode in an NPN transistor. The low impedance between the silicon surface and the collector connection of the buried bottom diffusion 5 forms a so-called collector plug. This plug uses a photoresist layer 3 1 on the entire surface of the wafer. It is engraved with the lithographic surname in the way that this layer is laid out, so that the opening area 3 0 ′ of the plug for this photoresist layer 31 can be formed on the area under consideration. In this preferred implementation In the example, the bottom diffusion layer 5 is also used as a flat surface at the same time. -30- The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page), 1Τ ί · # --- • J. I-In |: 4 2 3 0 7 9 A7 B7 V. Description of the invention (28) One of the electrodes printed by capacitors in the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. Therefore, in this process step In the figure, the region 3 ″ as the electrode in the photoresist layer is also defined. Here, This capacitor can be manufactured within the domain 'and this region contains two separate connection plug regions which are connected to the N + -type buried region 5' to reduce this buried bottom diffusion layer 5 (constituting a capacitor connected to one of the capacitor electrodes) Section) series resistance. The openings in the photoresist layer 31 are manufactured in such a way that they can cover the entire area between the field oxide layer regions. This also means that the remaining part of the photoresist layer 31 covers the field oxide layer. The entire other surface of this interval can be said to be that the edge of the opening in the photoresist layer is always located above the area of the field oxide layer. The opening is also provided above the area 30, '' to facilitate the fabrication of the base connection of the lateral pNp transistor, as shown in Figure 20b. After the layout of the photoresist layer 31, the opening to the photoresist layer 3 (that is, the opening of the region 30 'for the collecting plug), the region 30 "for the capacitor electrode, and the base connection The opening of the region 30, is doped to obtain a strongly doped region, as shown by the arrows in Figures 20a and 20b. This doping step is preferably performed with an energy of about 50keV and 5 X 1015 ions / cm² doping concentration ion implantation such as phosphorus. It is important that the energy selection in this implantation step prevents the defect sites introduced into the silicon due to this implantation step from By reaching the bottom of the field oxide layer or the depth defined by the lower surface, that is, the level at which the layer terminates, as seen in the downward direction of the planar surface. If the defect extends further downward, it will One of the adjacent areas causing the emitter-base junction and / or the base-collector junction — —31 — ^ Zhang Chi Chinese National Standard (CNS) from the specification (2ΐ〇χ295 ^ I tn! Rn t — _ _- .--- I i _ _ T _ _ _ _ _ _, exhibition * · -0 '" (Please read the notes on the back before filling this page) A7 A23QT9 ^ 2. The misplacement of invention description (29) and the extremely leakage problem in the NPN transistor to be produced. Therefore, the implantation energy and doping concentration sometimes need to be based on what was previously done to generate the field oxide layer 18. The conditions of the field oxidation change, especially as described in the aforementioned Swedish Patent Application No. 9701934-3. After the implantation step, 'the thin, protective oxide layer 24 is removed from above the implanted area, preferably This is done by dry etching, as shown in Figures 20a and 20b. However, it can be seen that the oxide layer 24 will remain on the surface portion covered by the photoresist layer 31, that is, in the bipolar NPN transistor. A base region 36 'is formed between other regions, as shown in FIG. 2 U. Then, the photoresist layer 31 is removed in a known manner, and then the dopants introduced in the implantation step are removed. Drive in, the plane is annealed in the best non-oxidizing environment (such as containing nitrogen or OR) at a temperature of substantially 90 ° C for about half an hour. Β The final N + type collector plug after this annealing process 3 〇, the collector electrode 32 feet and its connection 32, (also ν + type) and Connect the plug 32 of the embedded base connection layer 5 in the lateral PN transistor, as shown in Figures 21a and 21b. After the above annealing step is completed, the plane is etched with diluted hydrofluoric acid—temporarily Time 'will remove the possible thin oxide layer above the collector plug 2 1 for the NPN transistor and within the base connection area 30 for the PNP transistor (this layer has already been formed for Capacitor area 30 "and area 30, within), after etching, it is best to deposit a thin silicon nitride layer 34 on the plane by LPCVD, as shown in Figure __32- This paper size (eNS) Α4 (_21 () χ297 /

--------- i ------ 1T ------ ^ f Please read the notes on the back before filling in this page. J Printed by the Consumer Cooperative of the Central Standards Bureau, Ministry of Economic Affairs, r4 2 3 Ο 7 9 V. Description of the invention (30) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs == shown. The role of the nitrogen hard layer 34 is to take two special purposes in the manufacturing process: 1) The area of the silicon nitrogen layer 34 directly on the surface of the silicon plane (this area f is included in the capacitor area 30). And, where the capacitor electrode 30 is also to be formed, < a) The contacting portion will be used as the electric layer of the capacitor to be made. This nitrogen silicon layer has a higher dielectric constant than silicon dioxide, and is used. A nitride dielectric capacitor has a high capacitance per surface unit compared to a foot capacitor with a shattered dielectric layer. The thickness of this nitride layer makes the capacitance of the capacitor approximately 2 4fF / # This corresponds to LPCVD deposition and The thickness of the nitride layer 34 is about eight. The silicon nitride layer 34 is deposited on the active region 36, and the remaining oxide layer 24 (here, a bipolar NpN transistor to be generated later) is formed. It will partially increase the thickness of the insulation area, so there will be less parasitic capacitance for the collector-base junction. As shown in Figure 21a and 21b, after the silicon-nitrogen layer 34 is applied, The method of shadow etching is used to illustrate the plane. The method is to apply a photoresist layer 35 first, and then apply it to the surface. To define the base region 36 'for the NPN transistor to be generated and the openings 37 ", 37' for a collector, and the emitter of the lateral pNp transistor to be generated, and To define an opening to connect with the substrate contact 37 'in the P_ region. The position of the opening to define the base region 3 6 ′ of the NpN transistor to be fabricated is such that it is set on the area without the% oxide layer 18, and the edge of the opening is set on the field oxide. The area of the object layer 18 is not too small. For 33 paper music scales applicable to the Chinese National Standard (CNS) M specification (2ΐ〇χ297 mm) (Please read the cautions on the back before filling out this page} • 乂-* 17 i ^ 1 ------ ---- / 423079 V. Description of the invention (31) A7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The openings of the collector and emitter in the lateral PNP transistor to be manufactured are set in the same way in field-free oxidation Above the region of object layer 18. However, the edge of this opening is adjacent to the edge of the field oxide layer 8 as shown in Figure 2 1b. These openings are also placed on the N-region 13 and thus on N Above the + -type bottom diffusion layer 5. On the contrary, the opening for matrix connection in the photoresist layer 35 is provided above the p_ region j 4 and thus above the P-type bottom diffusion layer 8 Next, the opening of the photoresist layer 35 is etched, preferably with a dry name. This dry etching step is performed sequentially, first the nitride layer 34 is removed, and then the lower oxide layer 24 is etched. And stop etching when the silicon surface is exposed. The specific layout steps in the process described in this article The NPN transistor can reduce the area of the base region. This area has been determined by the opening in the field oxide layer, but in this article it is determined by the opening edge of the photoresist layer 35. In addition, it can avoid The base region generated in the NPN transistor is very close to the edge of the field oxide. Here, because of the "pile_up" of the doped ions in the N_ region or N hole 13, there will be an increased dopant concentration. As mentioned above, the layout of the openings in the nitride layer 34 and the oxide layer 24 between the regions of the field oxide layer 18 is to reduce the collector and base of the NPN transistor to be manufactured. The electric valley value between them is based on the fact that a well-defined Kai 2 can be obtained, and the rest of the nitride layer is used to form the dielectric layer of the electric valley to be manufactured. In addition, this same cloth The steps in the figure can also be used to define the distance between the emitter and the collector of the lateral PNP transistor to be made. (Please read the precautions on the back before filling this page) Λ Order nil t. ___- 34- This paper size applies China A7 B7 ^ d23〇79 Five 'invention description (32) {Please read the back (Notes should be filled in this manual) The advantage of this process is that the distance between the emitter and collector can be well defined, and at the same time, the emitter and collector openings can be made smaller, thus reducing the Capacitive coupling. This distance can also be defined by the% oxide string 18, as shown in Figure 2 1b. As described above, the advantage of making red is that the dielectric layer of the capacitor (which is formed by the nitride layer on the plug 32 of one electrode constituting the capacitor) can define the emitter_base region of the NPN transistor to be fabricated. At the same time, the layer of 36 ′ is generated at the same time. At the same time, the parasitic distribution of the capacitance value between the collector and the base of the NpN transistor is reduced, and because it is defined by lithographic etching, it is strictly necessary The emitter-base region 36 'in the fabricated NpN transistor will be well defined, and the distance between the emitter and collector in the PNP transistor to be fabricated can also be well defined. The Central Standards Bureau, Shelley Consumer Cooperative, Ministry of Economic Affairs, printed the finished nitride layer 34 and oxide layer 24 to define the base region 3 for the NPN transistor to be manufactured, and the handle to be manufactured. After the collector windows 3 7 ″, 37 ′ of the PNP transistor, and the substrate connection 37 ′, the photoresist layer 35 is removed by a known method. Next, in the present preferred embodiment, a thin amorphous silicon layer 38 with a thickness of about 200 nm is deposited on a flat surface (preferably by LPCVD) as shown in FIG. 22. This silicon layer 38 will form a conductive path for connecting the base of the NPN transistor to be manufactured, an electrode of the capacitor to be manufactured, and an emitter of the lateral PNP transistor to be manufactured in a later process. The conductive path to the collector and the connection to the substrate contacts. The silicon layer 3 8 can also be microcrystalline silicon 35 This paper ft scale applies to the national standard (CNS) A4 specification (210X297 mm) r4 2 3 0 7 9 5 Description of the invention (33 A7 B7 Printed by Polycarbonate and other materials such as a shellfish consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In the subsequent ion implantation (such as ::: layer 38 is doped to become a strong hybrid P-type. In the ion implantation step, it is best to implant the square of BF2 with an energy of about 50 keV and a doping concentration of 7 square centimeters. F: 'The implantation energy can also be adjusted to The implanted boron atoms do not reach down to the surface of the crystal layer 9 of the county. The doping concentration and energy = can also be changed according to the amorphous silicon layer 38 and the thickness naturally generated thereon. This ion implantation Other boron elements and / or atomic boron can also be used: into the attack layer +, but in this example its energy and doping The atom must be rounded to an appropriate value. A silicon oxide layer 39 is deposited over the amorphous silicon layer 38 and has a thickness of approximately 150 nm. In the preferred embodiment, the oxide layer 39 is PECVD. It can be obtained by the method of deposition, but the type of low-temperature oxidation (such as some suitable CVD method, such as LT), which can be called, can also be used. In the preferred embodiment, when the oxide layer 39 is deposited, The temperature is kept very low, so that the amorphous silicon layer 38 cannot be recrystallized. When a conductor that is used to connect the substrate of the NPN transistor is produced, an amorphous body implanted with bf2 is used under the oxide crush protection layer 39. The advantages of silicon (deposited by PECVD) have been described in Swedish Patent Application No. 9504 1 50-5. After the silicon oxide layer 39 has been deposited, the surface of the 'plane is covered with a photoresist layer 40, and this layer is The layout is lithographically etched to define an area as shown in 40. This area is included in the capacitor area. 36 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please first Read the notes on the back of the page and fill in this page) 乂 定 # A7 B7 _yA 2 ^ 0 Ί Q— V. Description of the invention (34) (Please read the precautions on the back before filling in this page), and it is used for the upper electrode belonging to the planar capacitor to be made, and it is placed in the entire area 30 "of the nitride dielectric layer μ Above, the 'region 40' is covered with a photoresist layer 40. In addition, the photoresist layer region 40 covers the starting emitter base region 36 '' which is to be made and it also covers the region 37 for the emitter, , And the collector region 3 7 ″ for the lateral PNP transistor to be fabricated to facilitate subsequent contact connection ′, as shown in FIGS. 23 a and 23 b. Using the currently applied and patterned photoresist layer 40 as a mask, the silicon oxide layer 39 and the underlying amorphous silicon layer 38 in the opening of the photoresist layer will be etched away. This process of engraving is best performed by continuous dry etching in a multi-chamber system or, cluster, system. This process will be completely exposed in the opening where the nitride layer is stored on the photoresist layer 40. The silicon-nitrogen layer 34 is stopped at times such as above the field oxide and in the region 40 "in which the bottom electrode of the capacitor to be formed is connected via the buried diffusion region. The results are shown in Figures 233 and 23b. In the preferred embodiment, the etch sequence used allows the silicon substrate with a thickness of about 20-4001111 in the opening of the base region 36 ′ to be used in the final etching process ( It is commonly known as the over-etching step.) It is consumed. It is printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. After the above-mentioned etching step, another incorporation step is performed on the area where the NpN transistor will be formed. The so-called "widening of the base", and thus improved the high-frequency characteristics of the transistor, such as MCWilson's literature in ESSDERC, 90, Nottingham, September 1990, "The applicaUon 0f 3 selective- 37- 藿 A23〇7 α Α7Β7 Warp Ministry of Consumer Cooperatives Central Bureau of Standards staff printed skirts V. invention is described in (35 implanted c〇Uect〇r to an advanced bip〇lar pr〇ces $ "

As described. In this preferred embodiment, the dosing of the sasongo 3 P AA,, r in this embodiment is performed in the form of ion implanted phosphorus, as shown by the arrows in Figures 23a and 23b, and This is best done in two steps. During the first step, the phosphorus was implanted at a doping concentration of about 20 × with an energy of about 1 × 10> 2 ions / cm 2. During the second step, the energy was about 46 × keV and about The scale was implanted at a doping concentration of 1.8X 10 ions / cm 2. The mutual order of these two implantation steps can be changed. In the correct manufacturing process, small adjustments of the implantation impurity concentration and energy can always be used to compensate for small process variations, such as the thickness of the epitaxial layer 9. It can then be observed that the dopant system is consistent or aligned with the opening of the initial emitter-base region 36 ', and the photoresist layer 40 remains on the plane during the implantation process to prevent dopants (a preferred embodiment Middle scale) into the epitaxial layer 9 on the non-extended place. Therefore, after the redundant process steps, the added collector doping will not exist under the so-called essential matrix, that is, the region along the edge of the region 36 ′. Here, the P + type amorphous silicon layer 38 will be in contact with the surface of the epitaxial layer 9. In this way, the low capacitance between the collector and the base in the NPN transistor to be produced must be maintained. After the implantation step is completed, the photoresist layer 40 is removed in a known manner, and then a thin silicon dioxide layer 42 ′ having a thickness of about 20 nm is deposited on the planar surface so that it can particularly cover the initial radiation. -The opening 3 6 ′ at the base region, see FIG. 24. In this preferred embodiment, 'this oxide layer 42 is preferably heat-38-' in a wet environment at 800 ° C, and the paper size is in accordance with Chinese standards (CNS > A4) (210X297 mm ----- -1T ------ # (Please read the notes on the reverse side before filling out this page) Consumption Cooperation by Staff of the Central Bureau of Standards, Ministry of Economic Affairs, printed fA23〇 ^ 5. Description of the invention (36) Deposited by oxidation = In this oxidation step, the previously applied oxide layer 39 (as described above, this layer is deposited at low temperature by PECVD) will form a silicon dioxide layer 41 on the vertical free of the amorphous silicon layer 38 Simultaneously densified on the sidewall or edge surface. During the oxidation process (which itself includes an annealing step), the amorphous silicon layer 38 will be converted to polycrystalline silicon or polyethylenimide when the implanted boron is redistributed. (That is, it is partially crystallized). The previous amorphous silicon layer 38 will be referred to as a p + -type polyethyleneamine layer later in this document, and the results are shown in FIG. 24. As described above, 'silicon dioxide is being generated. After layer 42, it is better to implant boron in the plane, as shown by the arrow in FIG. 24, to form the NPN transistor to be manufactured. The mass base region or the effective base region. In the preferred embodiment, boron is ion-implanted in a manner of about kekeVi energy and about 7X 1013 ions / cm 2. This topmost Applying slight changes in the thickness of the oxide layer 42 will make corresponding adjustments in energy and / or doping concentration. The implantation will only penetrate through the silicon oxide layer 42 directly at the position above the epitaxial layer 9 ( That is, the oxide, base, and nitride layers applied differently in the initial emitter-base region 3,6. After completing the base implantation as described above, the plane is thermally oxidized (preferably at 800 °). C in a humid atmosphere for about 2 hours), and further reduce the surface concentration of the boron atom. In the preferred embodiment, a layer of approximately 180 nm thick nitride layer 44 ′ is uniformly covered on this plane by LPCVD. As shown in Figure 25a. In the preferred embodiment, '____ -39- This paper size is applicable to the Chinese National Standard (CNS) A4 specification UlOx ^ T ^ i-) --------- clothing --- --- ΐτ ------ ^ (Please read the notes on the back before filling out this page) A7 B7 Employee Co-operation of Central Standards Bureau, Ministry of Economic Affairs社 印 褽 fA23〇 ^ 9 V. Description of the invention (S7) The nitride layer can be etched using a special anisotropic dry etching process until the position where the largest step is formed in the nitrogen layer 44 by a known method. (Such as the opening of the NPN transistor to be made at the opening of the base region 36) still retains the nitrogen stone stripe, or, spacers "up to 45. In this etching step, not only nitrogen The nitrided layer 44 is etched away, and at the same time, the previously applied nitrided layer 34 at the area immediately below the lastly applied nitrided layer 44 is also etched away. When the area surfaces of the field oxide 18 and the oxide sand layer 4 2 are exposed, the etching is stopped. The opening in the beginning of the emitter-base region 3 6 ′ (which is formed during this etching of the nitride layer 4 4) will constitute the so-called emitter opening 36 ″ The emitter in the NpN transistor will be separated from the p + type polyethyleneamine layer 38 due to the nitrided side strip 45 and the oxide layer 41 on the edge surface of the polyethylenamine layer. During this etching process, the The surface of the silicon is also exposed in the area 40, where the connection sand surface that can form the bottom electrode in the capacitor to be made at this area 40 "is also exposed in the area 45, where the lateral PNP electricity to be produced can be formed. The base of the crystal is connected. The remaining silicon oxide layer 42 which is only visible in the emitter opening is removed by a wet chemical method or a dry etching method. In the preferred embodiment, 'a two-step dry-etching method is used. First, the oxide layer 42 is removed by RIE ("Reactive Ion Etching") in a plasma of Ar / CHF ^ CF4. In the atmosphere of NF3, the mild in-situ ^ silicon etching method is used to remove heterodyne and radiation damage generated in the previous RIE step. The etching step in Ar / NF3 will self-emitter opening 36, within -40- This paper size is suitable for wealth and family (t) (CNS) Α4 · (plus magic 97 public love (read the notes on the back of the poem first) (Fill in this page)

Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ¥ 42307 9 A7 ____ B7 V. Description of the invention (38) The thickness of the silicon layer is removed from the free surface of the crystal layer 9 (essential base) by about 15-20 angstroms. . Since this etching step will affect the shape of the essential base ', it may require that the etching depth be changed according to the current gain factor (Hfe) of the transistor to be manufactured. In the modified embodiment shown in FIG. 2b (where the so-called, disposable spacer is used), the nitrogen biting layer 44 may be composed of a thinner nitride layer 144 (its thickness is about 50nm) was replaced. The nitride layer 144 was also uniformly deposited on the plane by the LPCVD method, and a silicon oxide layer 148 with a thickness of about 150 nm was deposited on the nitride layer. The silicon oxide layer 148 was made by PECVD. -TEOS-oxide or SACVD-oxide composition 'It covers the surface in a nearly uniform manner. This oxide layer 148 is characterized by being produced at a low temperature, such as about 400 ° C, so it will not be synthesized by stoichiometrically The oxidative breakdown composition is closer to that of 'porous'. The last-mentioned characteristics are used in the following steps. After the above-mentioned product step, the anisotropic dry etching is used to apply the composition. The emulsified layer 148 and the lower nitrogen hard layer 144 are removed. As the example described herein, "This re-etching is a three-step rie process." Among them, the oxide layer 148 is first removed with a mixed gas of Ar, CHF3 and CF4. The nitride layer 44 has been exposed on a flat surface On a parallel surface (for example, on a nitrided surface above the field oxide region 18), the etch stops, and the side of the paint-permeable oxide layer 1 4 8 remains on the vertical surface. Then In step 2, use the last 41-this paper applies the Chinese National Standard (CNS) A4 size (210X297 mm) according to the size H tnn In · n flufi 1 ^ 1. (Please read the precautions on the back before filling this page )-^ 4 ^ 3-CLZa. V. Description of the Invention (39) The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed the dagger side bar as a cover to remove the nitrided layer 144, that is, to repel 2 on all parallel surfaces. Removal. When the surface of the emitter region 18 and the silicon oxide layer 42 are exposed, this etching step is stopped. Step 3 is similar to this embodiment 'removing the oxide layer 42 remaining in the emitter opening 2 with rie. Then, the silicon etching with the sum of Ar / NF3 is performed to remove the surface impurities and light shot damage. After the dry etching is completed, the emitter opening will be changed by a “permeability”, oxide / nitride / oxidation. Synthetic side bars or spacers composed of objects 148, 144, 39. Placing the #synthesized side strip in HF (argon fluoride acid) for a short time can remove the outer, permeable oxide 'without significantly striking the area with thermal oxidation. The "permeability," oxides are effectively removed from HF-steam in equipment such as "FSI / Excalibur '", but a HF-based wet chemical bath can also be used. The side bars after this engraving process will not have a triangular cross-sectional area, but their cross sections will be more similar to "L" as shown in Figure 2 5b. The aforementioned method, which includes a so-called "disposable spacer", has the advantage that the openings in the P + -type polyethyleneamine layer 38 will not be narrowed. Therefore, it facilitates the following deposition and doping The electrons diffuse outward from the N + -type polyethylenamine 4 6, that is, the so-called "multi-plug effect" can be suppressed. Fig. 25c shows the NPN transistor manufactured according to the embodiment described in Fig. 25a. Bottom view of the cross section, that is, -42 is left in the emitter opening. This paper size is applicable to the Chinese National Standard (CMS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page). 2. · 3 Ο 7 9 V. Description of the invention (40) The side strips of nitride printed by the Consumers' Cooperative of the Central Standards Bureau of Shaoxing Ministry. Figure 2 5d shows the use of the method according to the above-mentioned "disposable spacer" method. The corresponding structure diagram can also be seen in Figure 25b. The cross-sectional image was taken with a transmission electron microscope XTEM. After being exposed on the broken surface of the single crystal in the emitter opening 36 ", the LPCVD method is used on the collector plug 31 of the NPN transistor to be manufactured and in the region 40" of the bottom capacitor electrode 32. A 250 nm thick polyethylene layer 46 is deposited on the contact area and on the base connection of the lateral PN transistor to be manufactured, as shown in FIGS. 2 and 26c. The polyvinylamine layer 46 is then doped in a manner that is preferably ion-implanted and / or phosphorous, as shown by the dashed arrows in Figs. 26a and 26d. It can be seen that the figure shows that the polyamide layer 46 is a figure before (dotted line) and after (solid line) the final layout, and its content will be described later. In this preferred embodiment, the ion implantation is performed in two steps before the step of patterning the previously applied polyvinylamine layer 46 as described below. The first step is to comprehensively implant arsenic on a plane with an energy of about 50 KeV and a doping concentration of about 3 X ί! 5 ions / cm 2, and then use a photoresist layer 48 and a photoresist to Θ The plane of the layer is lithographically patterned on the plane, leaving a photoresist layer 48 on a portion of the plane having a high resistance (referred to as Rhi, described later). Using this photoresist layer 48 as a mask, another arsenic ion implantation was performed, but the ion doping concentration was about 1.2 × 1016 ions / cm 2 this time, and the energy was about 150keV. This is shown in Figure 26b. It should be understood that all components on this plane, except for the area of high impedance resistance Rhi, are all (谙 read the precautions on the back before filling this page). 丨 salt ____- 43 · This paper is applicable to niT Mound standard (CNS) M specification (ϋ97 瘳 A 2 3 ◦ 7 9 a? _____B7 V. Description of the invention (W) The above two implantations were performed. Next, the lithography etching layout of the plane was performed, and then The area where the low-resistance resistance RL0 is defined 'in the last-mentioned case' will be left on all parts of the planar surface except for the low-resistance resistance R1, which photoresist layer is applied during this layout step and is not shown. Beyond the opening of 〇 "using this photoresist layer as a mask, implanting the field with an energy of about 25keV and a doping concentration of about 4 X 1 015 ions / cm 2 'These operating methods are not shown in the figure, but Comparison 26b. After completing the fabrication steps described in this article, the implantation step as described above can achieve a high impedance resistance Rhi with a surface impedance of about 500 ohms / square and a surface impedance of about 100 ohms / square. Low impedance resistance RL0. To compensate other Cheng can change the doping concentration and / or energy to the implant do a little adjustment Central Bureau of Standards, consumer cooperatives HIGHLAND Ministry of Economic Affairs print

(Please read the notes on the back before filling in this page J-After different doping steps to form the polyacetamide layer 46, pattern this layer using a known lithography method, as previously The explainer then defines the contact area of the emitter 49 'and the collector 50' for the NPN transistor to be fabricated, and the contact area 51 of the bottom electrode of the planar capacitor to be fabricated (see Fig. 26a). Connect to the base of the lateral PNP transistor to be fabricated, as shown in Figure 26b, and low resistance 5 2 'and high resistance 5 3' resistance (see Figure 2 6 b). At the position where the acetamide layer 46 is in direct contact with the surface of the single crystal strip in the emitter opening 49 ", the highly doped polyacetamide layer will be driven into the base region of the essence in a later process level. Extremely doped source. Use its photoresist layer layout as a cover (Figure-44- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)) Eliminate cooperation. Du printed | ΤΛ 9 3 Ο 7 9__β7 V. Description of the invention (42) Not shown in the formula ' But the results can be seen in part in Figures 26a and 26c) 'The polyethylene doped layer 46, which is doped with N +, is engraved by the last name until the surface of the field oxide 18 directly below it is exposed. This etching The step is preferably performed by RIE in a plasma consisting of Ch, HBr, and O2. After the polyethylenimine layer 46 is etched, the photoresist layer is removed in a known manner. It will then be generated previously The P + -type polyethylenamine layer 38 over the oxide layer 39 is etched away. This etching step is best performed by dry etching. It can be used for the entire surface in a comprehensive manner, or in a better way. After the relevant parts are defined by the shadow etching method, this will be described below. Therefore, in the preferred embodiment, the plane is first laid out by lithography, so the polyimide layer 38 and the polymer layer applied later Openings are created in other areas between other locations on the area of the Ethylamine layer 46, as shown in Figures 27a and 27b. Next, the light is etched in a dry manner in a plasma composed of, for example, Ai_, CHF3 and CF4 The oxide layer 39 in the opening in the resist layer 52 is removed. This etching process is stopped when exposed. The advantage of this step is that it does not include a full-scale engraving but a lithographic etching pattern layout before etching. The advantage is that the field oxide region 18 will be protected by the photoresist layer 52. It has been etched during the etching step), so it can maintain its integrity. Another advantage is that the oxide layer 39 will be left undesired with debris (explained below) (for example for lateral PNP to be fabricated) On the part of the emitter region 52, above) of the crystal, see ^ --------- < -------- II ------ ^ (Please read the note on the back first (Fill in this page again) -45-

A7 B7 Λ23019 V. Description of the invention (shown in 43 27b. This gives the process a better reproducibility. According to the aforementioned process, the results after etching the oxide are shown in Figures 27a and 27b. After the contact etching process is completed, The photoresist 52 is removed in a known manner, and then a thin oxide layer of about 30 nm thick is deposited on a flat surface, as shown in Figures 28a and 28b. In the preferred embodiment, this The oxide is deposited with TE number. But 'the oxide layer can also be other methods or PECVD. Next, over 100% of the currently applied oxide layer, a good LPCVD method is used to deposit about 100 nm of nitrogen. The silicon layer 58 is uniformly applied to the surface of the plane. After the deposition of the nitride layer is completed, the plane is annealed at a high temperature to drive and enable the previously implanted ions. In the preferred embodiment, this driving step is performed in two steps. First, the surface is treated in a mixed gas of oxygen and nitrogen and oxygen at 85 ° C in an oven for about 30 minutes in order to Make the impurity ions more uniform ": in the implanted layer. Next on this plane Annealing in nitrogen atmosphere, about 1 075. (: up to about 16 seconds, employees of the Central Standards Bureau of the Ministry of Economic Affairs consumer equipment printing equipment "(" rapid thermal annealing "). In a preferred embodiment, a so-called ", Hotline" (Hot) iner control drive. Temperature during the step. Processed in the RTA equipment

The combination of St: can sometimes be changed depending on the transistor material to be made. It should be understood that during this annealing operation, the oxynitride layer will be maintained as a protective layer on this plane to prevent paper-like CNS.) ΑΊ _____ Β7 5. Description of the Invention (44) The implanted ions are diffused out into the surroundings. During this annealing operation, the substrate implanted in the N + -type polyethyleneamine layer 46 above will penetrate the essential base via diffusion, and then form an emitter-base junction 6 Γ. In the entire process described in this article, the emitter depth is about 60nm, and the remaining thickness of the essential base below this emitter is about 100nm. The arsenic concentration in the emitter opening in the contact area between the surface of the epitaxial single-crystal silicon layer 9 and the N + -type polyacetamidine 49, is substantially about 4 × 1020 atoms / cm3. The corresponding concentration of boron in the emitter base junction in the essential base is approximately 8 × 1017 atoms / cm3. Similarly, boron, which has been implanted into the p + -type polyamidamine layer 38 due to diffusion, will penetrate and connect to the base of this essence. For the entire process described herein, the base depth of this essence is about 200 nm. The corresponding boron concentration in the boundary surface between the P + polyacetamide layer 38 and the epitaxial single crystal chip layer 9 It is basically about 2 × 1019 atoms / cm3. The resulting highly doped P + -type region is called the essential base. The matrix contact 6 0 ′ is formed in a manner similar to the manner in which outward diffusion from the p + -type polyethyleneamine layer 38 is performed. Similarly, emitter electrodes 62 ,, and collector electrodes 62 "for a lateral PNP transistor to be fabricated can be formed, as shown in Fig. 28b. Fig. 29 shows the N + type polyethylene measured by SIM S. The shape of the dopants below the amine emitter. The thickness of polyethylene is indicated by the shaded part on the left side of Figure 29. For analysis purposes, some of the gentle signals derived from the emitter are amplified, so Seen at the edge of the god than actually -47- This paper size applies the Chinese National Standard {CNS) A4 specification (2S0X297 mm) ----- I-I — ϋ----- 丁 _ in _] 1 Izumi-12.5 Service {Please read the notes on the back before filling out this page} Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs f 4 2 3 0 ^ 9 ^ A7 _ 87 V. Description of Invention (Μ) Further In the captured boron signal (indicating the extension of the base). After driving in, the plane is patterned by lithographic etching, so that after the layout, a photoresist protective layer 60 will remain on the resistor body of the resistors Rm and RL0, As shown in Figure 30. The terminal portion of the resistor will be exposed. After the photoresist layer 60 is patterned, an anisotropic dry etching step is performed. The nitrogen silicon layer 58 and the silicon oxide layer 56 in the surface portion not covered by the photoresist layer 60 are etched away, so that the so-called spacers or side strips 54 can follow the edges of the N + type polyethyleneamine layer 46 The formation is shown in Figure 28a. If the oxide layer 39 is to be left on, for example, the lateral PNP transistor p-emitter to be formed in order to avoid silicon formation, the etching step of this nitride layer will remove the layer 56 and these Partially stop before exposure 'as shown in Figure 28b. An essential part of the process described herein for making a so-called nitrogen-silicon spacer over a thin silicon oxide layer is similar to H. Norstrom et al. No. 4,470,484. In the preferred embodiment, 'an anisotropic (ie, direction-dependent) plasma etching process is used to remove the nitrogen silicon layer. When all the nitrogen on the planar horizontal field oxide layer 18 After the silicon has been removed, the 'edge-etching' step (using the gases SF6, HBr, and 〇2) is stopped. Now that the silicon-nitrogen layer 58 has been deposited in a good and uniform manner, that is, it covers all surfaces homogeneously, here After the etching step is completed, nitrogen silicon strings and spacers remain. On the sharp class or shaded position along the plane surface produced by the laid-out N + -type polyethylenamine layer 46. Next, the thin oxide is etched with RIE silver; the layer 5 6 and then the side strip Or spacer 5 4 to get its final shape. When the n + -48- this paper size applies the Chinese standard ^ standard (CNS) A4 (210X297 mm) ------ ί i. ^ 1 n I— T ------ Elephant (please read the notes on the back before filling in this page: > A7 423079 B7 V. Description of the invention (46) Polyethyleneamine layer 46 and P + type polymer When the surface of the acetamide layer 38 is exposed, it is preferable to stop the etching process using the gas Ar'CHF3 and. Next, the photoresist layer 60 is removed by a known method. The results are shown in Figures 28a, 28b, and 31. FIG. 31 is an enlarged image showing a region where an NPN transistor is to be produced after the doping and etching of the emitter and base electrodes are completed to generate side stripes. It can be seen from this figure that the essential base region defined by the lithographic etching of the openings in the nitrogen fragmentation layer 34 and the silicon oxide layer 24 is separated by the most adjacent edge of the field oxide region 8. As described earlier in Figure 6-6, the capacitance between the collector and base in the NPN transistor to be fabricated will decrease. If necessary, after removing the photoresist layer 60, the N + -type polyethyleneimine layer 46 and P + -type polyamidamine layer 38 may have a thin hardened layer 'to reduce the impedance of the conductors in different electrode regions from those of the component to be fabricated' These conductors will be silicided from this layer To be tapped. This silicide layer may be composed of, for example, PtSi, CoSi2, or TiSi2. In the preferred embodiment, titanium disilicide TiSi2 is used, which is formed on the exposed silicon surface by a so-called "self-alignment method". Since the main body of the resistor is not exposed ', it is protected by the remaining portion of the silicon-silicon layer 58, so there will be no stone evening on it. In this type of self-aligned silicidation process ("SACICIDE") (see U.S. Pat. Nos. 4,789,995 to Briton et al. And U.S. Pat. No. 4,622,735 to 311 & 13), it is preferred to sputter the Binding · Thread--ί .— (Please read the notes on the back before filling this page) Printed by the Central Sample Rate Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperative

The size of this paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 × 297). Printed by the Consumer Cooperatives of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs ΓΛ23〇 ^ 9 a? ______ Β7 5. A thin metal layer is deposited on the surface 70 (in this example, a titanium layer with a thickness of about 50 nm), as shown in Figs. 32a and 32b, this metal layer can be exposed to the exposed temperature at an estimated temperature of about 7 丨 5 under a nitrogen atmosphere under an RT A device. The silicon reacts for a short time. In some cases, a mixture of milk and urea can also be used. Then, the titanium that has not reacted with silicon is etched away by a wet method, that is, the etched away portion of the metal before the silicon has been exposed. This selectively removes the unreacted step, which has a relatively small effect on the fragmentation. After this chemical etching process, the plane is annealed at 875 ° C for about 30 seconds' so as to form a low-resistance form of titanium disilicide. Then the silicidation layer thus produced (its surface impedance is about 2-5 ohms / square) will only appear on the silicon surface of the previously exposed plane, that is, aligned with these surfaces. After silicidation, a passive layer 80 of silicon monoxide is deposited, as shown in FIG. 3 3. The oxide layer 80 is preferably composed of a TEOS-based oxide. The oxide is formed by thermal decomposition or deposited by PECVD. The oxide layer 80 will be planarized by photoresistive etching (reB) later. The deposited thickness is about 1 μm, and then a photoresist layer (not shown) with a thickness of 1 # m (measured on a large flat surface) is applied on a flat surface. This photoresist layer is then annealed at about 1 901 for a period of time. Because of the flat surface of the photoresist, its upper surface will be relatively flat, although the topography of its lower surface is quite uneven or rough. This plane is then etched by plasma to remove the protruding or extended portion of the photoresist layer and the silicon dioxide passive layer 80 at the same speed. -50- This paper is in accordance with the Chinese National Standard (CNS) 21〇ί 297 公 #) ---------: clothing ------ iT, ----, ~ line (please read the precautions on the back before filling this page) Central Standard of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Bureau Γ 4 23〇7 9 V. Invention Description (48). After the photoresist layer is completely removed, the final result is that the surface of the passive layer 80 can obtain a uniform topography, that is, its surface It becomes very flat and horizontal. This flattening method (REB) such as AC Adams, CD · Capio in Journal of the Electrochem, Soc., Vol. 128, p. 423, 1981, "PUnarization phosphorous doped silicon-dioxide," The above-described planarized oxide layer 80 is covered with a doped oxide layer 82 having a thickness of about 400 nm. The oxide layer 82 formed of a TEOS-based oxide is preferably doped with about 4%. Phosphorus to get the so-called gettering 'so it can easily fix the diffused ions. A combination of dopants is also feasible, such as 3% boron and 60/0 scale. Next, a doped oxide layer 82 (preferably PECVD) is deposited on the doped oxide layer 82 to a thickness of about 250 nm. Oxidation layer 82. This oxide layer functions as the same as a hard mask in the later. Then this oxide layer is placed at 700. (: Annealed under nitrogen for about 40 minutes to make it denser. It can also be changed to one The RTA process is performed at about 875 seconds. This RTA process can also replace the annealing step previously performed to generate low-resistance titanium disilicide. In a preferred embodiment, the plane is then lithographically etched. Figure, thereby defining the deep matrix contacts. These contacts are made by first using an anisotropic plasma etching method to convert an applied photoresist layer 81 layout into the underlying oxide layer 84 (82 , 84), then ^ remove this photoresist layer 81 by a known method, and make a deep hole 85 about 7 am under the substrate (9, 1) by dry etching. This process is similar to- —_ -51- Dimensions of this paper --------- A ------ IT ------ ^ (Please read the precautions on the back before filling this page) Luo 42307 9 V. hair Note (49) The process described by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs when printing the trench 22 for insulation. When the etching hole 85 is in contact with the substrate, the uppermost oxide layer 84 (the so-called The hard mask) will be completely or partially consumed. The results after the etching substrate connection are shown in Figure 33. After engraving the matrix connection hole 85, the boron is implanted into the plane at a concentration of about 3 × 1015 ion / cm 2 and an energy of about 30 keV in the direction shown by the arrow in FIG. 33. The implantation energy is adjustable so that the boron atom can be blocked by the passive oxidation doped layer 82 'and it will only penetrate into the silicon matrix by first passing through the opening of the hole 8S. After the step, the plane is annealed in oxygen at substantially 875 t: for about 30 seconds. The advantages of generating and implementing a deep-based negative contact as described above in a 1C circuit process for radio frequency have been described in the international patent application PCT / SE97 / 00487. After the above implantation and annealing are completed, the plane is covered with a photoresist layer again, and the contact holes for active and passive components are patterned at this time, as shown in Figs. 34a and 34b. Anisotropic plasma etching is then used to make contact holes 86, 87 in the stacked oxide layers 82, 80. Because the depth of the contact hole is different, and because of the topological figure below, it takes a fixed time to make this last name. Therefore, depending on the topology of some connecting layers, they will be over-etched more strongly than others. After the contact hole is etched, the photoresist layer is removed in a known manner. Therefore, in this case, the contact hole 86 to the substrate and the connection between the passive and active elements (please read the precautions on the back before filling in this page) j Ding, -0. Line -52- This paper The scale uses the Chinese National Standard (CNS) A4 specification (: !! 0 X 297 mm) ---- 1423079 A7 B7 Five 'invention description (50) The contact hole 8 7 of the piece. The result is shown in Figure 3 4 a And β shown in 3 4 b. The surface can be sputter-coated with a double-layer structure or a sandwich structure. The structure of the covered structure is a layer with a bottom of about 100 nm, and its upper part is about 50. nm-thick TiN layer. In the preferred embodiment, the Ti layer is used in a so-called "ion metal plasma equipment (IMP-equipment)" (eg, 'vectra Source' 'This is a trademark of Applied Materials (Named) deposited by sputtering so that it can cover the bottom of the deep matrix contact hole 85. The TiN layer is deposited by reactive sputtering, such as completed in a mixed gas of heart and heart, it is best to use Commonly known as aiming method (also known as consistent sputtering). This TiN layer can also be deposited by In a similar manner to the Ti layer, it is achieved by the reactive base clock method using IMP Vectra Source. After the Ti contact metal layer and the nitrided metal TiN are deposited (the TiN layer can form a barrier layer for the metal layer below it), The plane is annealed at an estimated temperature, so that the Ti layer at a position with a free silicon surface thereon reacts with the underlying silicon or with titanium silicide (that is, in the contact hole for the component) (Titanium silicide reaction) In this preferred embodiment, the annealing is performed in an oven in a mixture of N2 and H2 at a temperature of about 600t: for about half an hour. It can also be performed at a higher temperature in an RTA equipment Annealing, but for a short period of time, such as under N2 or urea atmosphere. It can also be used to strengthen the barrier in the deep matrix junction _, so that the implanted boron atoms can diffuse into the matrix material. _- -53- The size of this paper is toward + ~ ^ | 家 & (CNS) Α4 · (21 〖χ297 公 ---------------- ir ------ line ί Please Read the precautions on the back before filling out this one.) Instruction for Consumer Work Cooperatives, Central Government Standards Bureau, Ministry of Economic Affairs, rd23〇79 * V. Description of the invention (51) M Fan Ji, the Central Standards Bureau employee consumer cooperative, India Fanfan, deposited a town layer of about 1 m in C VD. This deposition step can be a good uniformity, it is performed on the entire surface of the plane Therefore, all contact holes can be completely and uniformly filled with tungsten. The latter is followed by a tungsten-re-etching process to remove all tungsten on the flat (ie horizontal) portion of the plane. When this TiN When the layer is exposed, the etching process stops. This allows tungsten to remain in the contact hole and form a so-called contact plug. Next, a first conductive layer composed of TiN of about 5011111 is deposited in the same manner as described above, and is covered with an aluminum layer having a thickness of about 600 nm. This aluminum layer is formed by sputtering 'and preferably contains 0.5-2_0 ° /. Copper to suppress electron migration. The thickness of these metal layers can vary depending on the application. A TiN layer with a basic thickness of about 50 nm is deposited on the aluminum layer by a reactive base plating method to help the subsequent layout and suppress the so-called, mound, (upward bulge), and then Ti The metal layer structure composed of / TiN / ANCu / TiN is patterned by lithographic etching, and then the component connections are defined by dry etching. More metal layers can be added in this process. The method is to deposit a passive layer over the first connection layer, and then use lithography and dry money engraving to define the via connection. Next, a Ti / TiN two-layer structure is deposited according to the aforementioned sputtering method, and then tungsten is inserted into the opening of the through hole according to the aforementioned procedure. Then, a second metal layer structure composed of a TiN / Al-Cu / TiN stack is deposited by sputtering. Then -54- This paper size applies the Chinese Gardener Standard {CNS) A4 specification (210X297 male f) (please read the precautions on the back before filling this page). "9 V. Description of Invention (52 A7 B7 Ministry of Economic Affairs) The Central Standards Bureau's consumer co-operative printing method and dry name engraving method define the connection layer on it. If more, the process is repeated. The thickness of the A1 Cu layer used can be changed from several hundred ㈣ to A few "claws, depending on the complexity imposed by the metal system and the circuit. If you want to integrate a flat coil in the circuit, a multilayer metal system with a relatively thick conductive layer (such as Al-Cu) is advantageous When manufacturing a flat coil for RF-IC application, a process using several metal layers connected in parallel and disposed above the substrate divided by the trench can be found in International Patent Application No. PCT / SE9 / 0. No. 954. This known process can be used in the aforementioned process. The structure of the core after adding several metal layers is shown in Figure 35a. The upper-left corner of Figure 35a shows the manufactured planar capacitor (called `` CapDn '') ) Cross-section It consists of a single-crystal silicon layer doped with N + underneath it and a p + -type polyethyleneamine layer above the nitride dielectric layer. A lateral PNP transistor is directly located on the right side of the capacitor. Polyethyleneamine forms an emitter and a collector. Its base is formed by diffusion of N + plugs from the surface in series with the bottom diffusion layer of N + type. An NPN transistor is shown on the upper right Cross-sectional view, and the resistance generated by the type of polyacetamide " It should be understood that all the elements arranged in the silicon matrix are insulated from each other by deep trenches. The deep matrix contact holes filled with tungsten in holes 85 and The matrix connection driven by P + polyamidamine is appropriately placed between the insulation grooves 22 surrounding each element area to obtain the best possible electrolytic coupling. -55- This paper standard is common in China Standard (CNS > Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page)

* 1T A7 B7 423〇 ^ 9 * V. Description of the invention (53) It can also be seen in Figure 35a that in addition to the aforementioned tCapDn, the = capacity CapMm is integrated between the uppermost metal layers, 'in = this metal-metal capacitor The process of CapMlN uses PECVD · emulsion as the dielectric layer. This process has been adjusted for use in tungsten n-holes. The advantages of the latter capacitor manufacturer who integrated it into the entire 1st company have been described in Swedish Patent No. 97〇1618_2. Howling is shown in Figure 3 and 5b, which shows the same structure as that in Figure 353, but in which there are no grooves 22 of different components for insulation, and the surface of the circuit plane is not equal to the insulation between all parts in the structure according to Figure 35. It consists only of an embedded region 8 and a P-region or p-hole 14. In this case, 'when boron is implemented to produce the ρ_region 14, the more limited doping concentration of the above range is used, that is, about 丨 χ 丨 " ions / cm2 to obtain the P-region The electrical conductivity is sufficiently high, so that a good insulation can be obtained on the plane surface of the circuit between different element regions. When the structure shown in FIG. 35b is generated, the above steps are omitted. This step is only required when the trench 22 is generated, that is, after applying the photoresist layer 21 and making appropriate openings and dry etching to the In the hard mask, openings are created that pass downward through the polyethylene barrier layer 19 and the field oxide layer 18 (that is, within the oxide layer 20). The photoresist layer 21 is removed, the trench 22 is etched, and after the trench is etched, Do a possible implantation step to estimate the critical value of the electric field, etch the rest of the oxide layer 20, and remove the polyacetamide layer 19 > a layer deposited as single crystal silicon or polyacetamide 25, to fill the trench 22 'to etch away the silicon layer 27 -56- The decision standard is applicable to Chinese National Standard (CNS) A4 (2ΐ〇χ297 公 «) I-rut 1 ^ 1 — ^^ 1. ^ ϋ-clothing 1 I f Please read the notes on the back before filling this page} Order --- line 1 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs PA23079 V. Description of the invention (54) A7 B7, thermal oxidation The plane is oxidized with silicon 27 in the trench 22 to generate a silicon dioxide insulating layer or cap-oxide layer 28 in the trench. However, when the layer 23 is generated, the thermal oxidation of the planar surface (see FIG. 18) used to oxidize the wall of the trench 22 as described above must be performed, because in this oxidation step, the K00 oxide layer 24 is Formed on the active surface. Figure 36 < Image is a microscope image showing the resulting circuit ' In it, a deep matrix contact filled with tungsten, a polyethylenimide resistor, and an pnn transistor insulated by a trench can be seen. It can be seen from Fig. 37 that the different elements ram horizontally extend along the plane surface of the transistor, and the cross-section direction is perpendicular to the paper surface, and the transverse PN transistor has an opposite shape, in which the emitter is placed in the center. The consumer cooperation of the Central Bureau of Standards of the Ministry of Noodles Du printed 57-degree ruled paper One rate 榇 Home country 0

Ns Women 1 cm 7 9 2 (Read the notes on the back before filling in this page)

Claims (1)

9 C8 D8 2. 3. 4. Printed by the Consumer Cooperative of Shiyang Standard Vehicle Bureau of the Ministry of Economics—a kind of semiconductor component, especially a bipolar NpN transistor. A thick field surrounds one of the active areas on the surface of this component. The oxide region, as viewed from the surface of the element, is characterized in that the active region is partially covered by an electrically insulating surface layer, and a base region in the active region is lithographed by the electrically insulating surface layer. Etching defines the opening. For example, for a semiconductor device under the scope of patent application, especially a bipolar NPN transistor, viewed along the surface of the device, it can be seen that the emitter and collector regions on the surface of the device consist of thick field oxide regions. It is surrounded by a feature in which an emitter region and / or a collector region is defined by an opening defined by lithography in an electrically insulating surface layer extending through and through the surrounding field oxide region, so that a An electrical edge surface layer may exist between an individual emitter or collector region and the field oxide region closest to this region. For example, the semiconductor device according to item 1 or 2 of the patent application scope is characterized in that the electrical insulating layer includes a stack of silicon nitride and silicon oxide. A process for manufacturing a bipolar transistor, particularly an NpN transistor, in which a thick field oxide is formed on a surface of a substrate doped with a first doped pattern below a doped region. Around the edge of an opening; on the field oxide and the opening ^ a first doped pattern, especially a doped, electronic silicon layer of an N-doped layer, and a first electrically insulating layer on top of it; ^ A hole is formed in the opening to penetrate the hair 1 and the first insulating layer, so that the field hole will be set at a distance from the edge of the opening and therefore the field oxide (please read the precautions on the back before filling this page). 58 r4 230 7 9 The scope of patent application for ABCD is that the Ministry of Economic Affairs and the Central Government Office of the Ministry of Economic Affairs employee consumer cooperatives print a distance away from each other; in this opening, a second doping pattern opposite to the first doping pattern (especially refers to Mouth-type) and doped first doped pattern (especially N-type) to generate an emitter and a base; characterized in that before the conductive silicon layer and the first insulating layer are generated, a A second electrically insulating layer is applied to the field oxide and On the opening; the second electrical insulation layer 'removes the part inside the opening, so that it only remains on the edge of the opening in a stripe form; 菘 through the silicon layer and the first insulating layer 0 hole making The method is such that the hole is arranged at a general distance from the inner edge of the strip, so that another strip generated by the second insulating layer can be formed in the first-mentioned strip. For example, the process of applying for the fourth item of the patent scope is characterized in that the application of the second electrically insulating layer is firstly applying a bottom sublayer, and then an upper sublayer 'to obtain a stacked second layer. 6. The process of claim 5 in the scope of patent application, characterized in that the application of the bottom sublayer is achieved by generating a thin oxide layer on the surface. For example, the process of applying for item 5 or 6 of the patent scope is characterized in that the application of the upper sublayer is achieved by applying a nitrided layer on the surface. The process of applying for item 4 of the patent scope is characterized by doping After doping the second doping pattern and the first doping pattern, especially after K and team doping, an annealing process is performed to make the dopants from the conductive silicon layer to 5. 7. 8. 59- First read the meanings on the back and then fill out this page} The bound paper is printed from Chaosguan to CNS (21GX297 mm P4230 7 9) Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs, Masonry Consumer Cooperative«. A8 B8 C8 D8 6 1. The scope of the application for a patent is diffused to form an essential base, and is used when doping the second doping type and the first doping type (especially those obtained in? _ And Qin doping). An essential base and an essential emitter are formed in the area where the component is received. 9. The process of the fourth scope of the patent application is characterized in that when the third insulation layer is generated, this process is also applied to be used as The area of the dielectric layer in a capacitor is also located in the Doped type doped region. 10. = The process of item 9 of the scope of patent application, characterized in that when a conductive silicon layer is generated, the conductive silicon layer f is covered in a region for forming a dielectric layer. On the second insulating layer, so that the conductive silicon layer can constitute the upper electrode of the capacitor. 11. The process of item 9 or 10 of the scope of patent application is characterized in that the application of the second electrical insulating layer is firstly applying the thin part of the lower part. An oxide layer, and an upper nitride layer applied thereon, the lower oxide layer is in the region where the upper nitride layer is applied to a contact plug of a buried electrode used to form a capacitor It was previously removed.! 2 · A process for manufacturing a bipolar lateral transistor, in which the lower region of the substrate is doped with a first doped pattern on the surface, a thick field oxide, which acts as a surround An emitter and a collector are generated by the edge; Doped in the openings for the emitter and collector to a second doping type that is opposite to the first penalty; And a second doping pattern in the opening of the collector -60- (Please read the notes on the back before filling this page} Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs, 23〇79 A8 —_ group-~ ------ ^ holes, area covered by patents, and conductive connection with the first doped type below the doped consumption 1 It is characterized in that after a thick field oxide layer is generated by f and a first doping pattern is doped, an electrical insulating layer is generated on the field oxide and the opening; and the part inside the opening is made by the electrical insulating layer It is removed so that the electrical insulation layer in the opening region will only remain on the edge of the opening in a stripe form, and then the opening is doped with a second doping type. 13. The process of item 12 of the patented patent park is characterized in that the doping of the second doping pattern in the opening is obtained by diffusing the dopant from the conductive connection line outward. For example, the process of claim 12 is characterized in that the application of the electrical insulating layer is firstly achieved by applying a lower sublayer and then an upper sublayer, so that a stacked second layer can be obtained. 15. The process of claim 14 in the scope of patent application is characterized in that the application of the lower sublayer is achieved by a thin oxide layer on the surface. 16. The process of claim 14 or 15 is characterized in that the application of the upper sub-layer is achieved by applying a nitrided layer on the surface. 17. A capacitor on the surface of a substrate, characterized in that: a dielectric layer is disposed on a portion of a substrate surface; a conductive layer is disposed on the dielectric layer to form one of the capacitors Electrodes; and a conductive connection, which is the part of the substrate that is not covered by the dielectric layer. -61-This paper applies the standard of China Standard < CNS), 8 and 4 (2 丨 0X297 mm)- -------- 衣 ------ tr ------ ^ (Jing first read the precautions on the back and then fill out this page) 9 " VI. Patent Application Scope Configuration to the dielectric On the area below the layer. 18. The capacitor according to item 17 of the scope of patent application, characterized in that the capacitor is placed on a doped region of the base, and the region also includes the surface of the substrate portion where the conductive connection is arranged. 19. The capacitor in the scope of patent application No. 17 is characterized in that the dielectric layer is a silicon nitride layer. 20. = The capacitor in the scope of patent application No. 17 is characterized in that the dielectric layer is disposed in a buried state. A highly-doped contact plug is formed from a surface in the part of the matrix that is not covered by the dielectric layer on the highly doped region. 21. The capacitor according to item 20 of the patent application is characterized by an electrode plug having a high connection to form a bottom electrode of the capacitor, and the electrode plug is connected from the lower side of the dielectric layer to the buried type. Highly doped regions extend. 22. —A manufacturing process for manufacturing a capacitor on the surface of a substrate, characterized in that: a dielectric layer is added to one of the surfaces of the substrate; (Please read the precautions on the back before filling out this page) — A conductive layer is added to the dielectric layer to form an electrode of the capacitor: it is conductively connected to the area below the dielectric layer. It is formed by the substrate The surface of the portion not covered by the dielectric layer is arranged. 23. For example, the process of claim 22 is characterized in that a layer with a doping is disposed on the surface of the substrate before the dielectric layer is applied, and then the dielectric layer is disposed on the substrate. The upper part of the doped layer, and visit -62- A8 B8 C8 D8 Liao 4 2 3 ◦ 7 _________ The scope of patent application for the conductive connection is configured from the surface of the doped layer. The process according to item 22 of the patent scope is characterized in that when the dielectric layer is applied, it is applied in the form of a nitrogen stone layer. For example, the process of item h in the scope of patent application is characterized in that, before applying the dielectric layer, a -buried, highly doped region is generated on the surface of the substrate, and this region is a distance from the surface of the substrate. It is located below the bit surface to which the dielectric layer is to be applied. 'Next, a highly doped contact plug is created from the surface of the substrate portion on which the dielectric layer will not be applied. 26. The system of claim 25 is characterized in that before applying the dielectric layer, a highly doped electrode plug is generated to form the bottom electrode in the capacitor. The electrode plug is made of a substrate. A portion of the surface (on top of the portion where the dielectric layer is to be formed) extends onto the buried, highly doped region. 27. A process for creating a free area on the surface of a substrate, the area being constrained by the edges of an electrically insulating layer (especially a nitride layer), characterized in that 'a layer of material is applied to A surface above the first area for forming the free area: °° A first oxide layer is uniformly applied to the material layer; an opening is made through the first oxide layer and the material layer, and reaches down to 唁On the surface of the substrate, the opening is slightly larger than the first region, and has a substantially vertical edge, so that the edge of the opening and the adjacent edge of the first region are at a substantially constant distance; 63 This paper scale is applicable to China National Ladder Standard (CNS) A4 is now available (210 X 297 mm). Clothing 1T -------- line ____ (please read the notes on the back before filling in this tile) Staff of the Central Government Bureau of the Ministry of Economic Affairs Consumption cooperation Du printed Γ 4 2 3 ο 7 9 AS Β8 C8 D8 'Please request the patent scope Employees of the Central Standards Bureau of the Ministry of Economic Affairs Consumer Cooperation 衽 Printing will apply another type of electrical insulation layer different from the oxide layer On the entire surface; A second oxide layer having characteristics different from the first oxide layer is uniformly applied to the entire surface of the electrically insulating layer; θ performs a first anisotropic etching to remove only the substantially flat, horizontal surface A second oxide layer, thereby exposing the electrically insulating layer to the surfaces, and the side strips of the second oxide layer are retained on the vertical surface; a first etching is performed to remove only the second oxide The electrically insulating layer on the surface covered by the layer, so that only the electrically insulating layer on the flat, horizontal surface is removed. The fact that the etching characteristic of the second oxide layer is different from that of the first oxide layer is used. Carry out the third surname engraving to remove only the remaining part of the second layer = that does not collide with the free surface portion of the first oxide layer, so that only a small portion of the galvanic insulating layer will remain. On the material layer and on the vertical edges of the first halide layer surrounding the first area. 28. The process of claim 27, wherein the material layer includes a conductive material layer, and at least a portion close to the first area is in electrical contact with the surface of the substrate. 29. The process of claim 28, characterized in that the conductive material layer forms all thicknesses of the material layer on its vertical edges. 30. Two processes for generating a free area on the surface of a substrate, the substrate having a vertical portion on the edge of the free area, which is characterized in that a first electrical insulating layer is first uniformly applied to the substrate. On the surface, please read it first * i I, then fill in this page to order • Silver 64- A3 B8 C8 D8 '423079-* ---- The scope of the patent application applies the second electrical insulation layer to the surface of the first layer. The materials of these layers are selected so that they have different etching characteristics. f. Selectively etch down to remove the substantially vertical portions first :::::: all the first and second layers, and then also remove the 31 · = patent scope item 3Q H, which is characterized by the 1 is formed in two steps. In the first step, only the second step on the horizontal part is removed. In the second step, it is only the first step on the horizontal surface part. Was removed. 32. A side strip structure on the active region on the surface of a doped substrate, which is characterized in that the arrangement of the lead-through substrate is in contact with the boundary region of the active region and the electrical insulating layer is essentially uniformly arranged only on the conductive silicon The partial vertical surface portion is thereby used to make the electrical insulating layer substantially the same thickness everywhere. 33. For example, the sidebar structure of item 32 of the patent scope is characterized in that-an insulating oxide layer is substantially disposed on the entire surface of the conductive silicon layer and under the electrically insulating layer. 34. The sidebar structure of item 32 in the scope of patent application, characterized in that the electrical insulation layer is a silicon silicon layer. 35. A process for making a transistor on the surface of a substrate, wherein. A conductive layer is added over the surface to make contact with the doped region on the surface, and then the electrical insulating layer is directly applied over the conductive second layer, and another conductive layer is added over the insulating layer. Next, remove the electrically insulating layer in the area not covered by this additional conductive layer -65-From the applicable TSIBI family standard rate (CNS) from the secret (2 敝 plus public) Nong -------- ( Please read the notes on the back first and then fill out the lettuce page) Sheet of paper I__ A copy printed by the Ningyang Standards Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives 14 2 3 Ο 7 9 The employee consumer cooperative prints / retains electrical contact with the subsequently applied conductive metal layer and is characterized in that only the electrically insulating layer in the selected area is removed. 36. The process of claim 35 in the patent application park, characterized in that when the removal step is performed, 'applying a mask with openings made by lithographic etching thereon' so that the rest of the mask can cover the previously applied mask Selected areas of the insulating layer and areas that are prevented from being silicified when the electrical insulating layer is subsequently applied, so that after the removal step is completed, these layers will still be covered by the insulating layer. 3-input—a kind of integrated circuit, comprising elements on the surface of a substrate, characterized in that each element is essentially generated in a manner that is structured on the N-doped region of the surface layer of the substrate, and is buried An in-fill, highly doped region is located below and in the matrix and has the same doping pattern as the region above it, contacts the doped region with the bottom, and there is ρ in the surface layer of the matrix between the elements The doped region has a buried region with the same doping pattern as the upper region as a contact between the region and the substrate, thereby obtaining lateral electrical insulation of the element. 38. = The integrated circuit of item 37 of the scope of patent application is characterized in that a good conductive layer is arranged above the P · doped region in the surface layer of the substrate, and this layer is used to connect to the electrical ground plane. 39_ A process for manufacturing an integrated circuit that includes components on the surface of a substrate is characterized in that a first region having the same surface layer as that of the substrate is made on the first region of the component to be fabricated. A doped area of the doped type, please note first with the same type. 2 Side-66-Α4 grid (210x297 mm) A8 B8 C8 D8 423079 6. The area of the patent application area is located below it. Heterotype pattern of doped area contact: and ... million, and have-doped ===== make a doped region, this region is connected to the next, its doped pattern is the same as the region above it. Zone 'so that it is in electrical contact with the substrate, thereby allowing the element to be laterally electrically insulated. The process of item 39 is characterized in that the doping is performed so that the second dopant enters the substrate. After the surface layer is added, a conductive layer is added to the surface to connect it to the electrical ground. 41_ = The process of applying for the scope of patent application No. 40, which is characterized in that the good conductivity is-a highly doped layer doped with the second doping type, Ϊ = layer, subjected to -annealing operation, so that the dopants pass through it Diffusion into a doped region with a second doping in a base layer and a surface layer to reduce the impedance between the conductive layer and the doped region with the second doping The components placed on the surface of the substrate are connected to the Central Quasi Bureau of the Ministry of Economic Affairs and printed by the Industrial Cooperative, creating a deep hole and filling it with a conductive material (preferably a metal). Prior to the conductive material, a doping is performed at the bottom of the deep hole to reduce the impedance between the conductive material and the substrate. 43, if the process of applying for the scope of the patent No. 42 is characterized in that the impurity is implanted and then annealed to diffuse the implanted atoms -67- The standard of this paper is applicable to China ’s national standard (CNS & gt A4 specification (2! OX297 public; §) A8 B8 C8 D8 4230 7 9 'The scope of patent application was reached. 44. If the process of applying for the scope of patent item 43 is characterized in that the implantation step is implanted with boron 45. If the process of applying for the scope of patent No. 42 is characterized in that after the doping step is completed, a thin layer containing titanium is added to the wall and bottom of the deep hole. The process is characterized in that after applying to at least one thin layer, an annealing operation is performed to form a silicide on the boundary surface between the at least one thin layer and the substrate. It is characterized in that the at least-thin layer of gadolinium is formed as the first layer of gadolinium, and a thin gadolinium nitride layer is formed above it. 48-a matrix connection for a semiconductor element arranged on a substrate surface , Which has A deep hole is filled with a conductive material (especially a metal), and is characterized in that a bottom doped with the deep hole is disposed in the substrate to reduce the impedance between the conductive material and the substrate. 49. For example, applying for a patent The matrix connection of item 48 is characterized in that the doping contains implanted boron atoms. Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 50. If the matrix connection of item 48 of the patent application is characterized by at least one A thin layer of titanium is provided on the wall and bottom of the deep hole between the substrate and the conductive material. 51_ ^ The patent application No. 50 substrate connection, characterized in that the at least one thin layer includes the at least one thin layer and Silicide on the surface of the boundary between the substrates. -68- This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm 423079¾) 6. Scope of patent application Bipolar formed on the surface of a semiconductor plane The device includes an electrically insulating layer which at least partially surrounds the active area on the surface of the device '(and is filled with an electrically insulating or semi-electrically insulating material, which is characterized by The electrically insulating material or semi-electrically insulating material is directly in the trench; the soil contains an oxide layer and a nitride layer thereon, and the main blade of the trench is filled with a uniform or homogeneous electrically insulating or semi-insulating material. Electrical insulation materials, 53, such as the bipolar device of the 52th scope of the patent application, characterized in that the homogeneous or homogeneous electrical insulation material or semi-electrical insulation material essentially contains undoped fragments, preferably Microcrystalline fragments. 54_ If the patent application scope is 52 or 53 'Bipolar device, it is characterized in that the uniform or homogeneous electrically insulating material or semi-electrically insulating material is an electronic semi-insulating material, and There is another oxide layer between the electrically insulating material and the nitride layer. 55. The bipolar device 'according to item 52 of the scope of the patent application is characterized in that the uniform or homogeneous electrically insulating material or semi-electrically insulating material contains oxidized sand. 56. —A process for manufacturing a bipolar element on the surface of a semiconductor plane 'includes the following steps: Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs to produce an electrically insulating trench, a portion of which surrounds the element Active area on the surface; filling the trench with an electrically insulating material or semi-electrically insulating material: characterized in that the step of filling the trench is achieved by the following steps: applying an oxide layer on the wall of the trench; A nitride layer is applied on the oxide layer; -69- The standard of this paper is t S national standard (called eight 4th (2 丨 0 parent 297 public director) glue 42307 Q A8 η C8 D8 'Scope of patent application = one uniform Sentence or homogeneous electrically insulating or semi-electrically insulating material fills the rest of the trench. 57. = The process of applying for item 56 of the scope of patent application is characterized by the homogeneous or homogeneous electrically insulating material When filling with semi-electrically insulating materials, a substantially undoped silicon, preferably single crystal silicon, is used. 8. The process of item 56 or 57 of the patent application scope is characterized by a uniform or Homogeneous electrically insulating material or When filling the electrically insulating material, half of the electrically insulating material is used, and the semi-electrically insulating material is filled with the semi-electrically insulating material as before, and an oxide layer is first applied on the nitrided layer. For example, the process of applying for the scope of patent application No. 56 features The reason is that when filling the other main parts of the trench, use silicon oxide as the uniform or homogeneous electrical insulation material. (Jingxian first read the precautions on the back and then fill out this K) t Ministry of Economy _ 阳 榡 率 局Printed by Employee Consumer Cooperatives 70-