4230 6 5031twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（/ ) 本發明是有關於一種電晶體（Transistor)的製造方法與 結構，且特別是有關於一種具有金屬閘極(Metal Gate)與高 介電常數（High Dielectnc Constant)閘極介電層之電晶體的 製造方法與結構。 尺寸縮小是半導體元件的製造趨勢，爲符合此製造 趨勢，不僅傳統的製程技術必須精進，許多慣用的材料也 必須更換。 以電晶體的製造爲例’傳統最常使用的閘極介電層， 是利用熱氧化法所形成之氧化矽層，而爲維持元件可接受 之短通道效應（Short Channel Effect) ’以及汲極(Drain)電流 的最大化’其所使用的厚度已約略降至40埃(六邱山,〇111) Q 然而，對於以超薄氧化層做爲閘極介電層的元件而 s ’其可能於聞極介電層中產生咼閘極漏電流，爲解決此 問題’具有_介電常數之介電層’成了眾所矚目的鬧極介 電層材料。 另外，胃尺寸約略低於400平方公詹的元件而言，聞 極的片電阻値(Sheet Resistance)必須約略低於每平方單位5 歐姆_ ) ’才能符合字元線(W〇rd Lme)的延遲約略在2 奈秒（Nano Second，ns)以內的限制。 一*幸的是，雖然傳統閘極軸用的導電材料，是粗 元件製造流程相容性較佳_晶砂材料，但 _ ==不能達到前述的要求’因此使用金屬做爲聞極 的導電材料，成了兀件尺寸縮小的η 日0另〜項必須改變的製 程。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公$ ) (請先閱讀背面之注意事項再填寫本頁) 裝-------—訂·- -------線· 423061 5031twf,doc/006 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（2) 一般具有金屬閘極與高介電常數閘極介電層之電晶 體的製造流程，係在閘極定義之後，才形成源極區（Source Region)與汲極區（drain Region)，而形成源極區與汲極區所 使用的方法，係先以閘極爲罩幕（Mask)，進行一離子佈植 製程（bn Implanuition)，而後再進行一高溫退火製程，以達 到摻質（Dopant)均勻化的目的。 然而，由於使源極區與汲極區中之摻質均勻化的温 度需要極高，因此容易造成金屬閘極的可靠度（Reliability) 發生問題。 因此本發明提供一種電晶體的製造方法與結構，藉 由假閘極（Dummy Gate)的使用，以使源極區及汲極區在金 屬閘極形成前便已完成，以解決金屬閘極與習知製造流程 無法相容的缺點。 本發明提出一種電晶體的製造方法，包括提供一基 底，首先形成一具有高介電常數之第一介電層覆蓋此基 底，接著形成一氧化層覆蓋此具有高介電常數之第一介電 層，然後形成一氮化矽層覆蓋此氧化層，接著定義此氮化 矽層、氧化層與具有高介電常數之第一介電層，以形成一 假閘極結構，然後形成一間隙壁於此假閘極結構的側壁， 再進行一離子佈植製程與一高溫退火製程，以在基底中形 成一源極區與-汲極區，接著形成一與假閘極結構約略等 高度的第二介電層於間隙壁的兩側，然後去除假閘極結構 中之氮化矽層，接著進行一氮化製程，以將氧化層轉換成 一氮化層，然後形成一金屬阻障層覆蓋第二介電層、間隙 4 <請先閱讀背面之注意事項再填寫本頁) ---- 訂---------線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ；4 2 3 0 6 1 5031twf.doc/006 經濟部智慧財產局員工消費合作社印製 五、發明說明（^) 壁與氮化層，再形成一金屬層覆蓋金屬阻障層，以及，對 金屬層與金屬阻障層進行一平坦化製程，以形成一金屬鬧 極’此金屬鬧極的商度與第^介電層的局度約略相等。 本發明同時提出一種電晶體的結構，包括一基底， 一閘極，形成於基底的表面，此閘極包括：一具有高介電 常數之第一介電層，形成於基底的表面，一氮化層，形成 於具有高介電常數之第一介電層的表面，一間隙壁，形成 於基底的表面，並位於具有高介電常數之第-介電層與氮 化層的兩側，此間隙壁的高度高於具有高介電常數之第一 介電層與氮化層的高度，一金屬阻障層，形成於氮化層與 間隙壁的表面，以及，一金屬層，形成於金屬阻障層的表 面，此金屬層約略與間隙壁具有相等的高度；以及，一第 二介電層，形成於閘極的兩側，此第二介電層與金屬層及 間隙壁約略具有相等的高度。 本發明係先形成由具有高介電常數之介電層、氧化 層與氮化矽層依序堆疊而成的假閘極結構，再以此假閘極 結構爲罩幕，進行一離子佈植製程與一高溫退火製程，以 形成元件之源極區及汲極區，接著將此假閘極結構中的氮 化矽層去除，之後進行一氮化製程，以使假閘極結構中之 氧化層氮化，再於此假閘極結構因氮化矽層去除而空出的 空間中，塡入一金屬阻障層與一金屬層，以形成金屬閘極。 本發明係藉由假閘極的使用，以使源極區及汲極區 在金屬閘極形成前便已完成，因此形成源極區及汲極區所 需要的高溫退火製程，不會在金屬閘極形成之後進行，進 (請先閱讀背面之注意事項再填寫本頁) .^1 ί t n it ft tt *t« 訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 1 4 230 6 1 A7 5031twf.doc/006 _______B7_ 五、發明說明（羊） 而維持了金屬閘極的可靠度。 本發明所揭露之電晶體閘極，係以具有高介電常數 之介電層做爲閘極介電層，因此在元件尺寸縮小的趨勢 下，可抑制可能於閘極介電層中產生之高閘極漏電流= 本發明所揭露之電晶體閘極，係使用片電阻値較低 之金屬做爲導電材料，因此在元件尺寸縮小的趨勢下，可 降低字元線的延遲。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1A至1G圖係繪示依據本發明較佳實施例之一種 具有金屬閘極與高介電常數之閘極介電層之電晶體製造流 程結構剖面示意圖。 圖式之標記說明： 100 :基底 l〇〇a :隔離結構 100b :源極區 100c :汲極區 102、102a :具有高介電常數之介電層 104、104a :氧化層 l〇4b :氮化層 106、106a :氮化砂層 108 :假閘極結構 (請先閱讀背面之注意事項再填寫本頁) 裳------ 11111 線· 本紙張尺度適用中困國家標準（CNS>A4規格（210 X 297公釐） 423061 A7 B7 ---^ 經濟部智慧財產局員工消費合作社印製 五、發明說明（5) lio :間隙壁 112:假閘極 — 1 14 :介電層 116、116a :金屬阻障層 118、118a :金屬層 120 :金屬閘極 第1A至1G圖係繪示依據本發明較佳實施例之一撞 具有金屬鬧極與局介電吊數之聞極介電層之電晶體製造流 程結構剖面示意圖。 請參照第丨A圖，首先依序形成一具有高介電常數之 介電層102、一氧化層104與一氮化矽層1〇6覆蓋基底100。 其中基底100已形成有隔離結構100a，此隔離結構100a 譬如是淺溝渠隔離結構(Shallow Trench Isolation，STI)。 而具有高介電常數之介電層102所使用的材料，譬如 是介電常數値約略爲25的五氧化二鉅（Tantalum Oxide， Ta2Cg，氧化層104所使用的材料，譬如是高溫氧化矽(Hlgh Temperature Oxide，HT0)，形成此具有高介電常數之介電 層102及氧化層104所使用的方法，譬如是化學氣相沉積 法（Chemical Vapor Deposition，CVD)。 請参"照第1B圖，接著進行一微影触刻製程，以定義 出具有高介電常數之介電層102a、氧化層i〇4a與氮丨匕石夕 層l〇6a堆疊而成的假閘極結構1〇8。 然後形成一間隙壁(Spacer)llO於假閘極結構ι〇8的側 ! φ it 訂 線 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公釐） 4230 6 5 0 3 1 14230 6 5031twf.doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (/) The present invention relates to a method and structure for manufacturing a transistor (Transistor). Method and structure for manufacturing a transistor of a metal gate and a high dielectric constant (Dielectric Constant) gate dielectric layer. Reduction in size is the manufacturing trend of semiconductor components. In order to comply with this manufacturing trend, not only must traditional process technology be refined, but many conventional materials must also be replaced. Take the manufacture of transistors as an example. 'The traditional gate dielectric layer most commonly used is a silicon oxide layer formed by thermal oxidation to maintain the short channel effect acceptable to the device' and the drain electrode. (Drain) Maximizing the current 'The thickness used has been reduced to approximately 40 Angstroms (Liu Qiushan, 〇111) Q However, for components using an ultra-thin oxide layer as the gate dielectric layer, it's possible In order to solve this problem, a 'dielectric layer with a dielectric constant' has become a material of attention. In addition, for components with a stomach size of slightly less than 400 square centimeters, the sheet resistance of the smell pole (Sheet Resistance) must be approximately less than 5 ohms per square unit. ) The delay is approximately limited within 2 nanoseconds (Nano Second, ns). Fortunately, although the conductive material used in the traditional gate shaft is compatible with the rough component manufacturing process _ crystal sand material, but _ == can not meet the aforementioned requirements' Therefore, the use of metal as the conductivity of the smell pole The material has become the manufacturing process of reducing the size of the components. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 $) (Please read the precautions on the back before filling this page). ------------ Order ------- -Line · 423061 5031twf, doc / 006 A7 B7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (2) The manufacturing process of transistors with metal gates and high-k gate dielectrics. The source region and drain region are formed after the gate is defined. The method used to form the source region and drain region is to first mask the gate. An ion implantation process (bn Implanuition) is performed, and then a high-temperature annealing process is performed to achieve the purpose of uniform dopant. However, since the temperature for homogenizing the dopants in the source region and the drain region needs to be extremely high, it is easy to cause problems with the reliability of the metal gate. Therefore, the present invention provides a method and a structure for manufacturing a transistor. By using a dummy gate, the source region and the drain region are completed before the metal gate is formed to solve the metal gate and the Know the disadvantages of incompatible manufacturing processes. The invention provides a method for manufacturing a transistor, which includes providing a substrate, firstly forming a first dielectric layer with a high dielectric constant to cover the substrate, and then forming an oxide layer to cover the first dielectric with a high dielectric constant. Layer, and then forming a silicon nitride layer to cover the oxide layer, and then defining the silicon nitride layer, the oxide layer, and the first dielectric layer having a high dielectric constant to form a dummy gate structure, and then forming a gap wall An ion implantation process and a high-temperature annealing process are performed on the side wall of the dummy gate structure to form a source region and a -drain region in the substrate, and then a third region approximately equal to the height of the dummy gate structure is formed. Two dielectric layers are on both sides of the gap wall, then the silicon nitride layer in the dummy gate structure is removed, and then a nitridation process is performed to convert the oxide layer into a nitride layer, and then a metal barrier layer is formed to cover the first Second dielectric layer, gap 4 < Please read the precautions on the back before filling this page) ---- Order --------- Line-This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm); 4 2 3 0 6 1 5031twf.d oc / 006 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (^) Walls and nitride layers, and then a metal layer is formed to cover the metal barrier layer, and the metal layer and metal barrier layer are flat Chemical process to form a metal alarm, the discussion of this metal alarm is approximately equal to the local dielectric layer. The invention also provides a transistor structure including a substrate and a gate formed on the surface of the substrate. The gate includes a first dielectric layer having a high dielectric constant, formed on the surface of the substrate, and a nitrogen layer. The formation layer is formed on the surface of the first dielectric layer having a high dielectric constant, a spacer is formed on the surface of the substrate, and is located on both sides of the first dielectric layer and the nitride layer having a high dielectric constant, The height of the spacer is higher than the height of the first dielectric layer and the nitride layer having a high dielectric constant. A metal barrier layer is formed on the surfaces of the nitride layer and the spacer, and a metal layer is formed on On the surface of the metal barrier layer, the metal layer is approximately the same height as the spacer; and, a second dielectric layer is formed on both sides of the gate, and the second dielectric layer is approximately the same as the metal layer and the spacer. Equal height. The invention first forms a dummy gate structure formed by sequentially stacking a dielectric layer, an oxide layer and a silicon nitride layer with a high dielectric constant, and then uses the dummy gate structure as a mask to perform an ion implantation. Process and a high-temperature annealing process to form the source region and the drain region of the device, and then remove the silicon nitride layer in the dummy gate structure, and then perform a nitriding process to make the oxide layer in the dummy gate structure Nitriding, and inserting a metal barrier layer and a metal layer into the space vacated by the dummy gate structure due to the removal of the silicon nitride layer to form a metal gate. The invention uses the use of a dummy gate so that the source region and the drain region are completed before the metal gate is formed. Therefore, the high temperature annealing process required to form the source region and the drain region is not performed on the metal. After the gate is formed, proceed (please read the precautions on the back before filling this page). ^ 1 ί tn it ft tt * t «Order --------- The paper size of the paper applies Chinese national standards ( CNS) A4 size (210 x 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 4 230 6 1 A7 5031twf.doc / 006 5. Description of the invention (sheep) The reliability of the metal gate is maintained. The transistor gate disclosed in the present invention uses a dielectric layer having a high dielectric constant as the gate dielectric layer. Therefore, under the trend of the reduction in the size of the device, it is possible to suppress the generation of the potential in the gate dielectric layer. High gate leakage current = The transistor gate disclosed in the present invention uses a metal with a lower sheet resistance 做 as a conductive material, so the word line delay can be reduced under the trend of shrinking component size. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: 1A to 1G A schematic structural cross-sectional view of a manufacturing process of a transistor having a metal gate and a high dielectric constant gate dielectric layer according to a preferred embodiment of the present invention is shown. Explanation of the marks of the drawings: 100: substrate 100a: isolation structure 100b: source region 100c: drain regions 102, 102a: dielectric layers 104, 104a with high dielectric constant: oxide layer 104b: nitrogen Chemical layers 106, 106a: Nitrided sand layer 108: Fake gate structure (please read the precautions on the back before filling this page). -------- 11111 line · This paper standard is applicable to the national standard of difficulty (CNS > A4 Specifications (210 X 297 mm) 423061 A7 B7 --- ^ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) lio: partition wall 112: false gate — 1 14: dielectric layer 116, 116a: metal barrier layer 118, 118a: metal layer 120: metal gate. Figures 1A to 1G show a dielectric with a metal electrode and a local dielectric hanging number according to one of the preferred embodiments of the present invention. A schematic cross-sectional view of the structure of a transistor manufacturing process. Referring to FIG. 丨 A, a dielectric layer 102, an oxide layer 104, and a silicon nitride layer 106 covering a substrate 100 are sequentially formed in order. The substrate 100 has been formed with an isolation structure 100a. The isolation structure 100a is, for example, a shallow trench isolation structure (Shallow Tr ench Isolation (STI). The material used for the dielectric layer 102 having a high dielectric constant, such as the material used for the Tantalum Oxide (Ta2Cg, Ta2Cg, oxide layer 104) having a dielectric constant 値 approximately 25, For example, Hlgh Temperature Oxide (HT0), a method used to form the dielectric layer 102 and the oxide layer 104 with a high dielectric constant, such as Chemical Vapor Deposition (CVD). Please Refer to FIG. 1B, and then perform a photolithography process to define a stack of a dielectric layer 102a, an oxide layer 〇4a, and a nitrogen 丨 stone layer 106a with a high dielectric constant. False gate structure 108. Then a spacer (Spacer) 110 is formed on the side of the false gate structure ι0! Φ it Alignment This paper size applies to China Solid State Standard (CNS) A4 (210 X 297) Centimeter) 4230 6 5 0 3 1 1
形成 五、發明說明（0) 壁’此間隙壁11〇與假閘極結構 112,宜中，間胳、日* ^ «可口彳冉爲〜假閘極 的材料譬如是氧化砂，I 形成方法言如是先形成一介電層圖 龃其宙不）覆盍假閘極結構 —/、基底 然後再以—回蝕刻（Etch Back)製P p考 盖在基底100表面之介電層去除。 壬寸, 與接者’在基底_中形成源極區l〇〇b 〃 ΠΠ C，形成此源極區100b與汲極區1〇() 的方法:譬如是以假_112爲罩= 行一離子佈植製程與一高溫退火製程。 請參照第]D圖，然後在假閘極U2的兩側 與假閘極112約略等高度的介電層il4。Formation 5. Description of the invention (0) The wall 'this gap wall 11 〇 and the false gate structure 112, Yizhong, Jian, Japan * ^ «delicious delicious ~ the material of the false gate such as oxide sand, I formation method If a dielectric layer pattern is first formed, the structure of the dummy gate is not covered. The substrate is then removed by an Etch Back (Pt) method. Ren inch, and the receiver 'to form the source region 100b Π Π C in the substrate_, the method of forming the source region 100b and the drain region 10 (): for example, using false_112 as a mask = line An ion implantation process and a high temperature annealing process. Please refer to FIG. D, and then the dielectric layer il4 of approximately the same height as the dummy gate 112 on both sides of the dummy gate U2.
此介電層1M所使用的材料譬如是氧化矽，其形成方 法譬如是先以化學氣相沉積法，形成一介電層（圖未示）覆 蓋假閘極112與基底100，然後進行一平坦化製程 (Planarizaticn)，將高度高於假閘極112之介電層去除D 此平坦化製程譬如是使用化學機械硏磨_手呈 (Chemical Mechanical Polishing，CMP)，以假閘極 ία 中之 氮化砂層106a爲硏磨終止層（P〇丨丨shing Stop Layer)，將高 度高於假閘極Π2之介電層硏磨去除。 其中，化學機械硏磨製程所使用的硏漿（SlUrry)，譬 如是氧化砂對®化矽的硏磨選擇比約略大於30的硏漿， 以確保硏磨進行時’可準確偵測到飾刻終點(EndP〇int)。 請參照第1E圖，接著將假閘極112中之氮化砂層106a 去除，此時氧化層104a做爲蝕刻終止層，以避免高介電 ----I I ----In 裝-- ----訂 * --------線 (請先閱讀背面之注意事項再填寫本頁) 濟 部 智 慧 財 產 局 員 工 消 費 合 作 杜 印 製 丨本紙張尺度適用“國家^^規格⑵0 ·公爱) 經濟部智慧財產局員工消費合作社印製 L4 2 3U 61 -〇3itwf.doc/006 A7 _____B7___ 五、發明說明（q) 常數之介電層l〇2a受蝕刻之損傷，然後對暴露出之氧化 層104a進行一氮化(Nitridation)製程，以將氧北層丨〇4a轉 變成氮化層】〇4b’此氮化層l〇4b譬如是氮氧化矽層⑸hc〇n Oxynitride，Si〇N)或氮化矽層。 其中，去除氮化矽層106a所使用的方法，譬如是濕 式會虫刻法，而氮化製程譬如是在氨（Ammonia，ΝΗ;)氣氛的 環境中進行。 請參照第1F圖’接著依序形成—金屬阻障層(MeUl Barrier Layer) 116與一金屬層118 ’覆蓋介電層114、間隙 壁110與氮化層l〇4b。 其中’金屬阻障層116所使用的材料，譬如是氮化鈦， 其形成方法譬如是使用濺鍍法（Sputtering)，而金屬層118 所使用的材料則譬如是鎢（Tun2sten，W)，其形成方法譬如 是使用化學氣相沉積法。 請參照第1G圖，然後進行~平坦化製程，將覆蓋於 介電層1M表面之金屬阻障層Π6與金屬層ία的部分去 除，只在約略等高於介電層114的表面以下，留下部分的 金屬阻障層116a與金屬層U8a，以形成與介電層114約 略等高度的金屬閫極120。 此平坦化製程譬如是以介電層114爲硏磨終止層，進 行一化學機械硏磨製程。 接下來的製程爲熟習半導體元件製造之技藝者所能 輕易達成，故此處不再贅述。 本發明係先形成由具有商介電常數之介電層、氧化 9 W尺度構準(CNS)A4規格(210 x 297公釐) .----^--I------ ^ ills — ^« — 11---! -^ ! (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4230 St - 1 AJ 5031twf . doc/ 0 06 _ B7 五、發明說明（分） 層與氮化矽層依序堆疊而成的假閘極結構，再以此假閘極 結構爲罩幕，進行一離子佈植製程與一高溫退火製程，以 形成元件之源極區及汲極區，接著將此假閘極結構中的氮 化矽層去除，之後進行一氮化製程，以使假閘極結構中之 氧化層氮化，再於此假閘極結構因氮化矽層去除而空出的 空間中，塡入一金屬阻障層與一金屬層，以形成金屬閘極。 本發明係藉由假閘極的使用，以使源極區及汲極區 在金屬閛極形成前便已完成，因此形成源極區及汲極區所 需要的高溫退火製程，不會在金屬閘極形成之後進行，進 而維持了金屬閘極的可靠度。 本發明所揭露之電晶體閘極，係以具有高介電常數 之介電層做爲閘極介電層，因此在元件尺寸縮小的趨勢 下，可抑制可能於閘極介電層中產生之高閘極漏電流。 本發明所揭露之電晶體閘極，係使用片電阻値較低 之金屬做爲導電材料，因此在元件尺寸縮小的趨勢下，可 降低字元線的延遲。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所際定者爲準。 -! — Γ1-------农.！-----訂--lull--線 <請先閱讀背面之注意事項再填寫本頁) I 〇 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公釐）The material used for the dielectric layer 1M is, for example, silicon oxide, and a method of forming the dielectric layer 1M is to first form a dielectric layer (not shown) to cover the dummy gate 112 and the substrate 100 by chemical vapor deposition, and then perform a flat Planarizaticn, which removes the dielectric layer that is higher than the dummy gate 112. This planarization process, for example, uses chemical mechanical polishing (Chemical Mechanical Polishing, CMP) to fake the nitrogen in the gate α. The sanding layer 106a is a honing stop layer, which hones and removes the dielectric layer having a height higher than that of the dummy gate Π2. Among them, the slurries used in the chemical mechanical honing process (SlUrry), for example, honing slurry with a ratio of honing of silicon oxide to siliconized silicon greater than about 30, to ensure that the engraving can be accurately detected during honing. End point. Please refer to FIG. 1E, and then remove the nitrided sand layer 106a in the dummy gate 112. At this time, the oxide layer 104a is used as an etching stop layer to avoid high dielectric ---- II ---- In package-- --- Order * -------- line (please read the notes on the back before filling this page) Printed by the consumer cooperation of the Ministry of Economic Affairs of the Ministry of Economic Affairs 丨 This paper is applicable to the "national ^^ specifications ⑵ 0 · Public Love) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs L4 2 3U 61 -〇3itwf.doc / 006 A7 _____B7___ V. Description of the Invention (q) The constant dielectric layer 102a was damaged by etching, and then exposed to The oxide layer 104a is subjected to a nitritization process to convert the oxygen north layer 〇04a into a nitride layer] 〇4b 'This nitride layer 104b is, for example, a silicon oxynitride layer ⑸hcox Oxynitride, Si. N) or a silicon nitride layer. The method used to remove the silicon nitride layer 106a is, for example, a wet intaglio method, and the nitridation process is performed in an ammonia (NH) atmosphere. Please refer to FIG. 1F 'Sequentially formed-MeUl Barrier Layer 116 and a metal layer 118' cover The electrical layer 114, the spacer 110, and the nitride layer 104b. Among them, the material used for the metal barrier layer 116 is, for example, titanium nitride, and the formation method thereof is, for example, sputtering, and the metal layer 118 The material used is, for example, tungsten (Tun2sten, W), and its formation method is, for example, chemical vapor deposition. Please refer to FIG. 1G, and then perform a ~ planarization process to cover the metal resistance on the surface of the dielectric layer 1M The part of the barrier layer Π6 and the metal layer α is removed only slightly above the surface of the dielectric layer 114, leaving a portion of the metal barrier layer 116a and the metal layer U8a to form a layer approximately the same height as the dielectric layer 114. Metal dynode 120. This planarization process, for example, uses the dielectric layer 114 as a honing termination layer to perform a chemical mechanical honing process. The next process can be easily achieved by a person skilled in semiconductor device manufacturing, so it is not here More details. The present invention is to first form a dielectric layer with a commercial dielectric constant, oxidize 9 W-scale configuration (CNS) A4 specifications (210 x 297 mm). -^ ills — ^ «— 11 ---!-^! (Please read the notes on the back first Please fill in this page again) Printed by 4320 St-1 AJ 5031twf. Doc / 0 06 _ B7 of the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives V. Description of the invention (separate) Fake gates in which the layers are sequentially stacked with the silicon nitride layer Electrode structure, and then using the dummy gate structure as a mask, an ion implantation process and a high temperature annealing process are performed to form a source region and a drain region of the device, and then silicon nitride in the dummy gate structure is formed. After the layer is removed, a nitriding process is performed to nitride the oxide layer in the dummy gate structure, and then a metal barrier layer and a metal barrier layer are inserted into the space vacated by the dummy gate structure due to the removal of the silicon nitride layer. A metal layer to form a metal gate. The invention uses the use of a dummy gate so that the source region and the drain region are completed before the metal sacrificial electrode is formed. Therefore, the high temperature annealing process required to form the source region and the drain region is not performed on the metal. After the gate is formed, the reliability of the metal gate is maintained. The transistor gate disclosed in the present invention uses a dielectric layer having a high dielectric constant as the gate dielectric layer. Therefore, under the trend of the reduction in the size of the device, it is possible to suppress the generation of the potential in the gate dielectric layer. High gate leakage current. The transistor gate disclosed in the present invention uses a metal with a lower sheet resistance 做 as a conductive material, so the word line delay can be reduced under the trend of shrinking element size. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. -! — Γ1 ------- Farm.! ----- Order --lull--line < Please read the precautions on the back before filling in this page) I 〇 This paper size applies the China National Standard (CNS) A4 specification (210 X 297 mm)