經濟部中央標浪局員工消費合作社印繁 ,4230 5 6 A7 J ._B7_ 五、發明説明（/ ) 技術領域： 本發明是關於積體電路之金氧半場效電晶體 (MOSFET ; Metal-Oxide Semiconductor FET)的製造方法， 特別是關於金氧半場效電晶體的製程中，前非晶化離子佈 植技術(pre-amorphization implant)之製造方法。 發明背景= 典型的金氧半場效電晶體(MOSFET)的製程是在矽半導 體晶圓上先定義出元件區，再利用場氧化生成隔離區以構 成每一獨立之元件區，然後在各獨立元件區內分別製造閘 極、源極以及汲極。 最近幾年來，由於積體電路之集積密度(packing density) 不斷增加，造成元件尺寸不斷減少，造成了場效電晶體中 閘極、源極以及汲極之阻值(parasitic electrical resistance)隨 之增加。請參閱圖一，爲了降低此阻極，傳統之製程方法 是在前述閘極3、源/汲極5處沈積一層低阻值之矽化物 (silicideX未標出），藉改善元件之傳輸延滯時間(propagation delay)，開關轉換速度(switching speed)而達到提升元件品質 之目的。矽化鈷(CoSi2)以及矽化鈦(TiSi2)均爲常見前述矽 化物之使用材料，矽化鈦因其低阻值之優點尤爲製程所善 用。而提升矽化鈦品質及沈積速度’在沈積矽化鈦之前， 可先進行砷(As)之離子佈植7將單晶矽基板的共價鍵打斷而 轉變爲非晶矽(amorphous silicon)以利於不同晶格狀態之矽 化鈦的生成，此製程稱之爲前非晶化離子佈植技術，常被 用在加強於微小寬度之矽化物成型上。關於此種技術較詳 2 . 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 公釐） I 11'/ ~~ϊ I I 11 訂-------1 — ^ In —Γ (請先閱讀背面之注意事項再填寫本頁) _ Γ 4 2 3 Ο 5 6 B7 娌肩部中央標準局負工消費合作社印製 五、發明説明（x?) 盡的描述，可參考以下的論文，”A new titanium salicide process (DIET) for sub-quarter micron CMOS", by Horiuchi et al., 1994 Symposium on VLSI technology digest on technical papers, 9A.3，pp. 12M22,以及’’Recent Progress of salicide technologies for subquarter micron CMOS", Kikkawa et al., IDEM 96, A3-5, pp. 125-132. 然而，由於元件尺寸不斷地被減少，以及複晶矽閘極 兩側側壁子9之影響，複晶線間的空間也不斷減少，而造成 了所欲生成之矽化物(silidde)無法在複晶矽閘極之源極/汲 極的P+區域上形成，也就是說，在元件尺寸小型化的過程 中，矽化鈦因在圖案較窄區以及沈積膜厚之減少，不但會 阻礙由所謂的C49到C54相位變化，同時也會加速矽化鈦膜 之凝結(agglomeration)，此種現象會使在含砷離子佈植之複 晶矽上之矽化鈦阻值增高，尤其是在P+區域中植入N型的砷 離子，減少了基板內多數載子(電洞)的濃度，更是提高了K 區域的阻值，在此情況下，利用前述異晶化離子佈植技術 將砷離子先行植入反而會提升元件之阻值，如此一來，未 蒙其利反受其害，卻造成了元件之劣化。同時，高能量植 入N型的砷離子也很有機會直達P+區域的底部5a，而造成了 pi/N接面漏電流的增加。 另一方面，因爲複晶矽閘極的晶格結構較爲疏鬆，植 入的砷離子也很容易貫穿至複晶矽與閘氧化層11的接面而 形成一個通道(channeling)，進而改變了複晶矽閘極的功函 數(work fimction)，也就影響了場效電晶體的特性。 3 — 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~~I----%--1 -- --- -----^衣 1— -I I I !、1τI -----1--I - ·-!-_ (請先閱讀背面之注意事項再填tr本頁) 4230 5 6 Λ7 B7 經濟部中央標準局員工消費合作社印聚 五、發明説明（力 本發明即是針對此現象，提出了一種改良型前非晶化 離子佈植技術，能夠成功地在進行微小尺寸之元件的前非 晶化離子佈植製程時，去除掉前述使用上之缺點，而仍保 有其優點之製程。 發明之簡要說明： 本發明之主要目的是提供一種前非晶化離子佈植技術 之改良製程，可以有效地解決離子植入狹窄無法於後續製 程形成矽化物之區域而造成不當之元件阻值提增之問題。 本發明之次要目的是提供一種前非晶化離子佈植技術 之改良製程，僅在複晶矽閘極上方植入砷離子，以降低矽 化物的阻值。 本發明之再一目的是提供一種前非晶化離子佈植技術 之改良製程，利用大角度方式植入砷離子，可以獲得較淺 的非晶矽深度，進而減少接面的漏電流》 本發明之又一目的爲提供一種前非晶化離子佈植技術 之改良製程，可以較高的能量卻植入較低劑量的砷離子， 減少對電晶體特性的影響。 本發明之進一目的爲提供一種前非晶化離子佈植技術 之改良製程，可以消弭習知技藝之通道效應，維持閘極正 常的功函數。 本發明之主要製程方法如下：首先，在矽半導體基板 上定義出元件區，再利用場氧化層區隔各元件區，然後在 元件區中沈積複晶矽，並利用微影及蝕刻技術將此複晶矽 形成複晶線以作爲MOSFET之閘極，接著，形成一層氧化 ____4_:___ 本紙張尺度逋用中國國家標準（CNS ) A4規格（.210x297公釐} {請先聞讀背面之注意事項再填寫衣頁) 裝·Employees' Cooperatives of Central Standard Wave Bureau, Ministry of Economic Affairs, Yinfan, 4230 5 6 A7 J ._B7_ V. Description of the Invention (/) Technical Field: The present invention relates to a metal-oxide semiconductor field-effect transistor (MOSFET; Metal-Oxide Semiconductor) FET) manufacturing method, especially the manufacturing method of pre-amorphization implant in the process of metal oxide half field effect transistor. Background of the Invention = A typical metal-oxide-semiconductor field-effect transistor (MOSFET) process is to first define a device region on a silicon semiconductor wafer, and then use field oxidation to generate an isolation region to form each independent device region, and then The gate, source, and drain are fabricated in the area. In recent years, due to the increasing packing density of integrated circuits, the size of components has continued to decrease, resulting in the increase in the gate, source, and drain electrical resistance of field-effect transistors. . Please refer to Figure 1. In order to reduce this resistance, the traditional manufacturing method is to deposit a layer of low resistance silicide (silicideX not shown) at the gate 3 and source / drain 5 mentioned above to improve the transmission delay of the component. Time (propagation delay), switching speed (switching speed) to achieve the purpose of improving component quality. Cobalt silicide (CoSi2) and titanium silicide (TiSi2) are common materials for the aforementioned silicides. Titanium silicide is particularly useful in manufacturing processes because of its low resistance. Improving the quality of titanium silicide and the deposition speed 'Before the deposition of titanium silicide, the arsenic (As) ion implantation can be performed. 7 The covalent bond of the single crystal silicon substrate is broken and transformed into amorphous silicon to facilitate The generation of titanium silicide in different lattice states, this process is called pre-amorphous ion implantation technology, and it is often used to strengthen the silicide molding with a small width. More details about this technology 2. This paper size applies Chinese National Standard (CNS) A4 specification (210X mm) I 11 '/ ~~ ϊ II 11 Order ------- 1 — ^ In —Γ ( Please read the precautions on the back before filling this page) _ Γ 4 2 3 Ο 5 6 B7 娌 Shoulder printed by the Central Bureau of Standards and Consumer Cooperatives V. Description of invention (x?) For the full description, please refer to the following paper , "A new titanium salicide process (DIET) for sub-quarter micron CMOS ", by Horiuchi et al., 1994 Symposium on VLSI technology digest on technical papers, 9A.3, pp. 12M22, and" Recent Progress of salicide technologies for subquarter micron CMOS ", Kikkawa et al., IDEM 96, A3-5, pp. 125-132. However, due to the ever-decreasing element size and the influence of side walls 9 on both sides of the polysilicon gate, The space between the lines is also continuously reduced, resulting in that the desired silicide cannot be formed on the P + region of the source / drain of the polycrystalline silicon gate, that is, in the process of miniaturizing the component size In the middle, the titanium silicide is Reduction will not only hinder the phase change from the so-called C49 to C54, but also accelerate the agglomeration of the titanium silicide film. This phenomenon will increase the resistance of titanium silicide on polycrystalline silicon implanted with arsenic ions. In particular, implanting N-type arsenic ions in the P + region reduces the concentration of majority carriers (holes) in the substrate and increases the resistance value in the K region. In this case, the aforementioned heterocrystalline ion cloth is used Implantation of arsenic ions in the implantation technology will increase the resistance value of the device. In this way, it will not damage the components but will cause the degradation of the device. At the same time, high-energy implantation of N-type arsenic ions is also very The opportunity directly reaches the bottom 5a of the P + region, which increases the leakage current at the pi / N junction. On the other hand, because the crystal structure of the polycrystalline silicon gate is relatively loose, the implanted arsenic ions can easily penetrate to the complex The interface between the crystalline silicon and the gate oxide layer 11 forms a channel, which in turn changes the work function of the polycrystalline silicon gate, which also affects the characteristics of the field-effect transistor. 3 — Size of this paper Applicable to China National Standard (CNS) A4 specification (2 10X297 mm) ~~ I ----%-1---- ----- ^ 衣 1— -III!, 1τI ----- 1--I-·-! -_ ( Please read the notes on the back before filling the tr page) 4230 5 6 Λ7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (This invention aims at this phenomenon and proposes an improved front amorphous The ion implantation technology can successfully remove the aforementioned shortcomings in the process of pre-amorphous ion implantation of micro-sized components, while still maintaining its advantages. Brief description of the invention: The main purpose of the present invention is to provide an improved process for pre-amorphous ion implantation technology, which can effectively solve the problem of improper component resistance increase due to the narrow area of ion implantation that cannot form silicide in subsequent processes. Increasing problems. A secondary object of the present invention is to provide an improved process for the pre-amorphization ion implantation technology, in which arsenic ions are implanted only above the polycrystalline silicon gate to reduce the resistance of the silicide. Another object of the present invention is to provide an improved manufacturing process of pre-amorphous ion implantation technology. By implanting arsenic ions in a large angle, a shallower depth of amorphous silicon can be obtained, thereby reducing leakage current at the interface. Yet another object is to provide an improved process for pre-amorphous ion implantation technology, which can implant lower doses of arsenic ions at higher energy and reduce the effect on transistor characteristics. A further object of the present invention is to provide an improved process for the pre-amorphous ion implantation technology, which can eliminate the channel effect of the conventional technique and maintain the normal work function of the gate. The main process method of the present invention is as follows: first, define a device region on a silicon semiconductor substrate, and then use a field oxide layer to isolate each device region; then deposit polycrystalline silicon in the device region, and use lithography and etching technology to The polycrystalline silicon forms a polycrystalline wire to serve as the gate of the MOSFET, and then forms a layer of oxidation ____ 4 _: ___ This paper size uses the Chinese National Standard (CNS) A4 specification (.210x297 mm) {Please read the note on the back first (Please fill in the clothing sheet for the items)
、1T A 7 B7 42305 五、發明説明 層以進行側壁子蝕刻形成側壁子，再利用離子佈植技術將 離子打入而形成源極以及汲極。接下來的步驟爲本發明之 重點所在，係利用大角度離子怖植技術，將砷離子(As+)進 行全面性植入(blanket As+ ion implant)，爲避免其被植入複 晶線間之半導體基板的源/汲極區域，選擇角度介於3〇°至 45°之間打入砷離子。如此，複晶矽間之間隙由於角度之 關係不會被植入砷離子，此區域在後續之矽化鈦(TiSi2)無 法形成後亦不會因砷離子之植入造成不欲之阻值增加，於 是，本發明所述之一種改良型前非晶化離子佈植技術於焉 完成。 簡要圖式說明： 圖一爲習知技藝經過前非晶化離子佈植處理之電晶體 的剖面示意圓。 圖二爲本發明實施例之製程剖面圖。 圖號說明： 3-閘極 7-離子佈植 11-隔氧化層 21-半導體基板 25-複晶砂層 29-側壁子 33-金屬矽化物層 發明之詳細說明： 請參閱圖二。首先，在矽半導體基板21上形成場氧化 (請先閱讀背面之注意事項再填笃太頁) 裝. 經濟邡中央標箪爲員工消費合作社印掣 5-源/汲極 9-側壁子 23-閘氧化層 27-源/汲極區域 31-離子束 本紙張尺度適用中國國家標準（CNS ) A4規格〔210 X 297公釐） -Λ23〇5 6 ^ Α7 Β7 經濟部中央樣装.局員工消費合作社印製 五、發明説明（Γ) 層（未標出），所述場氧化層通常是熱氧化(thermal oxidization)所述矽半導體基板21而成，其厚度介於2000埃 至6000埃之間，作爲隔離場效電晶體之用。然後，在場氧 化層之間形成金氧半場效電晶體，形成方式如下：先利用 熱氧化(thermal oxide)形戊一厚度介於200埃至300埃之閘氧 化層23，然後在此閘氧化層23之上經由低壓氣相化學沈積 法(Low Pressure Chemical Vapor Exposition)沈積一厚度介於 1000埃至2500埃之間之複晶矽層25，再利用微影及電漿触 刻製程技術，將所述複晶矽層25定義形成閘極，接著，利 用離子佈植技術來形成金場半場效電晶體之P+源/汲極區域 27，其離子佈植劑量爲介於2E14到4E16原子/平方公分之 間，離子佈植能量則介於50到90 KeV之間，接下來，再次 沈積一層氧化物並蝕刻之以形成側壁子29。以一個典型的 0.25微米製程爲例，兩個側壁子29之間的距離約爲0.36微 米，而裸露的源/汲極27區域大約僅爲0.12微米左右。 接下來，進行本發明重點之大角度的全面性前非晶化 離子佈植31，所植入的離子通常爲N型的離子，如砷 (As75)、磷(P31)、氮(N)、銻(Sb)或鉍(Bi)等離子，但是四價 的矽(Si)或鍺(Ge)離子，或者甚至是P型的離子，如二氟化 硼(BF2)、銦(In)，也都可以達到相同的功效，其佈植離子 之角度係介於30度到45度之間，以植入砷離子爲例，其離 子佈植能量爲20到40 KeV之間，而其離子佈植劑量則爲 E14到E15原子/平方公分。由於佈植離子之角度控制在30 度到45度之間，因此在複晶矽線間之裸露的P+源/汲極27狹 __6_^ _ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -----：-----装------訂------级 (請先閱讀背面之注意事項再填将本頁) 42305 6 Α7 Β7 五、發明説明（心） 小部份不會被植入離子。如此，本發明所述之改良式前非 晶化離子佈植於焉完成。接著利用濺鍍(sputter)技術沈積銘 或鈦等頑固金屬，再經過高溫快速熱回火(RTA)的處理以生 成如矽化鈷(CoSi2)或矽化鈦(TiSi2)等金屬矽化物33，最後 即可進行傳統金氧半場效電晶體之後續製程。 以上所述利用較佳實施例說明本發明，而非限制本發 明之範圍，且熟知此技藝之人士皆可了解。些微適當之改 變，將不失本發明要義所在 範圍。 亦不脫離本發明之精神以及 -- (請先閱讀背面之注意事項再填寫衣頁) 經濟部中央標隼局員工消費合作社印製 本纸張尺度適用中國國家榡準（CNS M4規格UH)X297公釐）1T A 7 B7 42305 V. Description of the invention Layers are used to etch sidewalls to form sidewalls, and then ion implantation is used to form ions into the source and drain. The next step is the key point of the present invention. It uses a large-angle ion implantation technology to make a blanket As + ion implant in order to prevent it from being implanted into the semiconductor between the polycrystalline lines. In the source / drain region of the substrate, select an angle between 30 ° and 45 ° to insert arsenic ions. In this way, the gap between the polycrystalline silicon will not be implanted with arsenic ions due to the angle. This region will not cause undesired resistance increase due to the subsequent implantation of titanium silicide (TiSi2). Therefore, an improved pre-amorphous ion implantation technology described in the present invention is completed in the cymbal. Brief description of the diagram: Figure 1 is a schematic circle of a cross section of a transistor that has been subjected to a prior amorphous ion implantation treatment in a conventional technique. FIG. 2 is a cross-sectional view of a manufacturing process according to an embodiment of the present invention. Explanation of drawing number: 3-gate 7-ion implant 11-isolation layer 21-semiconductor substrate 25-polycrystalline sand layer 29-side wall 33-metal silicide layer Detailed description of the invention: Please refer to FIG. First, a field oxide is formed on the silicon semiconductor substrate 21 (please read the precautions on the back and then fill in the page). The economy and central label are printed for the employee consumer cooperative 5-source / drain 9-side wall 23- Gate oxide layer 27-Source / drain region 31-Ion beam This paper size applies Chinese National Standard (CNS) A4 specification [210 X 297 mm]-Λ23〇5 6 ^ Α7 Β7 Central sample of Ministry of Economic Affairs. Staff consumption Cooperative printed 5. Description of invention (Γ) layer (not shown), the field oxide layer is usually formed by thermal oxidization of the silicon semiconductor substrate 21, and its thickness is between 2000 angstroms and 6000 angstroms , As an isolation field effect transistor. Then, a gold-oxygen half field-effect transistor is formed between the field oxide layers, and the formation method is as follows: first, a thermal oxide is used to form a gate oxide layer 23 having a thickness of 200 angstroms to 300 angstroms, and then the gate oxide is oxidized there. A polycrystalline silicon layer 25 with a thickness between 1000 Angstroms and 2500 Angstroms is deposited on the layer 23 through a Low Pressure Chemical Vapor Exposition method. The polycrystalline silicon layer 25 is defined to form a gate electrode. Then, an ion implantation technique is used to form a P + source / drain region 27 of a gold field half field effect transistor, and the ion implantation dose is between 2E14 to 4E16 atoms / square. Between centimeters, the ion implantation energy is between 50 and 90 KeV. Next, another layer of oxide is deposited and etched to form the sidewalls 29. Taking a typical 0.25 micron process as an example, the distance between the two side walls 29 is about 0.36 micrometers, and the exposed source / drain region 27 is only about 0.12 micrometers. Next, the comprehensive pre-amorphous ion implantation 31 with the large angle of the present invention is performed. The implanted ions are usually N-type ions, such as arsenic (As75), phosphorus (P31), nitrogen (N), Antimony (Sb) or bismuth (Bi) ions, but tetravalent silicon (Si) or germanium (Ge) ions, or even P-type ions, such as boron difluoride (BF2), indium (In), are also The same effect can be achieved. The angle of implanting ions is between 30 degrees and 45 degrees. Taking arsenic ions as an example, the ion implanting energy is between 20 and 40 KeV, and the ion implanting dose is For E14 to E15 atoms / cm². Because the angle of the implanted ions is controlled between 30 degrees and 45 degrees, the bare P + source / drain 27 between the polycrystalline silicon lines is narrow. __6_ ^ _ This paper standard applies to China National Standard (CNS) A4 specifications ( 210X 297mm) -----: -------- Installation ------ Order ------ Class (Please read the precautions on the back before filling this page) 42305 6 Α7 Β7 Five 2. Description of the Invention (Heart) A small part will not be implanted with ions. In this way, the improved pre-amorphous ion implantation according to the present invention is completed in the salamander. Sputter technology is then used to deposit refractory metals such as titanium or titanium, and then subjected to high-temperature rapid thermal tempering (RTA) to generate metal silicides 33 such as cobalt silicide (CoSi2) or titanium silicide (TiSi2). Subsequent processes for traditional metal-oxide half-field effect transistors can be performed. The above description uses the preferred embodiments to illustrate the present invention, but not to limit the scope of the present invention, and can be understood by those skilled in the art. Slightly appropriate changes will not lose the scope of the gist of the present invention. It does not depart from the spirit of the present invention and-(Please read the precautions on the back before filling in the clothing page) Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standards (CNS M4 Specification UH) X297 Mm)