TW421793B - Fabricating method of multi-stage memory unit having asymmetric drain current and the integrated circuit - Google Patents

Abstract

This invention relates to an asymmetric multi-stage memory unit that provides suppressed source reading current. This suppressed source reading current can greatly reduce the error possibility of misreading for device type of the memory array that includes multi-stage memory unit. The fabricating method of asymmetric multi-stage memory unit includes source ion implantation. Isolation material is formed to the drain side of the gate before source/drain ion implantation, and finally the compensated bias region is formed in between channel and drain. This compensated bias region is not controlled by gate voltage. For 0.12 mu m isolation material, drain current is 3.5 times larger than source current at 1.5 volt voltage bias. The asymmetric multi-stage memory unit in the memory array has common source assembly and in fact proceeds the read operation in one direction due to the fact that source current of the memory unit near the word line is smaller than drain current of the reading unit.

Description

4.2179 3 A7 ___B7 V. Description of the invention (1) The present invention relates to integrated circuit memory, especially a metal-oxide-semiconductor (MOS) integrated circuit memory device having multiple binary numbers (bits) per unit. Description of related technology The cost of an integrated circuit memory device is closely related to the size of the integrated circuit area required to store a fixed amount of data. This integrated circuit area size is often used as a parameter of component density ° to save integrated circuit area , Manufacturers can make more wafers from a given wafer in the manufacturing plant. Having more wafers per wafer can directly save manufacturing costs to consumers of hundreds of millions of devices. One way to increase the density of memory device components is to store more than one bit of data in each memory cell. For example, storing two bits of data per memory cell provides twice the data density on the integrated circuit. For floating gate memory devices, multi-bit technology has been developed, such as U.S. Patent No. 5,1 63,02 1 to Mehrotra et al. However, the method of the floating gate memory device involves the complex charging and discharging processes of the floating gate, as well as difficult detection techniques, which will increase its complexity and reduce the reliability of the hundreds of millions of devices. Therefore, there is a need for a simple, reliable, and low-cost technology to implement memory cells with multiple bits per billion cells in integrated circuits. This paper size is applicable to Chinese National Standard (CNS) A4 (210X297). Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4.2179 3 ______ Β7 5. Summary of the Invention (>) Summary of the Invention The present invention provides a Technology for storing multiple bits of data in each memory cell in an integrated circuit of a memory cell. Sources of errors found in memory arrays include symmetric memory cells. Another source of error is the current paths through nearby memory cells. These current paths will change the drain read current of the required 100 million cells, so that different types of cells are read. Asymmetric memory cells will greatly reduce the source read current. Properly place the asymmetric memory unit into the memory device and use the reduced source read current to ensure that the multi-level memory unit in the memory device can be accurately read out. The invention therefore eliminates errors from the current path. In some embodiments of the invention, the memory cell has a drain, a source, and a channel disposed between the drain and the source, all of which are on the substrate of the memory cell. In asymmetric billion-count cells, the channel extends laterally from the drain. The lateral distance between the drain and the source is a biased region. The offset area is placed in the substrate. The offset region is between the drain and the channel. The memory cell has a plurality of bits, and the a MOS element stored in the channel has multiple groups of memory cells. A particular group of memory cells has different threshold voltages compared to other groups of memory cells. The threshold voltage depends on the impurity concentration in the channel region. Each information bit is a threshold voltage 値 corresponding to a hundred million cells. 4 This paper size applies to China National Standard Umbrella (CNS) A4 size (210x297 male rear) ^ ------ 1, I installed-} (Please read the precautions on the back before filling this page) Order 421793 A7 ___________B 5. Explanation of the Invention (i) The first embodiment of the present invention provides a method for forming a multi-level memory unit in a memory array on a substrate. The memory array has a plurality of multi-level memory cells. Each multi-level memory cell includes a gate, a gate oxide, a channel, a drain, and a source. The gate is on the gate oxide layer. The gate oxide layer has a top. The channel is inside the substrate and is aligned with the gate. The drain is on the first side wall of the gate. The source is located inside the substrate and on the second sidewall of the gate. The second side wall is opposite to the first side wall. A method of forming a multi-level memory cell includes performing source ion implantation, forming a first spacer, and performing source / drain ion implantation. Source ion implantation is performed on the source of each multi-level memory cell. A first spacer is formed on the first sidewall of the gate and extends upward from the top of the gate oxide layer. The first spacer has a first spacer width. The first spacer width can provide offset between the channel and the drain of each multi-level memory cell.

The source / drain ion implantation of the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is performed on the source and drain of each multi-level memory cell. After these steps, an offset region is formed. The offset region is between the channel and the drain. The offset region can suppress the source read current. For the first embodiment, the width of the first spacer is about 0.05 μm. 5 This paper size is applicable to Chinese national standards (CNS > A4 specifications < 210X297 mm). Cooperative printed A7 ______ B7 V. Description of invention (〆) The range is about 0.20 microns. The offset bias is smaller than the width of the first spacer. For some embodiments, the magnitude of the offset is approximately greater than fifty percent of the first spacer width (> 50%). For the first embodiment, the method further includes performing a first channel ion implantation, performing a first code ion implantation, performing a second code ion implantation, forming a samarium oxide layer, and depositing a first conductive layer from the first The conductive layer defines the gate pattern and shields the drain; before the source ion implantation is performed. The first channel ion implantation is performed on a multi-level memory cell. The first bit code ion implantation is performed for the first group of selected multi-level memory cell channels. The second bit code ion implantation is performed for the second group of selected multi-level memory cell channels. The second bit code ion implantation has a different projection range than the first channel ion implantation. The second bit code ion implantation also has a different projection range than the first bit code ion implantation, that is, the depth distribution. Each multi-level memory cell has a bit code, which is selected from a set of four different bits. Each of the four different bits corresponds to the first channel ion implantation of a specific combination, the first bit code ion implantation, and the second bit code ion implantation. In general, bit code ion implantation can be regarded as n bit code ion implantation performed on a group of n selected multi-level memory cell channels. Each of the η ion implants has a set of ion implant characteristics, 6 paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (2 〖〇X297mm） 421793 Λ7 ______B7_ V. Description of the invention (today) But different from other η-1 ion implantation. Each multi-level memory cell can have one bit code, which is selected from a group of 2n different bit codes. Each bit code of 2 " different bit codes corresponds to the first channel ion implantation of a specific combination and the n-bit code ion implantation. For some embodiments, the set of ion implantation characteristics includes the projection range and the number of ions implanted. For some first embodiments, the method further includes depositing a second conductive layer and defining a second conductive layer; after performing the source / discharge ion implantation. For certain first embodiments, the method further includes forming a second spacer on a second side of the gate, the second spacer extending upward from the top of the gate oxide layer. A second embodiment of the present invention The MOS memory cell is provided in the integrated circuit. The integrated circuit has a substrate. This MOS memory cell has a source and a gate formed on a substrate. The MOS memory cell also has a gate oxide layer of the MOS memory cell between the substrate and the gate. The gate oxide further includes a drain, a channel, and an offset region. The drain is formed in the substrate and has a width. The channel is formed in the substrate. The channel contacts the gate oxide. I. 7 This paper size applies the Chinese national standard (CNS > A4 size (210XM7mm) 42Π93 A7 B? V. Description of the invention (dagger) The channel is aligned with the gate. The channel extends at least one section from the source to the drain. The channel is separated from the drain by a biased region. The channel is adjusted to store multi-bit data. For some embodiments, the channel will form an empty layer near the gate oxide layer to The gate voltage is reacted. The compensation region has an initial conduction state. The compensation region can maintain the original conduction state when it is close to the gate oxide layer. The MOS memory cell has a voltage corresponding to the drain voltage. The drain read current and the source read current corresponding to the source voltage. The source voltage is equal to the gate voltage. The magnitude of the drain read current is different from the source read current.

锖 先 (Notes on the back of T reading-¾ Fill out this I Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs For some second embodiments, the source read current is less than the drain read current, and the offset area will An empty layer is formed in a region close to the oxidized oxide layer to reflect the drain voltage. The offset region is in the range of about 0.02 microns to about 0.20 microns, and the offset region can maintain the original when close to the gate oxide layer. The on-state responds to the source voltage. For some second embodiments, the gate has a gate width. The gate also has a first side, a second side opposite to the first side, a bottom, and a top. The gate width is the distance between the first and second sides. The gate is between the source and the drain. The gate is on the gate oxide. The drain is on the first side 8 paper sizes Applicable to China National Standard (CNS) Α4 specification (2 丨 0X297 mm) Printed by Shellfish Consumer Cooperative of Central Standards Bureau of Ministry of Economic Affairs 42 ^ 93 A7 _______B7 V. Description of the invention (Even) The source is on the second side. Gate The width is less than the distance between the source and the drain. The electrode oxide layer has a top. In this embodiment, the MOS memory cell further includes a first spacer along the first side of the gate. The first spacer extends upward from the top of the gate oxide. The first isolation The object also has a first spacer width. A third embodiment of the present invention provides an integrated circuit including a memory cell array, a bit line, and a word line. The memory cell includes a plurality of transistors, and the transistors are on the substrate. There are channels in the channel area. The selected memory unit in the array stores multi-bit data in the channel. Word lines and bit lines are coupled to the columns and rows of the memory cells in the array, thereby reading the data stored in the array. Information. The bit line contains the first pattern layer of the integrated circuit. The word line contains the second pattern layer of the integrated circuit. Each selected billion cell has a source formed in the substrate. The gate oxide layer between the base gates. Each selected memory cell further includes an asymmetric drain, channel, and offset region. The asymmetric drain is formed in the substrate and has a width. The channel is in the base The channel is aligned with the gate. The channel extends from the source to the asymmetric drain. The channel and the asymmetric drain are separated by an offset region. The channel is adjusted to store multi-bit data. . This paper 9 paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) A7 __B printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (?) An empty layer is formed in the channel region to reflect the gate voltage. The offset region has an initial conduction state. The offset region can maintain the original conduction state when it is close to the gate oxide layer to reflect the gate voltage. The selected memory cell has a drain read current corresponding to the drain voltage and a source read current corresponding to the source voltage. The source voltage is applied at the first time and the drain voltage is applied at the second time. The current in the body circuit flows in a first direction at a first time and flows in a second direction at a second time. The second direction is opposite to the first direction. The source voltage is equal to the drain voltage. The magnitude of the drain read current is different from the magnitude of the source read current. The offset of each selected memory cell transistor is large enough to ensure that the selected memory cell transistor can only be accurately read by the corresponding word line and corresponding bit line in the same direction. For some third embodiments, the offset compensation is in the range of about 0.02 microns to about 0.20 microns. The offset region will form an empty layer in the region close to the gate oxide layer to reflect the drain voltage, and the offset region can maintain the original conduction state when it is close to the gate oxide layer, so as to respond to the source voltage. 10 This paper size applies to the Chinese National Standard (CNS) 6 and 4 grids (210X: 297 mm) (Please read the notes on the back 背面 # ·· Fill in this page)-Binding · Binding 4 217 9 3 Λ7 Β7 Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards

5. Description of the Invention (f) For some third embodiments, the gate of each selected memory cell may be addressed by a corresponding word line. The integrated circuit further includes a sense amplifier, ground, a first selected memory cell transistor, and a second selected memory cell transistor. The sense amplifier has a lead, a first side, and a second side. The ground has a lead, a first side, and a second side. The bit line is close to the ground wire. The bit lines are close to the leads of the sense amplifier. The bit line is on the second side of the sense amplifier wire. The first selected memory cell transistor is between the bit line and the second side of the sense amplifier wire. The drain of the first selected memory cell transistor is connected to the lead of the sense amplifier. The second selected memory cell transistor is between the bit line and the first side of the ground wire. The drain of the second selected hundred million unit transistor is connected to the ground wire. Both the first selected memory cell transistor and the second selected memory cell transistor have a common source. The bit line is connected to a common source of the first and second selected memory cell transistors. Among them, the first selected memory cell transistor can only be accurately read out by the corresponding word line and corresponding bit line in the first direction. The second selected memory cell transistor can be accurately read out by the corresponding word line and corresponding bit line in the second direction. The first direction is opposite to the second direction D I ------- ^^-4. 1. (Please read the precautions on the back before filling in this page), va Special paper size applies Chinese national standards ( CNS) A4 specification (210X297 mm) ΑΊ 421Τ9 3 ____L7___ Description of the invention (㈨) For some embodiments, the integrated circuit further includes a sense amplifier, a ground, a first selected memory cell transistor, and a second selected memory Million unit transistors. For these embodiments, the first direction is from the drain of the first selected memory cell transistor to the source of the first selected memory cell transistor. The second direction is from the drain of the second selected memory cell transistor to the source of the second selected memory cell transistor. Part of the current in the second direction will flow from the source of the first selected memory cell transistor to the drain of the first selected memory cell transistor. Part of the second direction current in the first selected memory cell transistor is less than forty percent of the second direction current in the second selected memory cell transistor. Part of the current in the first direction will flow from the source of the second selected memory cell transistor to the drain of the second selected memory cell transistor. A portion of the first direction current in the second selected memory cell transistor is less than forty percent of the first direction current in the first selected memory cell transistor. A fourth embodiment of the present invention provides a method for reading a memory cell with a complementary bias. The method includes providing a billion-memory unit, wherein the memory unit is an asymmetric memory unit. For some embodiments in the group, the asymmetric memory unit is a multi-level memory unit. Brief description of the drawings. 12 This paper size applies to China National Standard (CNS) A4 specification (2〗 0X297 gong) (please read the notes on the back and fill out this page). Equipment · '11 Staff Consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative 421793 __'_ B7 V. Description of the invention (ί)) Figure 1 shows the relationship between the drain read current and the threshold voltage in a two-bit order memory cell with four different bit codes. FIG. 2 shows the back gate bias voltage versus the threshold voltage in the embodiment of the present invention. Figure 3 shows the vertical miscellaneous distribution data in the embodiment of the present invention. "Figure 4 shows the relationship between the drain read current and the threshold voltage for a three-bit memory cell with eight different bit codes. FIG. 5 is a schematic cross-sectional view of a symmetric memory cell in a conventional technique. FIG. 6 is a schematic cross-sectional view of an asymmetric memory unit according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of a memory cell fabrication layer after a gate oxide layer, a first conductive layer and a first dielectric layer are deposited in a second group of embodiments of the present invention. FIG. 8 is a cross-sectional view of a memory cell fabrication layer after the pattern of the first conductive layer is defined in the embodiment of the present invention. Fig. 9 shows a cut-away view of the source ion implantation and the memory cell fabrication layer in the embodiment of the present invention. FIG. 10 is a cross-sectional view of a memory cell layer according to an embodiment of the present invention, and a drain ion implantation is also shown in the figure. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Figure 11 shows a cross-sectional view of the memory cell production layer after the second-stage gate shielding layer is removed in the embodiment of the present invention. FIG. 12 shows a cross-sectional view of a memory cell fabrication layer after a second conductive layer is deposited in an embodiment of the present invention. FIG. 13 shows a current-voltage diagram of an asymmetric memory cell in an embodiment of different offset (isolator) sizes of the present invention. 13 This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 1 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 42Π93 B7 V. Description of the invention (\ V) 'Figure 14 is the use of the conventional symmetric memory cell technology Structure diagram of the formed memory cell array. Figure 15 shows the structure of a memory cell array containing asymmetric multilevel memory cells. Figure 16 shows a scheme for blocking other current paths in a memory cell array containing asymmetric multilevel memory cells. Detailed description With reference to FIGS. 1 to 13, a manufacturing method and an integrated circuit for realizing a multi-level memory cell with an asymmetric drain are disclosed. In the following description, for the sake of explanation, a specific name will be mentioned first to provide a complete understanding. However, many details of these specific names are not needed for the present invention. For an integrated circuit with all the advantages of improved memory density provided by a multi-level memory unit, the integrated circuit must accurately read the bit code of each type in the multi-level memory unit. Each group of multi-level memory cells has a special bit code 値. Each bit code 値 is defined by a unique threshold voltage (Vt). In the absence of the source of the drain current reading error caused by the conventional symmetric memory cell technology, the bit code has been separated, because each memory unit type has a unique threshold voltage, which can be read out to record billions. It depends on the drain current of the cell. However, in the conventional memory cell array technology including symmetric memory cells, a source of errors was found. The source of this error is due to the fact that this paper applies the Chinese National Standard (CNS) Λ4 rule (210X297 gong) (please read the notice on the back first to fill out this page), τ A7 42ΊΤ9 3 V. Description of the invention (Oy) Other currents flowing through the adjacent memory cells will change the drain current of the required memory cells so that they can be read as different memory cells. The present invention provides a new symmetrical 100 million cell structure. The asymmetric memory cell of the present invention is adjusted to greatly reduce the source read current. The properly arranged asymmetric memory cells in the billion-cell array use the reduced source read current to ensure that the multi-level memory cells in the memory device can be accurately read. The invention therefore eliminates the source of errors from other current paths. The asymmetric memory unit is particularly suitable for multi-level photomask ROM integrated circuits. Please read the note on the back of the box. ▲ This page is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. By combining different ion implants in each memory cell channel, different threshold voltages are achieved. Different combinations of ion implantation provide unique threshold voltages for each type of billion-cell in the memory array. A series of n-bit code ion implantation is performed on the selected memory cell channel after the initial shallow critical voltage ion implantation process is performed on all memory cell channels. Each bit code ion implantation has a set of ion implantation characteristics that are different from other bit code ion implantation and different from the initial shallow critical voltage ion implantation. The bit code ion cloth vegetation is adjusted to provide a critical threshold voltage for some substrate bias. This set of ion implantation characteristics includes projection range and 15 paper waves with Chinese National Standard (CNS) A4 regulations (210 X 297 mm)

I 42Π93 Λ7 __B? 5. Description of the invention (\ V) Number of ions implanted by ions. Different combinations of different bit code ion implants provide memory cells capable of storing multi-level bit data per memory cell. Table 1 and Table 2 provide the basis for determining the number of bits per memory cell when all the 100 million cells in the memory array are ion implanted in the first channel, that is, the ion implantation of the initial threshold voltage. The number of unit bits will be used for the number of ions implanted for the given positioning code. The simplest example is a single bit code ion implantation of selected memory cells to form a one-bit memory array. At this time, n = 1 and only one bit is stored in each memory cell, 0 (no bit ion implantation in the memory cell) or 1 (bit ion implantation in the memory cell). When n = 1, each memory cell has a one-bit code, which is selected from group 0 or 1, or a selection group that forms a two-bit code. Also, when n = 1, the memory array contains two This type of memory unit is worth 0 million units and 1 memory unit. It should be noted that the number of bit codes in the selection group is equal to the number of memory cell types in the memory array. Based on this example and the above, printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, the relationship between the number of bit codes (S) in the selected group and the number of ion implantations of bit codes for the selected memory unit , Where S equals 2n. When n = 2, S = 2k2. Table 1 lists when n = 2, or 16 paper sizes for the selected memory cell channel are applicable to the Chinese standard (CNS) A4 specification (2 丨 0X 297 mm) 421T93 Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed A7 B7 V. Description of the invention (〆) When the discernable two-bit code is ion-implanted, there are multiple bits per memory unit. According to the assumed relationship, for two-bit code ion implantation (n = 2), the number of bit codes in the selected group is S = 22 = 4. Therefore, it can be seen from Table 1 that this hypothesis (S = 2n) still holds for n = 2. For n = 2, as shown in Table 1, the memory array includes four types of memory cell types. These four types of memory cell types are provided by combining two-bit code ion implantation and first channel ion implantation. This combination is applied to a two-bit order memory cell array. In the example discussed, the first bit code ion implantation has a smaller projection range than the second bit code ion implantation (because of the lower ion implantation energy) > > Type I memory Unit; 00 has only one channel ion implantation, that is, other bit code ion implantation. The second type memory cell 01 has another second bit code ion implantation. The third type memory cell 10 has another first bit code ion implantation. The fourth type memory unit 11 has another first bit code ion implantation and another second bit code ion implantation. The first channel ion implantation The first bit code ion implantation The second bit code ion implantation memory cell type YNN 00 YYN 01 YN .Y 10 YYY 11 The two-bit order records the billion-bit unit code ion implantation number = 2 = n Number of memory cell types = 2n = 4 Table 1 17 This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) {Please ^ t., Please note the notes on the back, please fill in this page)

42179 3 λ7 ____ Β7 ___ 5. Description of the Invention (\ W) The diagram in Figure 1 shows the relationship between the drain read current and the threshold voltage for a two-bit memory cell with four different bit codes. In this example, for a given voltage, each type of memory cell is separated from a different type of memory cell by the drain read current. As shown in Figure 1, the 00 unit current / voltage characteristic 100 includes the highest drain read current and the lowest threshold voltage, and the 11 unit current / voltage characteristic 115 includes the lowest drain read current and the highest. Critical voltage. Figures 2 and 3 provide critical voltage data and vertical doping profile data implemented according to the present invention for a two-bit mask n-channel ROM array. Figure 2 shows the effect on the threshold voltage of a two-bit mask n-channel ROM. This is achieved in particular with four memory units. The first memory unit, memory unit 00, has no bit code ion implantation, and is the initial low threshold voltage memory unit. The initial threshold voltage of the memory cell is at point 200 under zero back bias, and as the back gate bias voltage increases to 1 volt, 3 volt, the threshold voltage will be offset by its corresponding negative channel. Press up to point 201. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Notes on the back of the poem before reading #Fill this page) The second memory unit, remembering 100 million units, with a single shallow bit code ion implantation, boron ion concentration 2xl014cm_2, ion Planting energy of 150KeV. The initial threshold voltage of the memory cell is at point 202 at zero back bias. With a back-gate bias of 3 volts, this threshold voltage will rise to point 20 3. The third memory unit, remembering 100 million units, has a single deep bit code ion implantation, with an ion concentration of 9.3 × 10 4 cm · 2, and an ion implantation energy of 2000 KeV. The

1B i Paper size General Chinese National Standard (CNS) A4 specification (210X297 mm) " Μ B7 ^ 21793 V. Description of the invention (\ xi) The initial threshold voltage of the memory unit is at zero back bias at point 204 on. When the back bias voltage is 3 volts, the threshold voltage will rise to point 205 »The last memory cell, memory cell 11 has a combination of shallow bit code ion implantation and single deep bit code ion implantation. The initial critical voltage of the memory cell is at point 206 with zero back bias. With a back-gate bias of 3 volts, this threshold voltage will rise to point 207. As shown in Figure 2, the four memory cell types can get good level-to-level differences. The effect of the back gate bias on the fourth-order photomask ROM memory cell is also very clear. Adding a 2 volt back gate bias, the level-to-level difference varies from less than about 1 volt per billion cells to about 2 volts per memory cell. The shift of the threshold voltage is mainly because the overall doping profile of the two-bit ROM memory cells is changed by ion implantation. Figure 3 shows the doping profile of the ion implantation combination used in the two-bit ROM memory cell array in Figure 2. For memory cell 00, the vertical doping profile is represented by curve 301. For memory cell 01, the vertical doping profile is represented by curve 32. For the memory cell u, the vertical doping distribution is represented by the curve 303. A higher surface doping concentration in the memory cell π results in a higher threshold voltage at zero back gate bias. Moreover, the difference in surface doping concentration has a considerable impact on the bulk effect of these memory cells. Therefore, the large back-to-gate bias will produce a large level-to-level difference, giving the four memory cell types. Therefore, by adjusting the dose and energy of the ion implantation, the fourth-order photomask ROM memory unit can be implemented using only two photomasks. In addition, by adding 19 paper sizes to the Chinese national standard (CNS > A4 size (210 X 297 km)), the note on the back page is ordered by the Central Standards Bureau of the Ministry of Economic Affairs, and printed by the Ministry of Economic Affairs. Printed by Beige Consumer Cooperative Co., Ltd. 421793 A7 B7 V. Explanation of the invention (No) Gate bias, the noise margin will increase due to the difference in the ontological effects encountered by the four memory cell types. Table 2 lists when n = 3, or a combination of three-resolution bit-code ion implantation of the selected 100 million cell channels, multiple bits per memory cell. According to the assumed relationship, three-bit code ion implantation (N = 3), the number of memory cell types is S = 23 = 8. As shown in Table 2, the assumed relationship is also true for n = 3. For the example shown in Table 2, combining the three-bit code ion The implantation and the first channel ion implantation provide eight hundred million cell types. This combination is applied to a three-bit order memory array. For some embodiments of the present invention, the first-bit code ion implantation is better than the second-bit. Meta code ion implantation and third digit code The sub-planting has a smaller projection range. The second-bit code ion implantation has more ion implantation ions than the third-bit code ion implantation. The projection range of the second-bit code ion implantation and The third bit code ion implantation is the same. The first memory unit type 000 has only the first channel ion implantation, that is, there is no other bit code ion implantation. The second memory unit type 001 has another The first bit code is ion implanted. The third memory cell type 010 has another second bit code ion implant. The fourth memory cell type 011 has another third bit code ion implant. The fifth memory cell type 100 has another first bit code ion implantation and another second bit code ion implantation. The sixth memory cell type 101 has another first bit code ion implantation and another third bit code ion implantation. Planting: The seventh memory unit type 110 has an additional second 20 This paper size is applicable to China National Standard (CNS) A4 specifications (2! OX297 male shovel) ---------- I (Poem First M 'read the notes on the back! ^ Fill out this page)-Order 4

3 S 7 7 Λ Β V. Description of the invention (\ β) Meta code ion implantation and another third bit code ion implantation. The eighth memory cell pattern 111 has another first bit code ion implantation, another second bit code ion implantation, and another third bit code ion implantation. Further analysis shows that the s = 2 · 'relationship is valid for any multi-level memory array, where η is a positive integer. Therefore, because the use of asymmetric memory cells greatly reduces the reading error of the drain current in the memory array, the increased density advantage in the multi-level memory array is severely limited by the ion implantation process of the bit code ion implantation. (Please read the note on the back of $ ^ — ^ Fill this ") Equipment _ Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, the first channel ion implantation first ion code ion implantation first ion code ion implantation The first digit code ion implanted memory unit type: Ν NN 000 Υ Υ NN 000 1 Υ Ν YN 010 Υ Ν NY 011 Υ Υ YN 1 00 Υ Υ NY 101 Υ Ν YY 1 10 Υ Υ YY 1 1 1 Three digits Number of ions implanted in meta-level memory cell bit code = 3 = n Number of memory cell types = 2 " = 8 Table 2 21 This paper size applies to China National Standard (CNS) specifications (210 X 297 mm) 42179 3 Β7 V. DESCRIPTION OF THE INVENTION The diagram in FIG. 4 shows the relationship between the drain read current and the threshold voltage for a three-bit order memory cell with eight different bit codes, that is, it has a selection group including eight different bit codes. In this example, the type of each memory cell can be distinguished from the different types of bat- tery cells by reading the drain current at a given voltage. As shown in Fig. 4, the memory cell current / voltage characteristic 400 includes the highest drain read current and the lowest threshold voltage. Moreover, for the three-bit-order memory cell array Π 1, its memory cell current / voltage characteristic 435 includes the lowest drain read current and the highest threshold voltage. Figure 5 provides a schematic cross-sectional view of a symmetric hundred million cell 500 in the conventional technology. Figure 5 also shows the equivalent circuit symbols used in the symmetric memory cells shown in Figures 14 and 15 below. The symmetric memory cell 500 includes a gate 505, a conventional drain 510, and a source 515. The gate has a first side 520 and a second side 525. The gate electrode 505 is on the gate oxide layer 530. The conventional drain electrode 510 is on the first side 520 of the gate electrode, and under the rubidium oxide layer 530. FIG. 5 also shows a circuit symbol 550 of a conventional symmetric memory cell. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Figure 6 provides a schematic cross-sectional view showing an asymmetric multi-level memory unit 600 in the embodiment of the present invention. Figure 6 also shows the equivalent circuit symbols used in the asymmetric multi-level memory cell shown in Figure 15 below. The asymmetric multi-level memory cell 600 includes a gate 505, an asymmetric drain 610, and a source 515. The gate has a first side 520 and a second side 525. The gate electrode 505 is on the gate oxide layer 530. The gate oxide layer has a top. 22 This paper scale applies the Chinese National Standard (CNS) A4 specification (2IOX297 mm) 42179 3 at B7 V. Description of the invention (tA) The asymmetric drain 610 is on the first side 5 20 of the gate 5 05 and is on the gate Under the polar oxide layer 530. The source electrode 515 is on the second side 525 of the gate electrode and under the anode oxide layer 530. The first spacer 620 is on the gate oxide layer 530 and is adjacent to the first side 5 20 of the gate 505. The first spacer 620 has a first spacer width on top of the gate oxide layer 530. For some embodiments, the second spacer 625 is on the gate oxide layer 530 and is adjacent to the second side 525 of the gate electrode 505. For some embodiments of the invention, the width of the first spacer 620 is in the range of 0.05 micrometers to 0.20 micrometers. Embodiments of the invention have a first isolation width of 0.12 micrometers. Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics. The asymmetric drain 6 1 0 of the asymmetric multi-level memory unit 600 is laterally spaced by the offset region 63 0 and the gate 505. Fig. 6 also shows the equivalent circuit symbol 6S0 of the asymmetric multi-level memory unit 600. The shaded area to the left of the gate represents the offset compensation area 1030, which is formed between the asymmetric drain 610 and the channel 1020, and is discussed in the following description with reference to FIG. The following describes a method for forming an asymmetric memory cell: The first embodiment of the present invention includes a method for forming an asymmetric multi-level billion-count cell. For adjusting the threshold voltage of the memory cell channel and forming the gate electrode 23 This paper is applicable to the national standard (CNS) of the 4th secret (210X297) 褒 " " ^ ~ 421793 A7 —_ Zhu ·? V. Invention Explanation (The key steps after the oxide layer will be described below. FIG. 7 is a first schematic cross-sectional view of an asymmetric multi-level memory cell fabrication layer 700 after depositing a gate light mask layer 720 in a first group of embodiments of the present invention Figure 7 shows the memory cell fabrication layer after the gate oxide layer 530 is deposited on the base material 7 10. The first conductive layer 715 is also deposited to form the gate 505 and the gate mask layer is deposited. The first stage of 720. The first stage as the deposition of the gate mask layer 72 is generally a dielectric, and silicon nitride has been successfully used as the deposition of the gate mask layer 720. 'Figure 8 is the present invention In the first embodiment, after the gate electrode 505 pattern is formed with a bit line mask, a second cross-sectional view of the asymmetric multi-level memory cell fabrication layer 800 is formed. Define the pattern on the gate 505 A pattern gate polar mask layer 820 is formed. Printed in Figure 9 by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, is a schematic diagram of the third cross section of the asymmetric multi-level memory cell fabrication layer 900 in the first embodiment of the present invention, showing Ion implantation 910. A drain photoresist mask 91 5 has a pattern defined on the drain region of the substrate 710, and a portion of each pattern 閛 aurora mask layer 820 is laterally adjacent to the drain region. Therefore, the memory cell substrate 7 The drain region of 10 receives only a small amount of impurities from the first ion implantation 910. The first ion implantation 910 emits impurity ions into the source 5 1 5 region of each asymmetric multi-level memory cell 600 , Because the source 515 area is not covered by the drain photoresist mask 915. The amount of impurities from the first ion implantation 9 10 to the gate 505 is very small, because the pattern gate photomask layer 24 This paper size applies to Chinese national standards (CNS) Λ4 specification (210X29? Male) 4217 9 3 A7 B7_ _ V. Description of the invention (> >) 820 absorbs most of the impurity ions, otherwise it will shoot to the gate electrode 505. The first ion The planting 910 is aligned with the gate 505. It should be noted that the first separation The planting 910 is performed using an asymmetric photomask, and before the first spacer 620 is formed. FIG. 10 is a fourth schematic cross-sectional view of the asymmetric multi-level memory cell fabrication layer 1 000, which shows a memory cell according to an embodiment of the present invention. There are spacers on both sides of the gate in the array. Figure 10 also shows the second ion implantation 010. The central government bureau of the Ministry of Economic Affairs printed a drain photoresist mask 915 on the second ion implantation 1010 It was previously removed. The first spacer 620 was formed before the second ion implantation 1010. The first spacer 620 is generally composed of dioxide, but may be composed of other dielectric materials. The first spacer 620 extends upward from the gate oxide layer 530 to the top of the patterned gate mask layer 820. For the asymmetric drain 610 of the asymmetric multi-level memory unit 600, a second ion implantation 1010 is performed. For some embodiments, the second ion implantation 1010 is performed only on the asymmetric drain 610. For other embodiments as shown, the second ion implantation is performed on the asymmetric drain 610 and source 515 of each asymmetric multi-level memory cell 600. The second ion implant 1010 is aligned with the first spacer 620. For some embodiments shown in Fig. 10, the second spacer 625 is adjacent to the second side 525 of the gate 505. For the implementation with the second spacer 625 25 1 This paper size applies the Chinese national standard (CNS specification (210X297 mm)) Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperation Du printed 4 2ίΤ9? Λ 7 _7 Β7__ V. Description of the invention ( Ii) For example, the second spacer 625 was formed at the same time as the first spacer 620, that is, before the second ion implantation 1010. For these examples, the second ion implantation 1010 is more The asymmetric drain 6 1 0 and source 5 1 5 of the second-order memory cell 600. For some embodiments, the first spacer 620 (and the second spacer 625 of the embodiment having the second spacer 625) ) Includes an oxide layer formed by a TEOS deposition process. Then a first spacer 纟 20 (and a second spacer 62 of the embodiment having the second spacer 625) are defined by wet etching. ). For the embodiment having the second spacer 625, the second spacer 625 is formed at the same time by the same process as the first spacer 620. The channel 1020 in the substrate 710 is disposed near the gate oxide layer 530 And align with gate 5 05. Channel 1 020 from The pole 5 1 5 extends upward toward the asymmetric drain 610. The channel 1020 does not extend to the asymmetric drain 610 in all directions. Instead, the offset region 1030 in the substrate is placed between the channel 1020 and the asymmetric drain 610. The offset region 1030 is also close to the gate oxide layer 530. The offset region 1030 is a key feature of the asymmetric multi-order billion cell 600 of the present invention. The second ion implantation 1010 is directed toward the surface of the asymmetric drain electrode 610. The exposed asymmetric drain electrode 610 surface has a width defined by the top area of the gate oxide layer 53. The top of the gate oxide layer 530 is still unadjacent. 26 I paper size applies Chinese National Standard (CNS) Λ4 specifications. (2 丨 〇 > < 297 mm Ί 嫌 ^ — (Please read the notes on the back _ fill out this page first) Order 421793 Λ7 B7 V. Description of the Invention Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A spacer 620 is covered by the asymmetric drain 610. For some embodiments, the second ion implant is performed on the source 515 and the asymmetric drain 610. The second ion implant is 1 0 1 0 impurities The final position is from the area of the asymmetric drain 610, horizontal The area of the asymmetric drain 610 is projected by the second ion implant 1010. Therefore, the width of the first spacer 620 is larger than the offset region 63. For some embodiments of the present invention, the The bias region is fifty percent (50%) greater than the width of the first spacer 620. For some embodiments of the present invention having a width of the first spacer 620 in the range of 0.05 micrometers to 0.20 micrometers, the bias compensation region 630 Will be in the range of 0.02 microns to 0.20 microns. The offset region 1 03 0 is adjusted to prevent source current, as discussed in the following multi-level memory cell with source current suppression section. The first spacer 620 ensures that the offset region 1030 will not receive a large amount of impurities from the second ion implant 1010. The second spacer 625 is not used by some embodiments of the present invention because the second spacer 625 does not affect the offset region 1 030. However, the second spacer 625 provides symmetry to the gate 505 and simplifies the process, so it is used for other embodiments of the present invention, as shown in FIG. The second ion implantation 1010 does not shoot into the side close to either side of the source electrode 515.

A The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 42179 3 Λ7 _ B7 5. Description of the invention (A) Source 515 area. The ions from the second ion implantation 1010 only enter the central portion of the source electrode 515, because the second ion implantation 1010 absorbs ions that will be incident on the ion implantation near the side of the source electrode 515. The second ion implantation 1010 is unlikely to affect the source electrode 515 because the patterned gate mask layer 820 absorbs most of the ion implantation ions that will be incident on the source electrode 515. FIG. 11 is a fifth cross-sectional schematic diagram of an asymmetric multi-level billion-count cell-manufacturing layer 1100, which shows a memory cell-manufacturing layer after removing the pattern gate reticle layer 820. in the embodiment of the present invention. The first spacer 620 and the second spacer 625 extend upward beyond the top of the gate electrode 505. FIG. 12 is a sixth cross-sectional diagram of an asymmetric multi-level memory cell fabrication layer 1200, showing a memory cell fabrication layer after the second conductive layer 1210 is removed in the embodiment of the present invention. Then, a pattern of the second conductive layer 1210 is defined, and word lines are formed in the memory cell array. The following is a description of a multi-level memory cell with limited source current: The key advantage provided by the asymmetric multi-level memory cell 600 is that it will suppress the source 5 1 5 reading current, making the asymmetric multi-level memory cell The 600 can only be read in one direction. For some embodiments of the present invention, the asymmetric multi-level (MOS) memory cell 600 is a reinforced transistor and is normally off. 28 This paper size applies to China National Standard (CNS) A4 specification (2 丨 0X297 mm) A7 421793 ____B1____ 5. Description of the invention (1) Asymmetric multi-level memory unit 600 is in the integrated circuit. Each asymmetric multi-level memory cell 600 has the limitations discussed above for the asymmetric memory cell in this specification. The gate 505 has a first gate voltage and is a positive voltage for the MOS memory cell. The gate oxide layer 53 0 acts as a dielectric layer, and restricts the carrier flow between the channel 1020 and the gate 505. The high voltage of the gate 505 causes electrons in the channel 1020 to flow to the gate oxide layer 530. These electrons gathered near the channel 1020 / gate oxide layer 53 0 interface form an empty region in channel 1 020. The channel 1020 near the gate oxide layer 530 has a higher electron concentration, which is sufficient to conduct electrons across the channel 1020. . Because the gate 505 extends to the source 515, and the channel 1020 is aligned with the gate 505, the channel 1020 extends from all directions to the source 515. However, the asymmetric drain 610 is laterally spaced from the first side 520 of the gate 505 by the offset region 630. Therefore, the channel 1020 corresponding to the first side 520 of the gate electrode 505 is also laterally separated from the asymmetric drain electrode 610 by the offset region 630. The region 710 of the substrate near the gate oxide layer 530 and between the channel 1020 and the asymmetric drain 610 is an offset region 1030. The offset region 1030 has an initial conduction state according to the carrier concentration in the P-type substrate 7 10, as realized by implantation with a low-dose critical voltage ion. The offset area 1030 is at the gate electrode 505 29 This paper wave is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) II n ^. 1 (Please read the notes on the back before filling in this I) Central of the Ministry of Economy Standards Bureau Consumer Consumption Cooperatives Seal of the Ministry of Economic Affairs Central Standards Bureau Employee Consumption Cooperatives Seal 42IT93 Λ7 Β7 ______ 5. The first side of the invention description (7 ^) is 5 2 0. The offset region 1 03 0 cannot be controlled by the gate voltage because the gate 505 is not on the offset region 1030. The gate voltage will not attract enough electrons to the offset region 1030, but an empty region will be formed in the offset region 1030. Another statement of the offset region 103 0 is that the channel 10 20 “disappears” in the offset region 103. The bias compensation region 103 is adjusted to maintain its initial conduction state in response to the gate voltage. If no other voltage is applied in addition to the gate voltage, the current across the offset region 1 030 will be suppressed, and the asymmetric multi-level memory cell 600 will remain non-conductive. FIG. 13 shows a current-voltage diagram of an asymmetric multi-level memory cell 600 according to an embodiment of the present invention. The curve is provided to an asymmetric multi-level memory cell 600 having a width of the first spacer 620 and the second spacer 625, and the range is from 0.10 micrometer to 0.12 micrometer. The number is an asymmetric multi-level memory cell 600 corresponding to a width of 1.0 micron, and an asymmetric multi-level memory army 600 having a length of 0.32 micron. The bit line load effect on the asymmetric multi-level memory cell 600 represented by FIG. 13 is 8 kiloohm. As described above, the asymmetric multilevel memory cell 6Ό0 is adjusted to suppress the source read current. The suppression effect can be compared by comparing the drain read current of the asymmetric multi-level memory cell 600 at the drain voltage (the source voltage is zero) with the asymmetric multi-level memory cell 600 at the source voltage (the drain voltage is zero). Source 30 This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 cm) (Please read the note on the back # '. Fill out this page; >. Binding. Order 421793 Λ7 B7 (V s = 0) / I (V d = 0) 5. Description of the invention (^)

Read the current and be measured, or. Proportion is also used as a measure of the degree of freedom of misreading the memory cell type of a particular memory cell. The degree of freedom of misreading of memory cell types will improve as the number of measurements increases, but it depends on other factors, such as the current-voltage characteristics of each billion cell type in the memory array, and each memory Critical voltage difference between unit types. In terms of current-voltage characteristics (critical voltage), the closer the one type of asymmetric multi-level memory cell 600 is to another type of asymmetric multi-level memory cell 600 in the same array, the higher the I-scale factor will be to ensure asymmetry. The multi-level memory unit 600 is correctly read. · For an asymmetric multi-level memory cell 600 with a 0.12 micron spacer, Figure 13 shows a source voltage of 0.5 volts and a source read current of about 9 microamperes, such as point 1301. For a source voltage of 0.5 volts, the drain read current is about 20 microamperes, such as point 丨 3 丨 丨. At the voltage of 0. 5 volts, for this memory cell, the ratio of the degree of freedom of misreading of the memory cell type is IiVs = D > / I (Vd-e >, the ratio is about 2.22. Object 620 and asymmetric multi-level memory cell 600 with a 1.0 volt source read voltage, its source read current is about 16 microamperes, such as point 1302. For a 1.0 volt source voltage, its drain read The current is about 45 microamperes, such as point 1312. Under the voltage of 1.0 volts, the degree of freedom of misreading of the t memory cell type is 31 for this memory cell. This paper size applies the Chinese National Standard (CNS) A4 specification (锖Read. Notes on the back t Printed 42'U93 Λ7 _B7 printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The ratio of the invention description (/) is about 2.81 »For the first spacer 620 with a width of 0.12 microns and 1. Asymmetric multi-level memory cell 600 with a volt source read voltage has a source read current of about 19 microamperes, such as point 1 303. For a 1.5 volt source voltage, its drain read current is about 68 microamperes, such as Point 1313. At 1.5 volts, for this For the memory cell, the ratio of I (Vs-D / I (Vd =.) Of the degree of freedom of misreading of the memory cell type is about 3.58 »Therefore, as shown in FIG. In the embodiment, a higher drain voltage will obtain the most accurate reading current. The data shown in Figure 13 shows that for a drain voltage of 1.5 volts, it is clearly shown that the accuracy will vary with the drain voltage. For an asymmetric multi-level memory cell 600 having a width of the first spacer 620 of 0.12 microns, FIG. 13 shows that at a source voltage of 1.5 volts, its source read current is about 59 microamperes, such as Point 1323. Under the 1.5 volt drain voltage, its drain read current is about 85 microamperes, such as point 1 33 1. At 1.5 volt voltage, for this memory cell, the freedom to remember the wrong type of the hundred million cell type The ratio of I (vs-e > / I (Vd = < M) is about 1.44. However, for an asymmetric multi-order billion cell 600 having a width of the first spacer 620 of 0.12 microns, the size of the metric The improvement is not as large as this ratio, but it should be noted that for smaller memory cell sizes, the The width of the first spacer 6 20 will have a significantly reduced memory cell type misreading. Based on 32. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 male shovel). Print Λ7 ____B? V. Description of the invention (W) ~~ " The width of the first spacer of 0,12 microns and the projection data related to the size of the memory cell, hoping that the asymmetric memory cell can effectively reduce the data. The memory cell type of the first-isolator with a width of 62 micrometers ranging from 5 micrometers to 0.20 micrometers was misread. When a sufficiently large drain voltage is applied to the asymmetric multi-level memory cell 600, electrons will flow from the substrate 710 and the channel 1020 to the offset region 1030 until the empty region is established in the offset region 1030 and the memory cell Conducting electrons, passing through the bias zone 1 30 to the drain. As shown in Fig. 13, a drain voltage of 1.5 volts provides a drain read current of 68 microamperes for a width of the first spacer 620 of 0.12 micrometers. This current indicates that a drain voltage of 1.5 volts is sufficient to establish an offset region 1030 in the offset region 1030. For a source voltage of 1.5 volts and a width of the first spacer 620 of 0,12 micrometers, the source read current is 19 microamperes, which is much lower than the drain read current of 68 microamperes. The lower source read current indicates that the offset region 1030 is adjusted to maintain the initial on-state of the offset region (ie, enhanced-off) to reflect a source voltage of 1.5 volts. The following describes an integrated circuit with a source current limiting memory cell. A third group of embodiments of the present invention provides an integrated circuit including an array of hundreds of millions of cells. The memory cell array includes an asymmetric (source current suppression) multi-level memory cell 1 500, as shown in Figure 15, which is designed as an adjacent memory sheet '33 -------- ^-I ^- -(Please read the notes on the back first! ^ Fill in this page) D. " < * This paper size is applicable to China National Standard (CNS) A4 specification (210X297 cm) A7 42179 3 ____B7 V. Description of the invention (guide (Square) The elements all share a common source. In this design, the reading of the asymmetric drain current of the memory cell will be more accurate than that of the memory array containing the symmetric memory cell 500, because the source current of the adjacent asymmetric multi-level memory cell 600 is greater than that of the read memory cell. The asymmetric drain current is much lower, such as the multi-level memory cell with limited source current shown in FIG. 13 above. The integrated circuits provided in these embodiments generally include a plurality of interconnected memory cell arrays with asymmetric multi-level memory cells 1500.獒 The memory cell array contains memory cells. The memory cell contains a transistor having a channel, and the channel is in a channel region of the substrate. Memory cells Selected asymmetric multilevel memory cells in the array can store multi-bit data. The memory cell array further includes a word line and a bit line. Word lines and bit lines are coupled to memory cell columns and memory cell rows in the memory cell array. A voltage is applied to the memory cell row and the memory cell row in the memory cell array to provide a printing method for the Central Samples Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs to read the data stored in the memory cell array. The word line includes a first integrated circuit pattern layer. The bit line includes a second integrated circuit pattern layer. FIG. 14 shows a memory cell array including a conventional symmetric memory cell 1400. FIG. 14 shows a memory cell column of a single selectable memory cell within the first word line 1410. The corresponding memory band left selection line 1 4 1 5 is under the first word line 1410, while the corresponding memory band right selection line 1420 is 34. This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 Gongcheng> Economy Printed by Deng Central Bureau of Standards Consumer Cooperatives 421793 λ7 Λ7 — _B? _____ 5. Description of the invention (7 ^) on the first word line 14 10. Each memory band selection line is coupled to the transistor column. Contains conventional technology The memory cell array of the symmetric memory cell 1400 cannot provide an accurate symmetrical drain read current. For example, as shown in FIG. 14, if the first memory cell 1405 on the first word line 1410 is read, the The word line 1410 and the memory card left selection line 1415 will be at high voltage, while the memory belt right selection line 1420 will pass from the sense amplifier 1430 to the first memory unit. 1405 at the low voltage first current 1425, the second memory unit 1435, and flow to ground 1 440. Sense amplifier 1 430 has a sense amplifier wire 1445, which is used to connect the left selection line 1415 of the memory band, the right selection line 20 of the memory band, and the first word line 1410. The sense amplifier wire 1445 has Side (left side of Fig. 14) and second side (right side of Fig. 14). The ground 1440 has a ground wire 1450 for connecting the left selection line 1 41 5 of the memory band, the right selection line 1 420 of the memory band, and the first A word line I 4 1 0. The ground wire 1 450 has a first side and a second side. The first bit line 1 455 is close to the ground wire 1450 and is on the first side of the ground wire 1450 = the first bit line 1455 is also close to the sense amplifier wire 1445 and is on the second side of the sense amplifier wire 1445. The first memory unit 1 405 is between the sense amplifier wire 1445 and the first bit line 1 45 5. The second Billion Unit 1435 is the 35th line selected on the left side of the memory tape. The paper size is in accordance with Chinese National Standards (CNS > A4 format (210 × 297 mm). Please read the notes on the back first and fill in this page.) Printed by the Bureau of Standards, Consumer Cooperatives 421793 B7 V. Description of the invention (? 1415, and between the first bit line 14S5 and the ground wire 1450. The third record billion unit 1460 is on the first word line 1410 , Between the first bit line 14S5 and the ground wire 1450. The three memory units 146〇 provide a first current 1465 path, and between the first memory unit 1405 and the ground 1440, the second memory unit 1 4 3 5 will be bypassed. If the third memory unit i 4 6 〇 is of low threshold voltage The memory unit may be erroneously read by the first memory unit 1405, and the first memory unit 1405 may be read as a different, more conductive memory unit type. Therefore, the reading current of the first memory cell 1 405 depends strongly on the threshold voltage of its neighboring memory cell, and the third memory cell H60. The relative effective resistance 値 (R146e) of the third memory unit 1460 and the relative effective resistance 値 (R 1 4 3 5) of the second memory unit 1435 will determine that the first memory unit 1405 is misread by the memory unit type Take the situation. The reading current of the first memory cell 1405 is proportional to (R, 4 3 5 + R, 46D) / (R | 4 3 5 X R | 46 .;). Except for R146. Greater than RI435, otherwise the third memory unit 1460 of the symmetric memory unit will cause the memory unit type to be misread because (R1435 + RI46.) / (Rl4 3 5 X Rl46D) is less than κ · 1; ί: 35. For the above two-bit memory array example, the third memory unit 1460 with a small resistance (low critical voltage) may cause the first record that is less conductive. 36 This paper is applicable to the Chinese National Standard (CNS) A4 specification (2丨 0X297mm1 {Please read the precautions on the back before filling this page). _ 421793 A7 B7 V. Description of the Invention (Party ^) The memory unit 1405 was misread as a more conductive memory unit. For example, referring to Fig. 1, the memory unit will be misread as 10 memory unit, 0 memory unit or 00 memory unit. Similarly, the 10 memory unit will be misread as 0 1 memory unit or 00 memory unit; or 01 memory unit will be misread as 00 memory unit. FIG. 15 shows a memory cell array including asymmetric multi-level memory cells 1 500, which is an embodiment of the third group of the present invention. The two-bit memory cell on the second word line 1 505 is an asymmetric multi-level memory cell 600 ° The reading current of each asymmetric multi-level memory cell 600 is accurately read in a single direction, because asymmetric multi-level memory cells The current in the order-million cell 600 from the asymmetric drain 6 1 0 to the source 5 1 5 is more than that from the source 5 1 5 to the asymmetric drain 610. As mentioned above, there is a limited source. Discussed in Multi-level Memory Cells with Extreme Currents. The source current suppression provided by the asymmetric multi-level memory cell, when the ratio of I, .〇) / A (Vd * 0) is greater than 2.5 or I (Vd =. 〆 ”, please read the note Ⅰ Printed by 40% of I (Vs = (0), the work co-operative consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is particularly useful for memory cell arrays. Unlike the symmetric memory cell 500 in the traditional memory array 1 400, each non- The accurate reading of the symmetric multi-level memory unit 600 is provided when the asymmetric multi-level memory unit 600 is sensed from the appropriate array end. 37 This paper size applies the Chinese National Standard (CNS) Α < 4 specifications ( 2 丨 〇Χ297mm) 4 21793__b7__ 5. Description of the Invention (10,000 V?) There are five array terminals shown in Figure 15. Each array terminal provides two functions. According to the precise reading of the current flow of the selected memory cell Orientation 'Each associated array end is considered a ground or sense amplifier. The three array ends used in this discussion include the first array end 1510, the second array end 1512, and the third array end 1514. An array end 1510 has a first array end Line 1 5 1 6, the second array end 1 5 1 2 has a second array end lead 15 18, and the third array end 1514 has a third array end lead 1 520. Each array end lead has a first side (FIG. 1 5 left) and the second side (right of FIG. 15). The second array-side lead 1 5 1 8 is on the second side of the first array-end lead 1 5 1 6 and is the first on the third array-end lead 1520. The second bit line 1 522 is between the first array end wire 1 5 1 6 and the second array end line 1 5 1 8. The third bit line 1 524 is the second array end wire 1 5 1 8 and the third array-side wire 1520. The fourth memory cell 1 525 is on the second word line 1505, and is between the first array-side wire 1516 and the second bit line 1522. To read the fourth For the memory unit 1525, the first array end 1510 is used as a sense amplifier, the Central Standards Bureau of the Ministry of Economic Affairs is responsible for printing and the second array end 1512 is used as a ground. The second word line 1505 and the left side of the memory band are selected. 1415 is a high voltage, and when the memory band right selection line 1420 is a low voltage, the fourth memory unit 152S is accurately read. These voltages Causes the second current 1 530, from the first array end 1510, through the fourth memory cell 1 525, the fifth memory cell 1 535, and to the second array end 1512. The fifth memory cell 1 5 3 5 Select the line 14 1 5 on the left, and apply the Chinese National Standard (CNS) A4 size (210X297 mm) on 38 paper sizes. 421793 A7 B7 Printed by the Shell Department of the Central Standards Bureau of the Ministry of Economic Affairs. )) Between the second bit line 1 522 and the second array-end wire 1 5 1 8. The sixth memory cell 1 540 is adjacent to the fourth memory cell 1 525 on the second word line 1 505. The sixth memory cell is between the second bit line 1 522 and the second array-end wire 1 5 1 8. The sixth memory unit 1 540 and the fourth memory unit 1 525 share a common source 515. The current passing from the sixth memory cell 1540 to the second array terminal 1512 is not large enough to cause the memory cell type to be misread. This error can be avoided because the current from the source 5 1 5 to the asymmetric drain 6 1 0 in the sixth memory unit 1540 is much smaller than the current from the asymmetric drain 610 to the source 515 in the fourth memory unit 1525. Current, and the actual current will flow from the source 5 1 5 of the sixth memory unit 1 540 to the asymmetric drain 610, causing the memory cell type of the fourth memory unit 1525 to be misread. For example, an asymmetric multi-level memory cell 600 with a 0.1 2 micron offset region, as discussed in the above-mentioned multi-level memory cell with limited source current, has I < vs =.比例 I (vd = 〇) ratio is about 3.58 at 1.5 volts. Therefore, even if the critical voltage difference 不同 of different memory cell types in a 500-million array containing asymmetric multi-level memory cells 1500 is only half of the critical voltage difference 记忆 of a conventional memory cell type in a symmetric memory cell 1400, including asymmetric multi-level The memory array of memory unit 1 500 has a 50% chance of misreading the memory cell type in the traditional symmetric memory unit 1400, which is half the chance of misreading the 39 million unit type. 39 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 (Public note) Please read 'Notes on the face of the bookbinding' ~ ί% A7 421793 B7 ~~~ "The third current I545 needs to read out the sixth record accurately" " memory list τϋ V. Description of the invention (pair) 1 5 40. The second array end 1512 is used as a sense amplifier, and the first array end 15 1 0 is used as a ground. The third current 1 545 is selected according to the high voltage of the memory band right 420 and the high voltage of the second word line 1505 and the memory band. The left selects the low voltage of line 1415 and flows. A third current 1 545 flows from the second array terminal 1512 through the sixth memory unit 1540, and passes through the seventh memory unit 1550 to the first array terminal 1510. The central standard of the Ministry of Economic Affairs The local co-operative consumer cooperative prints the third current 1545, which is the opposite of the second current 1 530 corresponding to the sixth memory unit 1 540 and the fourth billion unit 1 525. For the third current 1545, the fourth The memory unit 1525 is adjacent to the billion-bit memory unit that performs the reading operation, that is, the sixth memory unit 1 540. The sixth memory unit 15 40 and the fourth memory unit 1 525 are both on the second word line 1 505. The fourth The memory cell 1 525 does not allow sufficient current to pass to the first array terminal 1510, which causes the memory cell type to be misread. This error can be avoided because the fourth memory cell 1525 runs from the source 515 to the asymmetric drain 610 The current is much smaller than the current from the asymmetric drain 610 to the source 515 in the sixth memory cell 1 540, and the actual current will flow from the source 515 to the asymmetric drain 610 in the fourth memory cell 1 5 25 , Causing the sixth memory cell type 1 540 memory cell type to be misread. The eighth memory cell 1560 is on the second word line 1 505 and is between the third bit line 1524 and the third array end wire 1 520 Requires a 40th paper size for China Standard (CNS) Α4 is present (210X297 public avoidance) Printed by the Consumers' Cooperative of the 4-Central Standards Bureau of the Ministry of Economic Affairs 42 179 3 A7 B7 5. Invention Description (y?) Current 1 5 55 to accurately read the eighth memory unit 1 560. The third array terminal 1 5 1 4 is used as the sense amplifier, and the second array terminal 1 5 1 2 is used as the ground. The fourth current 1 555 is based on the high voltage of the left selection line 1415 and the second word line 1505 of the memory band. And the memory band right selects the low voltage of line 1 420 and flows. The fourth current 1 5 5 5 flows from the third array terminal 15 14 through the eighth memory cell 1560 and passes through the ninth memory cell 1 565 to the second array terminal 1512. The ninth memory cell 1 565 is on the left selection line 1415 of the memory band, and is between the second array end wire 1 5 1 8 and the third bit line 1 524.

I The tenth memory cell 1 570 is adjacent to the eighth billion cell 1560 on the second word line 1 505. The tenth memory unit 157G is between the third bit line 1524 and the second array-end wire 1 5 1 8. The tenth memory unit 1 570 will not allow sufficient current to pass through the second array terminal 1512, which will cause the memory unit type to be misread. This error can be avoided, because the current from the source 5 1 5 to the asymmetric drain 6 1 0 in the tenth memory cell 1 570 is much smaller than the current from the asymmetric drain 610 to the source 515 in the eighth memory cell 1560. Current, and the actual current will flow from the source 515 of the tenth memory unit 157 to the asymmetric drain 610, causing a misreading of the memory cell type. A fifth current of 1 575 is required to accurately read the tenth memory unit. 1 5 70, the second array terminal 1512 is used as a sense amplifier, and the third array terminal 1H4 is used as a ground. The fifth current 1575 is in accordance with the high voltage of the right selection line 142 0 and the second word line 1550 of the memory band and the low power of the left selection line 1 4 1 5 of the memory band. 4] This paper size applies the Chinese National Standard (CMS) A4 specification. (210X297 mm) -------- I ---- V (Please read the precautions on the back before filling this page) Order the A7 ___B7___ printed by the Staff Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs W) Press and flow. The fifth current 1 575 flows from the second array terminal 1512 to the tenth memory unit 1 570 and passes through the eleventh memory unit 1 580 to the third array terminal 1514. The eleventh memory unit 1 580 is on the right selection line 1420 of the memory band, and is between the third bit line 1 524 and the right selection line 1420 of the memory band. For the fifth current 1 575, the eighth memory unit 1 560 is adjacent to the memory unit performing the reading operation, that is, the tenth memory unit 1 570. The eighth billion cell 1560 and the tenth memory cell 1570 are both on the second word line 1505. The eighth memory unit 1 560 will not allow sufficient current to pass to the second array terminal 1 5 1 2, which will cause the memory unit type to be misread. This error can be avoided, because the current from the source 5 1 5 to the asymmetric drain 6 1 0 in the eighth memory cell 1 560 is much smaller than the current from the asymmetric drain 610 to the source in the tenth billionth cell 1570 515 current, and the actual current will flow from the pole 5 1 5 of the eighth memory cell I 5 60 to the asymmetric drain 6 1 0, causing the memory cell type to be misread. As shown in FIG. 16, the twelfth memory cell 1605 is on the left side of the fourth memory cell 1 525 on the second word line 1 05 05 and is adjacent. FIG. 16 also shows that the first selection transistor 1610 and the second selection transistor 1615 are on the left selection line 1415 of the recording band. The first selection transistor 1610 is directly under the twelfth memory unit 1605, and the second selection transistor 1615 is directly under the fourth memory unit 1525. The first selection transistor 1610 and the second selection transistor 615 are high Vt memory cells. The third choice is transistor. 42 _ This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -------- 71 #-t (Please read the note on the back first # (fill in (This page)

• 1T-. C Printed by 42trg3 A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (vl) The body 1620 is on the left selection line 1415 of the memory band, and is adjacent to the left of the first selection transistor 1610 . The fourth array terminal 1625 has a fourth array terminal wire 1 630. The fourth array-side wire 1630 is on the first side (left side of FIG. 16) of the first array-side wire 1516. Unless the memory array containing the asymmetric multi-level memory cell 1 500 has the characteristics discussed in this specification, the other sixth current 1 6 3 5 path will cause the memory cell type 1 625 of the fourth array end to be misread. If not blocked, the sixth current 163 5 will pass from the first array terminal 15 10 through the first selection transistor 1610, the second selection transistor 1615, and then to the second array terminal 1512. However, the sixth current 1635 can be effectively blocked by the high Vt memory cells (the first selection transistor 1610 and the second selection transistor 1615) on the path of the sixth current 1635. Fig. 16 also shows that the seventh current 1640, which is not blocked, may cause the memory cell type of the fourth array terminal 1625 to be misread. If the seventh current 1640 is not blocked, it will pass from the first array terminal 1510 to the third array transistor 1 620 to the fourth array terminal 1 625. However, when the fourth memory cell 1 525 is read, a bias condition is applied to the array terminal in the memory array instead of the second array terminal 1512, so that the seventh current 1 640 is blocked. The bias condition applied to the other array terminals, that is, the fourth array terminal 1625, is approximately equal to the voltage on the first array terminal 1510. Therefore, no current flows to the fourth array terminal 162. The second array end 1 5 1 2 43 This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297). (Please read the note ^^ on the back before filling this page.) Installation,? Τ_ 421793 Λ7 B7_____ V. Description of the invention (Sub-grounded to ensure that the fourth memory unit 1 525 can use the current path of dimension one. It is read out. The first array end wire 1 5 1 6 is connected down to the left side of the memory band 1 4 1 5 Bottom. When the first array end wire 1 5 1 6 extends beyond the left selection line 1415 of the memory band, the first array end wire 1516 is a bit connected to another memory array (also called a memory band) in the integrated circuit On-line. This connection allows the integrated circuit to use the same sense amplifier to perform read operations on more than one memory array in the integrated circuit. Some embodiments of the present invention include a method for reading a memory cell with an offset region. Method. The method includes providing a symmetric memory cell with an asymmetric drain 610 that is spaced from the channel 1020 by an offset region 630. Some such methods include providing an asymmetric multi-level memory cell 600 = Please Attention binding, it is printed by the Central Standards Bureau of the Ministry of Economic Affairs, and the cooperatives printed above are only the preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. Equal changes and modifications made in the scope are covered by the patent scope of the present invention. 44 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm).

Claims (1)

Λ 29 3 Α8 Β8 C8 D8 VI. Application for Patent Scope Printing by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperatives 1. A method for manufacturing a multi-level memory cell with asymmetric drain current, the memory array has a plurality of multi-level A memory cell, each multi-level memory cell includes a gate, a gate oxide, a channel, a drain, and a ytterbium, wherein the gate is on the gate oxide, the gate oxide has a top, and the channel is in a substrate. The drain is inside the substrate and on the first side of the channel, and the source is inside the substrate and on the second side of the channel, where the second side is opposite to the first side, the method includes: The source of the multi-level memory cell is implanted with a first ion, and the + first ion implant is aligned with the gate; on the first side of the gate of each multi-level memory cell, a first spacer is formed, The first spacer extends upward from the top of the gate oxide layer, the first spacer has a first spacer width on the top of the gate oxide layer, and the second spacer width is adjusted to provide an offset region, Between each multilevel memory cell Between the channel and drain; and each memory cell of the multi-stage drain electrode a first ion implantation, ion implantation and the second is aligned with the first spacer. 2. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 1 of the scope of the application, wherein the width of the first spacer is in a range of about 0.05 micrometers to 0.20 micrometers. 3. For example, the method for manufacturing a multi-level memory cell with asymmetric drain current in item 1 of the scope of the application, wherein the width of the offset region is greater than about 50% of the width of the first spacer (> 50%). 45 This paper is a Chinese standard (CNS) A4 size (210X297 mm). Please read the original binding. A8 Β8 C8 D8 ^ 21793 々, apply for a patent scope 4. If the scope of the application for the first item In the manufacturing method of a multi-level memory cell with asymmetric drain current, the first step of implanting the first ion includes the following steps: performing a first-channel ion implant on each channel of the multi-level memory cell; A multi-level memory cell channel of a selected group is ion-implanted with a first bit code; a second-bit code ion implantation is performed with a multi-level memory cell channel of a second selected group, the second bit code Ion implantation has a different projection range than the first bit code ion implantation: each multi-level memory cell has a -bit code, which is selected from a set of four different bit codes, four different Each bit code in the bit code corresponds to a specific combination of the first channel ion implantation, the first bit code ion implantation, and the second bit code ion implantation; Polar oxide layer A first conductive layer; define a gate pattern from the first conductive layer; obscured and the drain. 5. For the method for manufacturing a multi-level memory cell with asymmetric drain current in item 1 of the scope of the application, before the first ion implantation, the method further includes the following steps: Ion implantation of the first channel; n-bit code ion implantation of n selected multi-level memory cell channels, each of the n-bit code ion implantation is related to other η-46 paper sizes Applicable to China_Home Standard (CNS) Α4 specification (210X297 male) — one;; ----- Γ '·' 丨 ^ ------ 1T ----- Q (锖 Please read the note on the back first Please fill in this page for further details.) Employees' Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs printed 42 mouths. 9 3 B8 C8 D8. VI. Patent application 1 bit code ion implantation, with a different set of ion implantation characteristics; Each multi-level memory unit has a bit code, which is selected from the group of 2 different bit codes. Each bit code of the 2 different bit codes corresponds to the first channel. Specific combination of ion implantation and n-bit code ion implantation; formation of gate oxygen Depositing a first conductive layer; defining a pattern of the gate electrode from the first conductive layer; and covering the drain electrode. 6. For example, the method for manufacturing a multi-level memory cell with an asymmetric drain current in the first scope of the application, further comprising forming a second spacer on the second side of the gate, the second spacer being Extends upward from the top of the gate oxide. 7. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 4 of the scope of the application, wherein the width of the first spacer is in a range of about 0.0 5 μm to 0.20 μm. 8. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 4 of the scope of the application, further comprising the following steps after the second ion implantation: depositing a second conductive layer; and a definition The pattern of the second conductive layer "9. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 5 of the scope of the application, wherein the set of ion implantation characteristics includes a projection range 47 and & ^ China National Standard (CNS) A4 Specification (210x297 mm) — (Please read the notes on the back before filling this page) • Equipment · Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 421793 A8 B8 C8 D8 VI. Patent Application Range and number of ions implanted by the ion. 10. If you apply for a multi-level record with asymmetrical drain current in item 5 of the scope of the application (please read the precautions on the back first and then fill in this page). It is in the range of about 0.05 microns to 0.20 microns. • 1 1. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 5 of the scope of the application, further comprising the following steps after performing the second ion implantation: depositing a second conductive layer; And defining a pattern of the second conductive layer. «12. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 6 of the scope of the application, wherein the width of the first spacer is in the range of about 0.05 micrometer to 0.20 micrometer. 1 3. The method for manufacturing a multi-level memory cell with asymmetric drain current according to item 6 of the scope of the application, further comprising the following steps after performing the second ion implantation: depositing a second conductive layer; and The pattern of the second conductive layer is defined. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 14. The manufacturing method of a multi-level memory cell with an asymmetric drain current as described in item 6 of the scope of the application, wherein the width of the first spacer is about 0- In the range of 05 micrometers to 0.20 micrometers, the method further includes the following steps after performing the second ion implantation: depositing a second conductive layer; and defining a pattern of the second conductive layer. 48 This paper scale is applicable to China's Gus Standard (CNS) A4 (210X297). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs / 421793-/ C8 / _ D8 Application for patent scope 15. — Kind of carcass circuit metal oxide Semi-memory unit, the integrated circuit has a substrate; the integrated circuit metal-oxygen semi-memory unit has a source, a gate, and a gate oxide layer, and the source is within the substrate, and the gate oxide layer is on the substrate Between the gate and the gate; the integrated circuit includes: a drain formed in the substrate, the drain having a width;-a channel formed in the substrate, the channel contacts the gate oxide layer and is aligned with the gate The channel extends upward from the source to the drain. The channel is isolated from the drain by a biased region. The channel is adjusted to store multi-bit data. The channel is adjusted to approach the gate oxide layer. An empty region is formed in the channel region to reflect the gate voltage; and a biased region in the substrate, and between the channel and the drain, the biased region has an initial conduction state, and the biased region is adjusted Keep thin gate oxygen The initial conduction state of the layer reflects the gate voltage. The metal-oxide-semiconductor memory cell has a drain read current corresponding to the drain voltage, and a source read current corresponding to the source voltage. The source The voltage is equal to the drain voltage, and the magnitude of the drain read current is different from the magnitude of the source read current. 16. · The integrated circuit metal-oxide semiconductor memory cell of item 15 of the scope of the application, wherein the source read current is less than the drain read current. 17. For example, the integrated circuit metal-oxide-semiconductor memory cell of item 15 of the scope of the application, wherein the offset region is adjusted to form an empty region near the gate oxide layer to reflect the drain voltage. 18. For the integrated circuit metal-oxygen half-memory unit in the scope of the application case No. 15, the 49 'paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) T-: Γ tPlease (Please read the notes on the back before filling in this page) Order Q 421T93 as CS D8 VI. Patent application range The offset area is in the range of about 0.0 2 microns to 0.2 0 microns. 19. For example, the integrated circuit metal-oxygen half-memory cell in the scope of the application case No. 15, wherein the offset region is adjusted to form an empty region near the gate oxide layer to reflect the drain voltage: the offset region is In the range of about 0.02 microns to 0.20 microns. 20. For example, the integrated circuit metal-oxygen half-memory unit of the scope of the application case No. 15, wherein the offset region is adjusted to form an empty region near the gate oxide layer to reflect the drain voltage; the offset region is adjusted by It is adjusted to maintain the initial ON state close to the gate oxide layer to reflect the source voltage; and the offset region is in the range of about 0.02 microns to 0.20 microns. Printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives (please read the notes on the back before filling out this page) 21 · If you apply for the integrated circuit metal-oxygen half-memory unit of item 15 in the scope of the special case, the compensation The region is adjusted to form an empty region near the gate oxide layer to reflect the drain voltage, and the offset region is adjusted to maintain the initial conduction state close to the gate oxide layer to reflect the source voltage and the compensation The bias region is in the range of about 0.02 μm to 0.20 μm, the gate has a gate width, a first side, a second side, a bottom, and a top, the second side is opposite to the first side; the gate The pole width is the distance between the second side and the first side, the gate is between the source and the asymmetric drain, the gate is on the gate oxide layer, and the asymmetric drain is on the first side, The source is on the second side, the gate width is smaller than the distance between the source and the asymmetric drain, the gate oxide layer has a top; and the integrated circuit metal-oxygen half-memory cell further includes a first Spacer, along the first side of the gate, the first spacer from the gate 50 papers with extremely oxidized layer are printed in accordance with Chinese National Standard (CNS) Α4 (210 × 297 mm). Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 421793 B8 C8 D8. A spacer has a first spacer width on top of the gate oxide layer; the first spacer width is equal to or greater than the size of the offset region. 22. A kind of integrated circuit, comprising: an array of 100 million cells, the memory cell contains a transistor, and the transistor has a channel in the channel region of the substrate, and an asymmetric multi-stage selected in the array Billion cells can store multi-bit data; a word line and a bit line are respectively coupled to the memory cell row and the memory cell row in the array to read the data stored in the array. The bit line contains the first product A body circuit pattern layer, and the word line includes a second integrated circuit pattern layer; each selected asymmetric memory cell has a source, a gate, and a gate oxide layer, and the source is on the substrate The gate oxide layer is formed between the substrate and the gate; each selected asymmetric memory cell further includes:-an asymmetric drain, which is formed in the substrate, the asymmetric drain has a Width; a channel is formed in the substrate, the channel contacts the gate oxide layer and is aligned with the gate electrode, the channel extends from the source electrode to the asymmetric drain electrode, and an offset region separates the channel from the asymmetric electrode Drain The channel is adjusted to store multi-bit data, and the channel is adjusted to form an empty region in the channel near the gate oxide layer to reflect the gate voltage; and a biased region in the substrate, and in Channels and Asymmetric Drains 51 Paper Wave Scales Use Yin National Standard (€ \ 3) 厶 4 Specifications (210 ¥ 297 ^ cent) (Please read the note f on the back before filling this page). Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives to print 421793 a8 B8 C8 D8 6. Between the scope of patent application, the offset area has an initial conduction state, and the offset area is adjusted to keep living near the gate oxide layer. The initial on-state is to reflect the gate voltage. Each selected asymmetric memory cell has a first asymmetric drain read current corresponding to the drain voltage, and a source read corresponding to the source voltage. Current, the source voltage is equal to the drain voltage, and the magnitude of the drain read current is different from the source read current; the offset area of each selected asymmetric memory cell transistor is large enough to ensure the selected memory Unit electricity Body can be accurately read out on the bit line corresponding to the word line and the same direction. I. 23. The integrated circuit of item 22 of the scope of the application, wherein the offset region is in a range of about 0.02 μm to 0.20 μm. 24. For the integrated circuit of item 22 of the scope of the application, wherein the offset region is adjusted to form an empty region in the channel near the gate oxide layer to reflect the drain voltage; the offset region is adjusted Cheng energy can be maintained in the initial conduction state near the gate oxide layer to reflect the source voltage; and the offset region is in the range of about 0.02 microns to 0.20 microns. 25. For the integrated circuit of item 22 in the scope of the application, in which the gate of each selected asymmetric memory cell can be addressed using a corresponding word line, and the integrated circuit further includes:- A sense amplifier has a sense amplifier wire, the sense amplifier wire has a first side and a second side; a ground, has a wire, the ground wire has a first side and a second side: the bit line is close to the ground wire The bit line is the first 52 of the ground wire. This paper standard applies the Chinese National Standards (CNS) six-dimensional rule (210X297 cm) (please read the note on the back before filling this page) i, ττ -_Initial policy of Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 4 · 2, Port 9 3. A8 BS C8 D8 6. On the side of the patent application, the bit line is close to the sense amplifier wire, and the bit line is in the sense amplifier. The second side of the wire; a first selected memory cell, between the bit line and the second side of the sense amplifier wire, the asymmetric drain of the first selected memory cell is connected to the sense amplifier wire, the second Selected memory unit The asymmetric drain is connected to the ground wire; both the first selected memory cell and the second selected memory cell have a common source, and the bit line is connected to the common source of the first and second memory cells; The first memory cell can only be read out by the corresponding word line and bit line in the first direction, and the second memory cell can only be accurately read by the corresponding word line and bit line in the second direction. Read it out, the second direction is opposite to the first direction. 26. If the integrated circuit of item 22 of the scope of the application includes a memory band selection line, which is coupled to the transistor column in the array to reflect the applied voltage, the memory band selection line is used to determine the The selected asymmetric multi-level memory cell to be read by the array is electrically coupled to the memory band selection line and contains a plurality of high-critical voltage transistors which are in the array to block out other Current path. 27. For the integrated circuit of item 25 of the scope of the application, wherein the first direction is from the asymmetric drain of the first selected memory cell to the source of the first selected memory cell, and the second direction is From the asymmetric drain of the second selected memory cell to the source of the second selected memory army. "28. For example, if you apply for the integrated circuit of item 25 in the scope of the application, the first direction is 53 copies.逋 Use the national standard (CNS) A4 specification (210X297 mm) A8 B8 C8 DS 6. The scope of patent application is from the asymmetric drain of the first selected memory cell to the source of the first selected memory cell. And the second direction is from the asymmetric drain of the second selected memory cell to the source of the second selected memory cell; part of the second direction current will flow from the source of the first selected memory cell to The asymmetric drain of the first selected memory cell, the current in the second direction of the part in the first selected memory cell, and the current in the second direction of the second selected memory cell that is less than forty percent; Current in one direction will be selected from the second The source of the selected memory cell flows to the asymmetric drain of the second selected memory cell, and the current in the first direction of the part in the second selected memory cell is less than forty percent of the first selected memory cell. Current in one direction. 29. A method for reading a memory cell with complementary bias, including providing a memory cell; the memory cell has a source, a gate, and a gate oxide layer, and the source is in the substrate. The gate oxide layer is between the substrate and the gate; the billion-unit includes: a drain formed in the substrate, the drain having a width; a channel formed in the substrate, the channel contacting the gate oxide Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note “$” on the back before filling out this page) and align it with the gate. The channel extends from the source to the drain, and the offset zone is isolated. The channel and the asymmetric drain are adjusted to store multi-bit data, and the channel is adjusted to form an empty region in the channel near the gate oxide layer to reflect the gate voltage; and a bias compensation Zone Moreover, it is between the channel and the asymmetric drain. The offset region has an initial conduction state, and the offset region is adjusted to be 54 squares. It is applicable to China's standard (0) 8 4 specifications (210 &gt); < 297 mm) '~~' A5 421, 93 S D8 __ VI. The patent application park maintains the initial conduction state near the gate oxide layer to reflect the gate voltage. Each selected non- Symmetric memory cells each have a first asymmetric drain read current corresponding to the drain voltage, and a source read current corresponding to the source voltage. The source voltage is equal to the drain voltage. Differences in source read currents "3 0. For the method of reading the memory cell with complementary bias, as described in the scope of application case No. 29, wherein the channel is adjusted to be able to store multi-bit data. (Please read the precautions on the back before filling out this page) Employees ’Cooperatives of the China Standards Bureau of the Ministry of Outfitting and Economics% — 55 Standards Standards China National Standards Applicable Noisy Public 1 97 2 X 10