經濟部智慧財產局員工消費合作社印制rt 419S95 5093twf,doc/006 A7 _B7 五'發明說明（/ ) 本發明是有關於一種比較器，且特別是有關於--種 高速全幅輸入比較器。 請參照第la圖，其所繪示爲習知類比式比較器（analog comparator)之繪示圖。此比較器係由二個PM〇S電晶體 以及二個NMOS所組成，PMOS 10與20係構成主動式負 載（active-loaded)。VREF 爲參考訊號（Vss< VReF <VL.C)由 NMOS 30閘極輸入，VTN則爲輸入訊號由NMOS 40閘極輸 入。NM0S 40汲極則作爲輸出訊號VQUT。而Is爲定電流源。 當輸入訊號VIN大於參考訊號VRi;F時，NM0S 30關 閉，NM0S 40開啓，輸出訊號Vm,T會接近Vss電壓，當輸 入訊號\^小於參考訊號VREF時，NM0S 30開啓，NM0S 40 關閉，輸出訊號 V〇UT 會接近Va電壓。 而習知比較器其輸入訊號是在vss至v€e之間，假設 輸入訊號vIN爲vee，輸出訊號νουτ爲接近，當輸入訊 號V1N由vet迅速變化爲vss時，輸出訊號VQUT必須以由vss 附近開始上升，直到變成爲止，同理，當輸入訊號VIN 由vs>快速變化爲Ve。時，輸出訊號νουτ必須以相反的程 序由V。。轉變爲Vy，而其輸入輸出特性曲線如第lb圖所 繪示。 習知的比較器由於輸入訊號νΐΝ的擺動範圍（swing range )爲德_範圍，rail-torail ，亦即 Vee 至 或者 Vss 至Va.，所以習知比較器的輸出端亦會有範圍較大的輸出 訊號擺動範圍，由於輸出的訊號擺動範圍大，因此需要較 長的時間來反應才能輸出正確的比較結果，所以不利於應 3 ----------- 敦---- ----訂---------線 r (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 419895 5093twf.doc/006 ^ __B7____ 五、發明說明（>) 用在高速電路上。 請參照第2a圖，其所繪示爲習知具有磁滯現象的比 較器繪示圖。在此電路中此比較器係由四個PMOS電晶體 以及二個NMOS所組成，PMOS 52與54係構成第一主動 式負載50，PMOS 62與64係構成第二主動式負載60，VREF 爲參考訊號（Vss< VREF <V„)由NMOS 70閘極輸入，VIN 則爲輸入訊號由NMOS 80閘極輸入。NMOS 80汲極則作 爲輸出訊號V(U:T。而Is爲定電流源。 而在此電路中只要PMOS 54的元件參數K54 ，device paramater)大於 PMOS 52 的元件 參數Ki2，並且PMOS 64的元件參數K64大於PMOS 62的 元件參數K62，此比較器會有遲滯現象產生。 請參照第2b圖，其所繪示爲習知具有磁滯現象的比 較器特性曲線圖。經由設計習知比較器可以具有二個參考 電壓（VREF+與VREH·)，當輸入訊號大於VREF+時，輸出訊 號由V。。附近開始下降，直到輸出訊號變成Vss爲止。當輸 入訊號小於VRtF時，輸出訊號由Vss附近開始上升，直到 輸出訊號變成Vu爲止。而此具有磁滯現象的比較器之輸 出訊號的訊號擺動範圍亦很大，因此也需要長時間來反應 才能輸出正確的比較結果，這應用在高速電路上也是非常 不利。 本發明係提供一種高速全幅輸入比較器，利用在輸 出端與主動元件之間連接壓降元件電路，用來降低輸出端 點在高電壓輸出時電壓値。 4 -----------t--------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度過用中國國家標準（CNS)A4規格（210x297公釐） 419895 5093twf.doc/006 經濟部智慧財產局員工消費合作社印制衣Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs rt 419S95 5093twf, doc / 006 A7 _B7 Five 'invention description (/) The present invention relates to a comparator, and in particular to a high-speed full-frame input comparator. Please refer to FIG. 1a, which is a drawing of a conventional analog comparator. This comparator is composed of two PMOS transistors and two NMOS. The PMOS 10 and 20 series constitute active-loaded. VREF is the reference signal (Vss < VReF < VL.C) is input by the NMOS 30 gate, and VTN is the input signal by the NMOS 40 gate. The NM0S 40 drain is used as the output signal VQUT. And Is is a constant current source. When the input signal VIN is greater than the reference signal VRi; F, the NM0S 30 is turned off and the NM0S 40 is turned on. The output signal Vm, T is close to the Vss voltage. When the input signal is less than the reference signal VREF, the NM0S 30 is turned on, and the NM0S 40 is turned off. The signal VOUT will approach the Va voltage. The input signal of the conventional comparator is between vss and v € e. Assume that the input signal vIN is vee and the output signal νουτ is close. When the input signal V1N changes rapidly from vet to vss, the output signal VQUT must start with vss. The neighborhood starts to rise until it becomes the same. Similarly, when the input signal VIN changes from vs > to Ve quickly. The output signal νουτ must be changed by V in the reverse sequence. . Change to Vy, and its input and output characteristics are shown in Figure lb. Since the swing range of the input signal νΐΝ is conventional, the conventional comparator is rail-torail, that is, Vee to or Vss to Va. Therefore, the output of the conventional comparator will also have a larger range. Output signal swing range. Because the output signal swing range is large, it takes a long time to react to output the correct comparison result, so it is not conducive to response. 3 ----------- Tun ----- --- Order --------- line r (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Affairs Cooperative of the Property Bureau 419895 5093twf.doc / 006 ^ __B7____ 5. Description of the invention (>) Used on high-speed circuits. Please refer to Fig. 2a, which shows a conventional comparator with hysteresis. In this circuit, the comparator is composed of four PMOS transistors and two NMOS. PMOS 52 and 54 constitute the first active load 50, and PMOS 62 and 64 constitute the second active load 60. VREF is the reference. The signal (Vss < VREF < V „) is input by the NMOS 70 gate, VIN is the input signal is input by the NMOS 80 gate. The NMOS 80 drain is used as the output signal V (U: T. Is is a constant current source. In this circuit, as long as the component parameter K54, device paramater of PMOS 54 is greater than the component parameter Ki2 of PMOS 52, and the component parameter K64 of PMOS 64 is greater than the component parameter K62 of PMOS 62, the comparator will have a hysteresis phenomenon. Please refer to Figure 2b, which is a graph showing the characteristics of a conventional comparator with hysteresis. By design, the comparator can have two reference voltages (VREF + and VREH ·). When the input signal is greater than VREF +, the output signal It starts to fall from the vicinity of V until the output signal becomes Vss. When the input signal is less than VRtF, the output signal starts to rise from near Vss until the output signal becomes Vu. And this comparator with hysteresis The output signal has a large signal swing range, so it takes a long time to respond to output the correct comparison result, which is also very disadvantageous in high-speed circuits. The invention provides a high-speed full-amplitude input comparator, which is used at the output end and A voltage drop element circuit is connected between the active components to reduce the voltage 値 at the output terminal at high voltage output. 4 ----------- t -------- Order ---- ----- Line (Please read the precautions on the back before filling this page) This paper has been used in China National Standard (CNS) A4 (210x297 mm) 419895 5093twf.doc / 006 Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperative prints
五、發明說明（$ ) 本發明係提供一種高速全幅輸入比較器，利用在輸 出端與NMOS共源極端之間連接壓降元件電路，用來提高 輸出端點在低電壓輸出時電壓値。 本發明係提供一種高速全幅輸入比較器，利用壓降 元件電路來縮小輸出的變化範圍，進而加快比較器比較結 果的輸出速度，相當適合應用於高速元件的領域上。 本發明提出一種高速全幅輸入比較器，其簡述如下： 第一 PMOS源極連接高電壓源，並且閘極與汲極連 接。第二PMOS源極連接高電壓源，第二PMOS閘極連接 第一 PMOS閘極。第一 NMOS汲極連接第一 PMOS汲極， 第一 NMOS閘極連接參考訊號。第二NMOS汲極連接第二 PMOS汲極與輸出訊號端，第二NMOS閘極連接輸入訊號， 第二NMOS源極連接第一 NMOS源極。定電流源之輸入端 連接第一 NMOS源極，定電流源之輸出端連接低電壓源。 第一壓降元件電路連接於第二PMOS閘極與第二NMOS汲 極之間，陽極端連接至第二PMOS之閘極，陰極端連接至 第二NMOS汲極。第二壓降元件電路連接於第二NMOS汲 極與第二NMOS源極之間，陽極端連接第二NMOS汲極， 陰極端連接至第二NMOS源極。 本發明提出一種高速全幅輸入比較器，其簡述如下： 第一 PMOS源極連接至高電壓源。第二PMOS源極連 接至高電壓源，第二PMOS之閘極連接至第一 PMOS閘極。 第三PMOS源極連接至高電壓源，第三PMOS汲極連接至 第二PMOS汲極。第四PMOS源極連接高電壓源，第四PMOS ------------ 裝--------訂.--------線 p (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國囤家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 419895 5093twf.doc/006 _B7_ 五、發明說明（分） 閘極連接至第三PMOS閘極，第四PMOS汲極連接至第一 PMOS汲極。第一 NMOS汲極連接至第一 PMOS汲極，第 一 NMOS閘極連接參考訊號。第二NMOS汲極連接第三 PMOS汲極與輸出訊號端，第二NMOS閘極連接輸入訊號， 第二NM0S源極連接至第- NM0S源極。定電流源之輸入 端連接至第一 NM0S源極，定電流源輸出端連接至低電壓 源=第一壓降元件電路連接於第一 PMOS閘極與第一 NM〇S 汲極之間，陽極端連接至第一 PMOS閘極，陰極端連接至 第一 NM0S汲極。第二壓降元件電路連接於第一 NM0S汲 極與第一 NM0S源極之間，陽極端連接至第一 NM0S汲極， 陰極端連接至第一 NM0S源極。第三壓降元件電路連接於 第三PMOS _極與第二NM0S汲極之間，陽極端連接至第 三PMOS閘極，陰極端連接至第二NM0S汲極。第四壓降 元件電路連接於第二NM0S汲極與第二NM0S源極之間， 陽極端連接至第二NM0S汲極，陰極端連接至第二NM0S 源極。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第la圖其所繪示爲習知比較器之繪示圖； 第lb圖其所繪示爲第la圖比較器之輸入輸出特性曲 線繪示圖； 第2a圖其所繪示爲習知具有磁滯現象的比較器繪示 6 本紙張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐） ----------- --------訂---------艘 (請先閱讀背面之;t意事項再填寫本頁) 419895 經濟部智慧財產局員工消費合作社印製 五、發明說明（Γ) 圖； 第2 b圖其所繪示爲第2a圖比較器之輸入輸出特性 曲線繪不圖； 第3a圖其所繪示爲本發明高速全幅輸入比較器之第 一實施例繪不圖； 第3b圖其所繪示爲第3a圖比較器之輸入輸出特性曲 線繪示圖；以及 第4a圖其所繪示爲本發明高速全幅輸入比較器之第 二實施例繪示圖； 第4 b圖其所繪示爲第4a圖比較器之輸入輸出特性 曲線繪示圖。 標號說明： 10 、 20 、 52 、 54 、 62 、 64 、 110 、 120 、 152 、 154 、 162 、 164 PMOS 30、40、70、80、130、140、170、180 NMOS 200、210、220、230、240、250 二極體 實施例 請參照第3a圖，其所繪示爲本發明高速全幅輸入比 較器之第一實施例繪示圖。PMOS (第一 PMOS) 110的源 極連接高電壓源，並且PM0S 110之閘極與汲極相連接。 而PMOS (第二PMOS) 120的源極連接至高電壓源，PMOS 120的閘極連接至PMOS liO的閘極。NMOS (第一 NMOS) 130的汲極連接至PM〇S 110的汲極，而NMOS 130的閘極 則連接參考訊號VRH1..。NMOS (第二NMOS) 140的汲極連 7 ------------ 裝-----I--訂---------線 ， (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2Wx297公釐） 419895 5033twf . doc/006 A7 B7_ 五、發明說明（έ) 接至PMOS 12◦的汲極與輸出訊號端Vm:T，NMOS 140的 閘極連接至輸入訊號VIN，NMOS 140的源極連接至NMOS 130的源極。定電流源之輸入端連接至NMOS ] 30的源極， 定電流源之輸出端連接至低電壓源。兩個二極體200與210 作爲壓降元件電路，二極體（第一壓降元件電路）200的 陽極端連接至PMOS 120的閘極，二極體200的陰極端連 接至NMOS 140的汲極。二極體（第二壓降元件電路）210 的陽極端連接至NMOS 140之汲極，二極體210的陰極端 連接至NMOS 140的源極。 本實施例與習知最大的不同在於比較器中加入了二 極體200與210，用來限制輸出高準位以及輸出低準位， 當輸入訊號V1N爲V。。時，由於二極體200的限制，輸出 端點V(_u.F的電壓約爲A點電壓VA再減去0.7伏特，當輸 入訊號V[N爲Vss時，由於二極體210的限制，輸出端點VQUT 的電壓約爲B點電壓▽13再'加上0.7伏特。因此，輸出端點 的電壓將會被限制在（VA -0.7)與（VB +0.7)之間。請參 照第3b圖爲本發明第一實施例之輸入輸出曲線繪示圖。 而本實施例中所使用的二極體（亦即壓降元件電路） 亦可以用PMOS電晶體來代替，將PMOS電晶體汲極與閘 極連接，以源極爲陽極端，以汲極爲陰極端，一樣會有類 似二極體特性曲線之固定壓降的特性，或者可以用NMOS 電晶體來代替，將NMOS電晶體汲極與閘極連接，以汲極 爲陽極端，以源極爲陰極端，一樣會有類似二極體特性曲 線之固定壓降的特性。 8 ---------t I . 裝---f I---訂---------線 I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印利衣 本紙張尺度適用中國國家標準（CNS)A4規格mo X 297公釐） 經濟部智慧財產局員工消費合作社印*'1衣 419S95 5093twf .doc/006 A7 _B7 五、發明說明（1 ) 若是輸出端點的電壓變化範圍仍舊太大不能滿足要 求，則可以將壓降元件（二極體、PM0S電晶體或者NM0S 電晶體）串聯起來，以二極體來舉例說明，以第一個二極 體正極爲陽極端，將第一個二極體負極連接第二個二極體 正極，第二個二極體負極爲陰極端，這樣就可以構成二個 壓降元件的壓降元件電路，而輸出的電壓就會被限制在（VA -Νχ〇.7)與（VB十Ν χ〇.7)之間，N爲壓降元件電路中所 串聯之壓降元件數S。 依照本發明之第一實施例的結果，爲3.3V，可得 到VA約爲2V，約爲1.2V，所以輸出範圍約在1.3V〜1.9V 之間，其可以加速輸出端點VQUT的轉換速度。 請參照第4a圖，其所繪示爲本發明高速全幅輸入比 較器之第二實施例繪示圖。PM0S (第一 PM0S) 152的源 極連接至高電壓源。PM0S (第二PM0S) 154的源極連接 至高電壓源，PM0S 154的鬧極連接至PMOS 152的閘極。 PM〇S(第三PM0S) 162的源極連接至高電壓源，PM0S 162 的汲極連接至PM0S 154的汲極。PM0S (第四PM0S) 164 的源極連接至高電壓源，PM0S 164的閘極連接至PM0S 162 的閘極，PM0S 164的汲極連接至PM0S 152的汲極。NM0S (第一 NM0S) 170的汲極連接至PM0S 152的汲極，NM0S Π0的閘極連接至參考訊號VREF。NM0S (第二NM0S) 180 的汲極連接至PM0S 162的汲極與輸出訊號端VQUT，NM0S 180的閘極連接至輸入訊號ViN，NM0S 180的源極連接至 NM0S 170的源極。定電流源的輸入端耦接至NM0S 170 9 本紙張尺度適用令國國家標準（CNS)A4規格X 297公釐） -----------裝- ------訂---------線 ] (請先間讀背面之注意事項再填寫本頁) 經濟部智慧时產局員工消費合作社印製 419S95 5093twf.doc/006 _B7_ 五、發明說明（Ϊ ) 的源極，輸出端連接至低電壓源。四個二極體220、230、 240與250作爲壓降元件電路，二極體（第一壓降元件電 路）220陽極端連接於PMOS 152的閘極而陰極端連接於 NMOS 170的汲極。二極體（第二壓降元件電路）230陽極 端連接於NMOS 170的汲極而陰極端連接於NMOS 170的 源極。二極體（第三壓降元件電路）240陽極端連接於PMOS 162的閘極而陰極端連接於NMOS 180的汲極。二極體（第 四壓降元件電路）250陽極端連接於NMOS 180的汲極而 陰極端連接於NMOS 180的源極。 本實施例與習知具有遲滯特性之比較器最大的不同 在於比較器中加入了二極體220、230、240與250，用來 限制輸出高準位以及輸出低準位，當輸入訊號VIN爲V。。 時，由於二極體220或二極體240的限制，輸出端點VQUT 的電壓約爲C點電壓Ve再減去0.7伏特，當輸入訊號VIN 爲\^時，由於二極體230或二極體250的限制，輸出端 點VQUT的電壓約爲D點電壓VD再加上0.7伏特。因此， 輸出端點的電壓將會被限制在（Vc -0.7)與（VD +0.7)之 間。請參照第4b圖爲本發明第二實施例之輸入輸出曲線 繪示圖。 而本實施例中所使用的二極體（亦即壓降元件電路） 亦可以用PMOS電晶體來代替，將PMOS電晶體汲極與閘 極連接，以源極爲陽極端，以汲極爲陰極端，一樣會有類 似二極體特性曲線之固定壓降的特性，或者可以用NMOS 電晶體來代替，將NMOS電晶體汲極與閘極連接，以汲極 I ϋ ------------ 裝--------訂---------線 . {請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 419895 A7 5093twf.doc/006 _B7___ 五、發明說明（7) 爲陽極端，以源極爲陰極端，-樣會有類似二極體特性曲 線之固定壓降的特性。 ί請先閱讀背面之注意事項再填寫本頁) 若是輸出端點的電壓變化範圍仍舊太大不能滿足要 求，則可以將壓降元件（二極體、PMOS電晶體或者NMOS 電晶體）串聯起來，以二極體來舉例說明，以第一個二極 體正極爲陽極端，將第一個二極體負極連接第二個二極體 正極，第二個二極體負極爲陰極端，這樣就可以構成二個 壓降元件的壓降元件電路，而輸出的電壓就會被限制在 (VA -Μχ〇.7)與（VB + Μ χ〇.7)之間，Μ爲壓降元件電 路所_串聯之壓_俾元趣數目3 依照本發明之第二實施例，Vee爲3.3V，可得到Vt. 與VE約爲2V， VB與VF約爲1.2V，所以輸出範圍約在 1.3V〜L9V之間，其可以加速輸出端點V0UT的轉換速度。 因此，本發明的優點係提出一種高速全幅輸入比較 器，利用在輸出端與主動元件之間連接的壓降元件電路， 用來降低輸出端點在高電壓輸出時電壓値。 經濟部智慧財產局員工消費合作社印製 本發明的另一優點係提出一種高速全幅輸入比較 器，利用在輸出端與NMOS共源極端之間連接壓降元件電 路’用來提高輸出端點在低電壓輸出時電壓値。 本發明的再一優點係提出一種高速全幅輸入比較 器，利用壓降元件電路來縮小輸出的變化範圍，進而加快 比較器比較結果的輸出速度，相當適合應用於高速元件的 領域上。 綜上所述，雖然本發明已以較佳實施例揭露如上， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 419S95 5093twf.doc/006 Λ7 Β7 五、發明說明（/⑴ 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 (請先閱讀背面之注意事項再填寫本頁) 裝.--I ----訂----------線 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準規格（210 X 297公釐）V. Description of the invention ($) The present invention provides a high-speed full-scale input comparator, which uses a voltage drop element circuit connected between the output terminal and the NMOS common source terminal to increase the voltage at the output terminal at low voltage output. The invention provides a high-speed full-scale input comparator, which uses a voltage drop element circuit to reduce the output variation range, thereby speeding up the output speed of the comparison result of the comparator, and is quite suitable for the field of high-speed components. The present invention provides a high-speed full-scale input comparator, which is briefly described as follows: The first PMOS source is connected to a high-voltage source, and the gate is connected to the drain. The second PMOS source is connected to the high voltage source, and the second PMOS gate is connected to the first PMOS gate. The first NMOS drain is connected to the first PMOS drain, and the first NMOS gate is connected to the reference signal. The second NMOS drain is connected to the second PMOS drain and the output signal terminal, the second NMOS gate is connected to the input signal, and the second NMOS source is connected to the first NMOS source. The input terminal of the constant current source is connected to the first NMOS source, and the output terminal of the constant current source is connected to a low voltage source. The first voltage drop element circuit is connected between the second PMOS gate and the second NMOS drain, the anode terminal is connected to the gate of the second PMOS, and the cathode terminal is connected to the second NMOS drain. The second voltage drop element circuit is connected between the second NMOS drain and the second NMOS source, the anode terminal is connected to the second NMOS drain, and the cathode terminal is connected to the second NMOS source. The present invention provides a high-speed full-scale input comparator, which is briefly described as follows: The first PMOS source is connected to a high-voltage source. The second PMOS source is connected to the high voltage source, and the gate of the second PMOS is connected to the first PMOS gate. The third PMOS source is connected to the high voltage source, and the third PMOS drain is connected to the second PMOS drain. The fourth PMOS source is connected to a high-voltage source. The fourth PMOS ------------ installed -------- ordered. -------- line p (please read first Note on the back, please fill in this page again.) This paper size is applicable to China Store Standard (CNS) A4 (210 X 297 mm). Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 419895 5093twf.doc / 006 _B7_ 5. Description of the invention (Minutes) The gate is connected to the third PMOS gate, and the fourth PMOS drain is connected to the first PMOS drain. The first NMOS drain is connected to the first PMOS drain, and the first NMOS gate is connected to the reference signal. The second NMOS drain is connected to the third PMOS drain and the output signal terminal, the second NMOS gate is connected to the input signal, and the second NMOS source is connected to the -NM0S source. The input terminal of the constant current source is connected to the first NMOS source, and the output terminal of the constant current source is connected to the low voltage source = the first voltage drop element circuit is connected between the first PMOS gate and the first NMOS sinker. The extreme terminal is connected to the first PMOS gate, and the cathode terminal is connected to the first NMOS drain. The second voltage drop element circuit is connected between the first NM0S drain and the first NM0S source, the anode terminal is connected to the first NM0S drain, and the cathode terminal is connected to the first NM0S source. The third voltage drop element circuit is connected between the third PMOS_ electrode and the second NMOS drain, the anode terminal is connected to the third PMOS gate, and the cathode terminal is connected to the second NMOS drain. The fourth voltage drop element circuit is connected between the second NMOS source and the second NMOS source. The anode terminal is connected to the second NMOS source and the cathode terminal is connected to the second NMOS source. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows: Brief description of the drawings: FIG. 1a Figure 1 shows a conventional comparator; Figure 1b shows the input-output characteristic curve of the comparator in Figure 1a; Figure 2a shows a conventional comparator with hysteresis. Draw 6 This paper size is applicable to China National Standard (CNS) Al specification (210 X 297 mm) ----------- -------- Order -------- -Vessel (please read the back of the page first; please fill in this page before filling in this page) 419895 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (Γ); Figure 2b shows the comparison of Figure 2a Figure 3a shows the input and output characteristic curve of the comparator; Figure 3a shows the first embodiment of the high-speed full-frame input comparator of the present invention; Figure 3b shows the input and output of the comparator of Figure 3a Characteristic curve drawing; and FIG. 4a which shows the second embodiment of the high-speed full-frame input comparator of the present invention; FIG. 4b which 4a shows the first input of the comparator of FIG output characteristic curve shown in FIG. Explanation of symbols: 10, 20, 52, 54, 62, 64, 110, 120, 152, 154, 162, 164, PMOS 30, 40, 70, 80, 130, 140, 170, 180 NMOS 200, 210, 220, 230 , 240, 250 diode embodiments Please refer to FIG. 3a, which shows the first embodiment of the high-speed full-frame input comparator of the present invention. The source of the PMOS (first PMOS) 110 is connected to a high voltage source, and the gate of the PMOS 110 is connected to the drain. The source of the PMOS (second PMOS) 120 is connected to a high voltage source, and the gate of the PMOS 120 is connected to the gate of the PMOS liO. The drain of the NMOS (first NMOS) 130 is connected to the drain of the PMOS 110, and the gate of the NMOS 130 is connected to the reference signal VRH1 .. NMOS (Second NMOS) 140 Drain Connection 7 ------------ Install ----- I--Order --------- Line, (Please read the back first Note: Please fill in this page again.) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2Wx297 mm) 419895 5033twf .doc / 006 A7 B7_ 5. Description of the invention (rod) Connected to the drain and output of PMOS 12◦ The signal terminal Vm: T, the gate of the NMOS 140 is connected to the input signal VIN, and the source of the NMOS 140 is connected to the source of the NMOS 130. The input terminal of the constant current source is connected to the source of the NMOS] 30, and the output terminal of the constant current source is connected to the low voltage source. Two diodes 200 and 210 are used as voltage drop element circuits. The anode terminal of the diode (first voltage drop element circuit) 200 is connected to the gate of PMOS 120, and the cathode terminal of the diode 200 is connected to the drain of NMOS 140. pole. The anode terminal of the diode (second voltage drop element circuit) 210 is connected to the drain of the NMOS 140, and the cathode terminal of the diode 210 is connected to the source of the NMOS 140. The biggest difference between this embodiment and the conventional one is that diodes 200 and 210 are added to the comparator to limit the output high level and output low level. When the input signal V1N is V. . At the time, due to the limitation of the diode 200, the voltage at the output terminal V (_u.F is about the voltage A at the point A minus 0.7 volts. When the input signal V [N is Vss, due to the limitation of the diode 210, The voltage at the output terminal VQUT is about point B voltage ▽ 13 plus 0.7 volts. Therefore, the voltage at the output terminal will be limited to (VA -0.7) and (VB +0.7). Please refer to section 3b The figure shows the input-output curve of the first embodiment of the present invention. The diode (ie, the voltage drop element circuit) used in this embodiment can also be replaced by a PMOS transistor, and the PMOS transistor can be drained. Connected to the gate electrode, the source terminal is the anode terminal, and the drain terminal is the cathode terminal. It has the same characteristic of a fixed voltage drop as the diode characteristic curve, or it can be replaced by an NMOS transistor. The electrode is connected to the anode terminal and the cathode terminal of the source, and it will have a similar voltage drop characteristic similar to the diode characteristic curve. 8 --------- t I. --- Order --------- Line I (Please read the notes on the back before filling out this page) Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 size mo X 297 mm.) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * '1 419S95 5093twf .doc / 006 A7 _B7 V. Description of the invention (1) If output The voltage change range of the terminal is still too large to meet the requirements, you can connect a voltage drop element (diode, PM0S transistor or NM0S transistor) in series, take the diode as an example, and use the first diode The positive electrode is the anode terminal, the first diode negative electrode is connected to the second diode positive electrode, and the second diode negative electrode is the cathode terminal, so that a voltage drop element circuit of two voltage drop elements can be formed, and the output The voltage will be limited between (VA-Νχ〇.7) and (VB Νχχ 0.7), where N is the number of voltage drop elements S connected in series in the voltage drop element circuit. According to the result of the first embodiment of the present invention, it is 3.3V, and the VA is about 2V and about 1.2V, so the output range is about 1.3V ~ 1.9V, which can accelerate the conversion speed of the output endpoint VQUT. . Please refer to Fig. 4a, which shows a second embodiment of the high-speed full-frame input comparator of the present invention. The source of PM0S (first PM0S) 152 is connected to a high voltage source. The source of PM0S (second PM0S) 154 is connected to a high voltage source, and the alarm of PM0S 154 is connected to the gate of PMOS 152. The source of PM0S (third PM0S) 162 is connected to a high voltage source, and the drain of PM0S 162 is connected to the drain of PM0S 154. The source of PM0S (fourth PM0S) 164 is connected to a high voltage source, the gate of PM0S 164 is connected to the gate of PM0S 162, and the drain of PM0S 164 is connected to the drain of PM0S 152. The drain of NM0S (first NM0S) 170 is connected to the drain of PM0S 152, and the gate of NM0S Π0 is connected to the reference signal VREF. The drain of NM0S (second NM0S) 180 is connected to the drain of PM0S 162 and the output signal terminal VQUT, the gate of NM0S 180 is connected to the input signal ViN, and the source of NM0S 180 is connected to the source of NM0S 170. The input terminal of the constant current source is coupled to NM0S 170 9 This paper size is applicable to the national standard (CNS) A4 size X 297 mm) ----------- install ------- order --------- Line] (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Wisdom and Time Bureau of the Ministry of Economic Affairs 419S95 5093twf.doc / 006 _B7_ V. Description of the Invention (Ϊ) Source, the output is connected to a low voltage source. The four diodes 220, 230, 240, and 250 serve as voltage drop element circuits. The anode of the diode (first voltage drop element circuit) 220 is connected to the gate of PMOS 152 and the cathode is connected to the drain of NMOS 170. The anode of the diode (second voltage drop element circuit) 230 is connected to the drain of the NMOS 170 and the cathode is connected to the source of the NMOS 170. The anode of the diode (third voltage drop element circuit) 240 is connected to the gate of PMOS 162 and the cathode is connected to the drain of NMOS 180. The anode of the diode (fourth voltage drop element circuit) 250 is connected to the drain of NMOS 180 and the cathode is connected to the source of NMOS 180. The biggest difference between this embodiment and the conventional comparator with hysteresis is that diodes 220, 230, 240, and 250 are added to the comparator to limit the output high level and output low level. When the input signal VIN is V. . At the time, due to the limitation of the diode 220 or the diode 240, the voltage at the output terminal VQUT is about the voltage C of the point V minus 0.7 volts. When the input signal VIN is \ ^, due to the diode 230 or the diode The limit of the body 250 is that the voltage at the output terminal VQUT is about the voltage D at the point D plus 0.7 volts. Therefore, the voltage at the output terminals will be limited between (Vc -0.7) and (VD +0.7). Please refer to FIG. 4b, which is an input-output curve drawing of the second embodiment of the present invention. The diode (ie, the voltage drop element circuit) used in this embodiment can also be replaced by a PMOS transistor, and the drain of the PMOS transistor is connected to the gate, with the source terminal being the anode terminal and the drain terminal being the cathode terminal. , There will be similar characteristics of the fixed voltage drop of the diode characteristic curve, or you can use NMOS transistor instead, connect the NMOS transistor drain to the gate to drain I ϋ -------- ---- Install -------- Order --------- Line. {Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 Specifications (210x297 mm) 419895 A7 5093twf.doc / 006 _B7___ V. Description of the invention (7) For the anode terminal and the source terminal for the cathode terminal,-there will be a characteristic similar to the fixed voltage drop of the diode characteristic curve. (Please read the precautions on the back before filling this page.) If the voltage change range of the output terminals is still too large to meet the requirements, you can connect a voltage drop element (diode, PMOS transistor or NMOS transistor) in series. Take the diode as an example, take the first diode anode as the anode terminal, connect the first diode anode to the second diode anode, and the second diode anode as the cathode terminal. A voltage drop element circuit of two voltage drop elements can be formed, and the output voltage will be limited between (VA-Μχ0.7) and (VB + Μ χ 0.7), where M is the voltage drop element circuit. _ 系列 压 压 _ 压 元 趣 数 3 According to the second embodiment of the present invention, Vee is 3.3V, and Vt can be obtained. V and VE are about 2V, VB and VF are about 1.2V, so the output range is about 1.3V ~ Between L9V, it can accelerate the conversion speed of the output endpoint V0UT. Therefore, the advantage of the present invention is to propose a high-speed full-scale input comparator, which uses a voltage-drop element circuit connected between the output terminal and the active device to reduce the voltage 値 at the output terminal at high voltage output. Another advantage of the present invention is that the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has proposed a high-speed full-scale input comparator that uses a voltage-drop element circuit connected between the output and the NMOS common source extreme to increase the output endpoint at low Voltage 値 during voltage output. Another advantage of the present invention is to propose a high-speed full-amplitude input comparator, which uses a voltage drop element circuit to reduce the output variation range, thereby speeding up the output speed of the comparator comparison result, which is quite suitable for the field of high-speed components. To sum up, although the present invention has been disclosed in the preferred embodiment as above, the paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 419S95 5093twf.doc / 006 Λ7 B7 V. Description of the invention (/ Of course, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be regarded as the scope of the attached patent. The definitions shall prevail. (Please read the notes on the back before filling this page.) Packing. --I ---- Order ---------- Consumption Cooperation Du Intellectual Property Staff The paper size of the paper is applicable to Chinese national standard specifications (210 X 297 mm)