TW418499B - Manufacturing method of landing pad - Google Patents

Abstract

The present invention provides a manufacturing method of landing pad which includes the following step: providing a semiconductor substrate; forming a transistor with a gate structure on the semiconductor substrate; forming a first insulation layer to isolate the sidewall of the gate structure and the top portion; forming a planarized conductive layer totally; defining the planarized conductive layer to expose an area for isolating the landing pad; forming a second insulation layer to fill the area for isolating the landing pad; removing the planarized conductive layer to expose a predetermined area on the semiconductor substrate; forming a landing pad by an epoxy silicon growth process on the predetermined area in which the insulation layer may use the oxide layer material to reduce the dielectric coefficient and stress; further, using the epoxy silicon growth process to form a landing pad for preventing the problems encountered in the self-aligned etching process.

Description

418499 Description of the invention (1) The present invention relates to a method for manufacturing a contact pad (especially a method of forming an isolation contact pad region by using an insulating layer) and forming a contact pad by a process of epitaxial growth. Production method. Known semiconductor memory devices, such as dynamic random access memory, generally exist in the form of an array. 'It is mainly composed of memory cells. Memory cells generally include the selection of transistors and capacitors, generally to increase the density of memory devices.' The size must be continuously reduced. However, in the process of reduction, how to improve the error tolerance of the bit line contact window or the capacitive node contact window is also one of the current issues. The traditional solution proposed is self-aligned contact. The window process plus the two-stage capacitive node contact pad and contact plug process. Generally speaking, the source of the transistor is connected electrically through the contact of the first stage and the contact plug of the valley of the first stage. The capacitor and its drain D are electrically connected to the bit line BL ′ through the contact plug of the bit line contact window as shown in FIG. 1. First, according to Fig. 1, in order to provide a semiconductor substrate 10, for example, a P-type semiconductor substrate composed of a silicon material. Then use isolation processes to form several shallow trenches, STI structures, to define several active regions on the semiconductor substrate, and then use traditional processes such as deposition, lithography, money engraving, etc. to form a source electrode s on the active region of the semiconductor substrate. , A drain D, and a transistor composed of a gate structure WL as a word line. In addition, in order to perform the self-aligned contact window process, the gate structure η is isolated by a silicon nitride material. For example, a thick, appropriate silicon nitride layer is first deposited by a chemical vapor deposition process, and a nitrogen is formed after etch back. Silicon spacer layer 20 and silicon nitride cap layer 25, and secondly, it is different from silicon oxide material.

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The insulating layer is used to deposit an oxide layer 30 using a chemical vapor deposition process to cover the crystal and the semiconductor substrate. Then use the lithography process and #etching step to define the oxide layer 30 to form a contact window exposing the source region 3, and sequentially form a contact pad LP. Inside the contact window, a chemical vapor deposition process is used to form an insulating layer such as ^ Layer 40 to isolate the contact pad LP and subsequent bit lines BL. Next, the lithography process and the etching step are used to define the oxide layer 40 to form a contact window exposing the drain region D, and then a bit line plug BC is formed in the contact window to form a bit line BL. A metal layer is formed by a plating or chemical vapor deposition process, and a bit line is formed by a lithography and etching process, which is electrically connected to the bit and the plug BC. Then the subsequent insulation layer isolation, capacitor node contact window and contact plug manufacturing, and capacitor formation are performed. However, the aforementioned problem is that as the size is reduced, the gap between the gate structures of the adjacent sidewalls having a silicon nitride spacer layer will be less than 0.05um, so it is difficult to perform a self-aligned contact window etching process. In addition, nitrogen Siliconized materials also include disadvantages such as increased stress and higher dielectric constant. In order to improve the problem just described, the present invention provides a method for manufacturing a contact pad, which includes the following steps: providing a semiconductor substrate; forming a transistor with a gate structure on the semiconductor substrate; forming a first-insulating layer to isolate the gate structure Sidewall and top; comprehensively forming a planarized polycrystalline silicon layer; defining a planarized polycrystalline silicon layer to expose the area used to isolate the contact pad; forming a second insulating layer to fill the area used to isolate the contact pad Removing the planarized polycrystalline stone layer to expose a predetermined region on the semiconductor substrate; and forming a contact ridge on the predetermined region by a worm crystal stone growing process. Among them, the above insulation

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An oxide layer can be used for the layer to reduce the dielectric constant and stress. In addition, the contact pad is formed by an epitaxial silicon growth process, which can avoid the problems encountered by self-aligned etching (SAC). The invention is described below with reference to the drawings and preferred embodiments. Simple drawing. Sectional view of the first contact pad manufacturing process. Figures 2 to 9 are cross-sectional views of the manufacturing process of a contact pad according to a preferred embodiment of the present invention. [Explanation of symbols] 10, 100 ~ semiconductor substrate; S / D ~ source / drain; 20 ~ nitride nitride spacer layer; 25 ~ silicon nitride top cap layer; 30, 40 ~ oxide layer; bL ~ bit Line; BC ~ bit line contact plug; LP ~ capacitor node contact plug; mi ~ shallow trench isolation structure; 120, 220 ~ oxide layer; 140 ~ polycrystalline silicon layer; 18 ~~ oxide layer; AC ~ active Area; 240 ~ silicon oxide spacer layer; 230 ~ silicon oxide cap layer. EXAMPLES Examples of the present invention will be described below with reference to Figs. 2 to 9. First, according to Figs. 2A and 2B, where "Fig. 2A is a cross-sectional view of a general transistor process" and Fig. 2B is a cross-sectional view taken along the word line of Fig. 2A. First, a semiconductor substrate 100 is provided, such as a P-type semiconductor substrate composed of a silicon material. Then an isolation process is used to form a plurality of shallow trench STI structures' to define a plurality of active regions K on the semiconductor substrate. Next, a gate structure as a word line WL is formed on the active region of the semiconductor substrate using conventional processes such as deposition, lithography, and etching.

Page 6 418493 V. Description of the invention (4) Then 'form a first insulating layer 230, 240 to isolate the sidewall and top of the gate structure WL', for example, first deposit a silicon oxide layer of an appropriate thickness using a chemical vapor deposition process. After the engraving, an oxide is formed; the spacer layer 240 and the silicon oxide cap layer 230 are formed. In addition, the foregoing process further includes using an ion implantation step on the active regions on both sides of the gate structure to form a source S and a drain D. Among them, in order to avoid the tunnel effect, an insulating layer is generally formed as an ion implantation mask. For example, a sacrificial oxide layer 1 2 0 is generated by a thermal oxidation method, and then the source electrode S is completed by performing an ion implantation step. , A drain D, and a transistor composed of a gate structure of the word line WL. Next, for the sake of convenience, the subsequent process of the embodiment of the present invention will be described along the cross-sectional view of the word line, as shown in FIGS. 3 to 7. Please refer to FIG. 3 ', which shows a step of comprehensively forming a planarized conductive layer on the aforementioned semiconductor substrate with transistors, the height of which is higher than the word line WL. For example, a chemical vapor deposition process can be used to deposit a polycrystalline silicon layer on the entire semiconductor substrate, and then a planarization process such as etch-back or chemical mechanical polishing is performed to form a planarized polycrystalline silicon layer. Secondly, please refer to FIG. 4, which shows a step of defining a planarization of the polycrystalline silicon layer 140 to expose the area 160 for isolating the contact area. For example, a lithography process and an etching step such as an anisotropic dry etching process are performed to transfer a pattern onto the planarized polycrystalline silicon layer 140, and a shallow trench isolation region ST I is formed to isolate contacts The area of the pad 160 ′ is because the polycrystalline silicon has a higher etching selection ratio to the oxide layer. Therefore, the foregoing insulating layer material may be selected from the oxide layer for isolation. As for the area where the contact pad is to be formed

Page 7 / Π8499 V. Description of the invention (5) If the source region of the active region is covered by a planarized polycrystalline silicon layer. Then refer to Figure 5 which shows the steps of forming an insulating layer to fill the area of the isolated contact pad. For example, a chemical vapor deposition process can be used to fully deposit an oxide layer, or a high-density plasma oxidation layer (HDP), a TEOSCTetra-Ethyl-Ortho-Silicate oxide layer formed by a low-pressure chemical vapor deposition process, Or HSQ (Hydrogen Silsesquioxane), etc., and then, a planarization process such as an etch-back or a chemical mechanical polishing process is performed to form a planarized oxide layer 180 that fills the region 160 of the isolation contact pad. Accordingly, the planarized polycrystalline silicon layer 140 is removed to leave a planarized oxide layer 180 that fills the area 160 of the isolation contact pad. Next, please refer to FIG. 6, which shows a step of forming a contact pad by epitaxial silicon growth process on a predetermined area. For example, first, a wet etching process such as a dilute hydrofluoric acid solution (DHF) or a hydrofluoric acid buffer solution (BHF) may be used to remove a portion of the oxide layer 120 to expose a predetermined area on the semiconductor substrate 100, such as an active area The source region of the contact pad is to be formed, and then a contact pad LP is formed on the predetermined region by a silicon epitaxial growth process (Si Epitaxial Growth). Among them, when the silicon growth exceeds the height of the oxide layer 180, the lateral growth of the silicon can be appropriately allowed to increase the surface area of the silicon contact pad. Subsequently, please refer to FIG. 7 and FIG. 8, where “FIG. 8 is a cross-sectional view of a character line, which shows the formation of an insulating layer such as an oxide layer formed by a chemical vapor deposition process to cover the aforementioned contact pad LP And transistor semiconductor substrate 100. Next, please refer to FIG. 9 ’, which shows the subsequent traditional system based on FIG.

4 ^ 8499 V. Description of the invention ¢ 6) The perspective view of the bit line contact window BC is completed. Among them, the contact pad Lp is located on the source region of the active region AC, and the area shown in FIG. 18 is a planarized oxide layer that fills the region that isolates the contact pads. Therefore, the contact pads can be prevented from contacting with the semiconductor substrate due to lateral growth. Adjacent contact pads are shorted. In addition, since the second example does not use the self-aligned coining process, it is not necessary to select a silicon nitride material, but an oxide layer material can be used. Therefore, a word line meter can be isolated from the top oxide layer 23 and the spacer layer 240, so It can reduce the dielectric constant and stress. Furthermore, the formation of contact pads using the silicon epitaxial growth process can avoid the problems encountered in self-aligned etching (SAC), such as the contact window is too small to etch to the source, etc. . Although the present invention has been better defined by the present invention, any person familiar with this god and scope can make changes and attach to it as follows_please refer to the examples in the scope of the patent as disclosed above, but it is not intended for the artist Without departing from the refined decoration of the present invention ', the scope of protection of the present invention shall prevail.

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Claims (1)

6. Scope of Patent Application 1. A method for manufacturing a contact pad, comprising the following steps: providing a semiconductor substrate; forming a transistor with a gate structure on the semiconductor substrate; forming a first insulating layer to isolate the gate structure Sidewall and top; comprehensively forming a planarized conductive layer; defining the planarized conductive layer to expose an area for isolating the contact pad; forming a second insulating layer to fill the area for isolating the contact pad; removing the The conductive layer is planarized to expose a predetermined region on the semiconductor substrate, and a contact pad is formed on the predetermined region by an epitaxial silicon growth process. 2. The manufacturing method according to item 1 of the scope of patent application, wherein the first insulating layer is an oxide layer. 3. The manufacturing method as described in item 1 of the scope of patent application, wherein the planarized conductive layer is a polycrystalline silicon layer. 4. The manufacturing method described in item 1 of the scope of patent application, which makes the second insulating layer an oxide layer. 5. The manufacturing method as described in item 1 of the patent application scope, wherein the second insulating layer is a high-density plasma oxide layer. 6. The manufacturing method as described in item 1 of the patent application scope, wherein the second insulating layer is a TEOS oxide layer formed by a low-pressure chemical vapor deposition process. 7. The manufacturing method according to item 1 of the scope of patent application, wherein the second insulating layer is an H S Q layer. Page 10 4 18499 6. Application for Patent Fan Yuan 8. A method for manufacturing a contact pad, comprising the following steps: forming a semiconductor substrate on which a transistor having a source, a drain and a gate structure is formed on the semiconductor; On the bottom; forming a first insulating layer to isolate the sidewall and the top of the gate structure; forming a planarized polycrystalline silicon layer comprehensively; 'defining the planarized polycrystalline silicon layer to be exposed on the semiconductor substrate for isolation Area of the contact pad; opening> forming a second insulating layer to fill the area for isolating the contact pad; removing the planarized polycrystalline silicon layer to a predetermined area on the semiconductor substrate; and The epitaxial silicon growth process forms a contact pad. 9. The manufacturing method according to item 8 of the scope of patent application, wherein the first insulating layer is an oxide layer. 10. The manufacturing method according to item 8 of the scope of patent application, wherein the predetermined region exposed on the semiconductor substrate is a source region. 11. The manufacturing method according to item 8 of the scope of patent application, wherein the second insulating layer is an oxide layer. 12. The manufacturing method according to item 8 of the scope of patent application, wherein the first insulating layer is a high-density plasma oxide layer. 13. The manufacturing method according to item 8 of the scope of the patent application, wherein the second insulating layer is a TEOS oxide layer formed by a low-pressure chemical vapor deposition process. U 14 · The manufacturing method as described in item 8 of the scope of patent application, wherein 41R4 99 6. Scope of patent application The second insulation layer is an H S Q layer. Page 12