TW417177B - Semiconductor device with silicide contact structure and method for producing the same - Google Patents

Semiconductor device with silicide contact structure and method for producing the same Download PDF

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Publication number
TW417177B
TW417177B TW086116486A TW86116486A TW417177B TW 417177 B TW417177 B TW 417177B TW 086116486 A TW086116486 A TW 086116486A TW 86116486 A TW86116486 A TW 86116486A TW 417177 B TW417177 B TW 417177B
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Taiwan
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film
titanium
semiconductor device
contact hole
conductive film
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TW086116486A
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Chinese (zh)
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Hiromi Gohara
Takeshi Baba
Masayasu Suzuki
Hideo Miura
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Within a contact hole 5 made in an insulating film 4; a diffusion layer 3a of a silicon substrate 1 and a conductive film 8, or a polycrystalline silicon layer 10 and conductive film 8, or a gate electrode 12 and conductive film 8 are connected through a titanium silicide film 6. The film 6 is formed by utilizing a silicide reaction between a titanium film 7 and silicon. And the upper and lower thicknesses of the titanium silicide film 6 are set at values prescribed by an internal stress of the conductive film 8 respectively.

Description

ϊ 417177 Α7 Β7____ 五、發明説明（1 ) (請先聞讀背面之注意事項再填寫本頁) 本發.明係關於，半導體矽和導電性膜藉由具接觸孔之 層間絕緣膜積層，該矽和導電性膜於接觸孔內部藉由矽化 物連接而成之矽化物接觸構造，特別是極適合具防止矽化 物與矽之間之層間剝離之矽化物接觸構造的半導體裝置及 其製造方法。 近年來，半導體裝置高集積化、微細化、半導體裝置 之各部分功能之提昇被強烈要求，例如，爲實現高速動作 ，導電性膜形成之金屬配線與半導體矽之連接部分之接觸 電阻之低減被期待著^ 習知技術之減低矽基板表面與金屬配線之電連接接觸 部分之電阻，係如揭示於特開平0 7 - 7 8 8 2 1號公報 ，在矽基板與積層於該基板上之金屬配線間形成矽化鈦膜 〇 經濟部智慈財產局員工涓費合作社印製 爲於矽與金屬之界面間形成矽化鈦膜以得低接觸電阻 ，需將矽化鈦（T i s i X，XS2 )膜之膜厚形成某種 較厚程度，此乃經驗所知者。但相對地，矽化鈦膜之膜厚 越厚，在矽化鈦膜與矽之界面容易產生剝離，此爲問題。 此乃因上述矽化鈦膜，係於矽上沈積鈦膜後施予熱處理使 矽和鈦反應而形成，因而反應時膜之體積變化致使膜內部 產生應力。 · 於該矽化鈦膜內部產生之應力，導致在矽化鈦膜與矽 之界面附近亦產生較高應力，當矽化鈦膜之膜厚越厚，或 接於矽化鈦膜之導電性膜之膜內部應力（導電性膜成膜後 產生之內部應力）越高，該應力越大。因此’上述矽化鈦 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） _ 4 - Α7 Β7 五、發明説明（2 ) 膜與矽之界面附近產生之較大應力，將成爲矽化鈦膜剝離 之原因。 亦即，矽化鈦膜，當膜厚越厚時越容易剝離，成爲半 導體裝置之高集積化、微細化之障礙β 本發明目的爲提供一種，在絕緣膜所設接觸孔內，矽 及導電性膜藉由矽化鈦膜連接時，可防止矽化鈦膜之剝離 的半導體裝置及其製造方法。 本發明爲一種半導體裝置，矽層和導電性膜係藉由絕 緣膜積層：於該絕緣膜設有接觸孔，於該接觸孔內部上述 矽層和導電性膜係藉由矽化鈦膜連接，其特徵爲：上述矽 化鈦膜之膜厚之上限係設定爲對應於成膜後之上述導電性 膜之膜內部應力所界定之値。 依此種構成之本發明，考量矽化鈦膜之膜厚，與接於 該矽化鈦膜之導電性膜之膜內部應力間之相關關係，將矽 化鈦膜之膜厚上限設定爲對應於導電性膜之膜內部應力所 界定之値。亦即，矽化鈦膜之膜厚設定爲不會剝離之導電 性膜之膜內部應力之對應値。如此則可減低矽化鈦膜與矽 之界面附近所產生應力，可防止矽化鈦膜之剝離。 於上述半導體裝置較好是，上述矽層係包含上述絕緣 膜及導電性膜所積層之半導體裝置之矽基板。 又，接觸孔內部中之上述矽基板之上方沈積有多晶矽 層，上述矽化鈦膜可形成於該多晶矽層和導電性膜之間。 又，於上述半導體裝置中，於上述矽基板上設由多晶 矽所形成閘極，上述接觸孔可設於該閘極上面。 本紙張尺度適用中國國家搮準（CNS)A4規格（ 210X297公釐）-5- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消貪合作社印製ϊ 417177 Α7 Β7 ____ V. Description of the invention (1) (Please read the precautions on the back before filling out this page) This issue is about semiconductor silicon and conductive films laminated with an interlayer insulating film with contact holes. A silicide contact structure in which silicon and a conductive film are connected by a silicide inside a contact hole is particularly suitable for a semiconductor device having a silicide contact structure that prevents interlayer delamination between the silicide and silicon, and a method for manufacturing the same. In recent years, high integration, miniaturization of semiconductor devices, and enhancement of the functions of various parts of semiconductor devices have been strongly demanded. For example, in order to achieve high-speed operation, the contact resistance between the metal wiring formed by a conductive film and the connection portion of semiconductor silicon has been reduced Looking forward to ^ reducing the resistance of the electrical connection contact portion between the surface of the silicon substrate and the metal wiring by the conventional technology, as disclosed in Japanese Patent Application Laid-Open No. 0 7-7 8 8 2 1, the silicon substrate and the metal laminated on the substrate A titanium silicide film is formed in the wiring room. The employee of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a titanium silicide film at the interface between silicon and metal to obtain a low contact resistance. The film thickness forms a certain thickness, which is known by experience. In contrast, the thicker the thickness of the titanium silicide film, the more easily the peeling occurs at the interface between the titanium silicide film and silicon, which is a problem. This is because the above titanium silicide film is formed by depositing a titanium film on silicon and applying heat treatment to react the silicon and titanium, so the volume change of the film during the reaction causes stress inside the film. · The stress generated inside the titanium silicide film causes higher stress near the interface between the titanium silicide film and silicon. When the thickness of the titanium silicide film is thicker, or it is connected to the inside of the conductive film of the titanium silicide film The higher the stress (the internal stress generated after the conductive film is formed), the larger the stress. Therefore, 'The above titanium silicide paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) _ 4-Α7 Β7 V. Description of the invention (2) The large stress generated near the interface between the film and silicon will become silicified Reasons for peeling of titanium film. That is, the titanium silicide film is more likely to peel off when the film thickness is thicker, which becomes a barrier to high integration and miniaturization of semiconductor devices. The object of the present invention is to provide silicon and conductivity in a contact hole provided in an insulating film. A semiconductor device capable of preventing peeling of a titanium silicide film when the films are connected through a titanium silicide film and a method for manufacturing the same. The invention is a semiconductor device. The silicon layer and the conductive film are laminated by an insulating film: a contact hole is provided in the insulating film, and the silicon layer and the conductive film are connected by a titanium silicide film inside the contact hole. It is characterized in that the upper limit of the film thickness of the above-mentioned titanium silicide film is set to correspond to the boundary defined by the internal stress of the film of the conductive film after film formation. According to the present invention having such a structure, considering the correlation between the film thickness of the titanium silicide film and the internal stress of the conductive film connected to the titanium silicide film, the upper limit of the film thickness of the titanium silicide film is set to correspond to the conductivity Membrane is defined by the internal stress of the membrane. That is, the film thickness of the titanium silicide film is set to correspond to the internal stress of the film of the conductive film that does not peel. In this way, the stress generated near the interface between the titanium silicide film and silicon can be reduced, and peeling of the titanium silicide film can be prevented. In the semiconductor device, it is preferable that the silicon layer is a silicon substrate of a semiconductor device including a laminated layer of the insulating film and the conductive film. In addition, a polycrystalline silicon layer is deposited above the silicon substrate in the inside of the contact hole, and the titanium silicide film may be formed between the polycrystalline silicon layer and the conductive film. In the semiconductor device, a gate formed of polycrystalline silicon is provided on the silicon substrate, and the contact hole may be provided on the gate. This paper size applies to China National Standard (CNS) A4 (210X297 mm) -5- (Please read the notes on the back before filling this page) Order Printed by the Anti-Corruption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

五、發明説明（3 ) 本發明提供一種半導體裝置，其係具備在M' 0 S電晶 體上部配置有資訊儲存用電容元件之推疊電容器構造之記 億格，在用以連接上述Μ 0 S電晶體之擴散層及位元線之 接觸孔內部沈積多晶矽層之同時，與週邊電路之MO S電 晶體之擴散層連接之電氣配線及上述位元線係以同一 W/ T i N / T i之配線層構成，上述位元線及電氣配線係藉 由矽化鈦膜分別連接於上述多晶矽層及上述周邊電路之擴 散層；其特徵爲：上述矽化鈦膜之膜厚上限，係設定爲對 應於成膜後之上述導電性膜之膜內部應力所界定之値。 又，上述半導體裝置，矽化鈦膜之膜厚上限値t ( n m )，較好是依成膜後之導電性膜之膜內部應力σ 〔 Μ P a )而設定爲 1 = 150-0. 03σ 所界定之値。 又，上述接觸孔之孔徑上限較好爲0 . 4 /zm。 本發明係一種半導體裝置之製造方法，其係在矽基板 上設絕緣膜，於該絕緣膜開設接觸孔，至少在上述接觸孔 內部沈積接觸於上述矽基扳之鈦膜，沈積接觸於上述肽膜 之導電性膜後，對沈積有上述鈦膜及導電性膜之上述矽基 板進行熱處理，藉上述鈦膜與上述矽基板間之矽化物反應 來形成矽化鈦膜者，其特徵爲：上述鈦膜之膜厚上限値， 係設定爲對應於成膜後之上述導電性膜之膜內部應力所界 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - (請先閱讀背面之注意事項再填{?5本頁) 訂 經濟部智恶財4场員工消費合作社印製 A7 B7 五、發明説明U ) 定之値。 (請先閱讀背面之注意事項再填寫本頁) 於本發明此種半導體裝置之製造方法中，考量鈦膜之 膜厚與該導電性膜之膜內部應力間之關係，將鈦膜之膜厚 上限設定爲依導電性膜之膜內部應力所界定之値。亦即， 將鈦膜之膜厚設爲依導電性膜之膜內部應力之値俾在矽化 鈦膜不產生剝離。如此則可將矽化鈦膜與矽之界面附近產 生之應力控制爲剝離產生應力値以下，可防止矽化鈦膜之 剝離。 於上述半導體裝置之製造方法，較好是將鈦膜之膜厚 上限値（nm)，依成膜後之導電性膜之膜內部應力σ ( MPa)'設疋爲 γ = 60-0.012σ 1 所界定之値。 又，本發明之半導體裝置之.製造方法中，上述接觸孔 之孔徑上限較好爲0 . 4 // m。 經濟部智慧財產局8工消#合作社印製 依本發明之半導體裝置，於絕緣膜所設接觸孔內部， 矽和導電性膜藉由矽化鈦膜連接，將矽化鈦膜之膜厚上限 及鈦膜之膜厚上限分別設定爲依導電性膜之膜內部應力所 界定之値*故可防止矽和矽化鈦之界面之剝離。另外，藉 由矽化鈦膜膜厚之控制可減低矽與導電性膜間之接觸電阻 ，因此可提供具良好接觸構造之半導體裝置。 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部智慧財1局員工消費合作社印製 r 417；:. A7 B7___ 五、發明説明（5 ) 〔較佳實施例〕 以下，參照圖1〜圖5說明本發明第1實施形態。 圖1及圖2 A〜2 D分別爲本實施形態之半導體裝置 中之接觸構造（接觸孔附近之構造）及其製造方法。 本半導體裝置，如圖1所示，係具備：矽基板1 ，形 成於矽基板1上之閘極氧化膜1 1及閘極，及形成於矽基 板1表面之絕緣膜（層間絕緣膜）4。絕緣膜4上設有接 觸孔5。另，矽基板1上形成有元件分離區域2，擴散層 3a ，3b。接觸孔5內面、接觸孔5底面之擴散層3a 表面，及絕緣膜4表面形成有鈦膜7及導電性膜8。又， 於接觸孔5內部，於擴散層3 a與鈦膜7之間形成矽化鈦 膜6，擴散層3 a與導電性膜（例如T i N膜等）8藉由 矽化鈦膜6連接。V. Description of the invention (3) The present invention provides a semiconductor device, which is equipped with a memory cell with a push-up capacitor structure in which an information storage capacitor element is arranged on the M '0 S transistor, and is used to connect the above M 0 S The polycrystalline silicon layer is deposited inside the diffusion layer of the transistor and the contact hole of the bit line. At the same time, the electrical wiring connected to the diffusion layer of the MOS transistor of the peripheral circuit and the bit line are the same W / T i N / T i The wiring layer is composed of the bit line and the electrical wiring connected to the polycrystalline silicon layer and the diffusion layer of the peripheral circuit through a titanium silicide film. The feature is that the upper limit of the film thickness of the titanium silicide film is set to correspond to The thickness of the conductive film after film formation is defined by the internal stress of the film. Also, in the above-mentioned semiconductor device, the upper limit of the film thickness of the titanium silicide film 値 t (nm) is preferably set to 1 = 150-0. 03σ depending on the film internal stress σ [M P a) of the conductive film after film formation. As defined. The upper limit of the pore diameter of the contact hole is preferably 0.4 / zm. The invention relates to a method for manufacturing a semiconductor device. An insulating film is provided on a silicon substrate, a contact hole is opened in the insulating film, and a titanium film contacting the silicon-based substrate is deposited at least in the contact hole, and the peptide is deposited in contact with the peptide. After the conductive film of the film, the silicon substrate on which the titanium film and the conductive film are deposited is subjected to heat treatment, and a titanium silicide film is formed by a silicide reaction between the titanium film and the silicon substrate, which is characterized in that the titanium The upper limit of the film thickness 値 is set to correspond to the internal stress of the above-mentioned conductive film after film formation. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6-(Please read first Note on the back page (? 5 pages) Order the A7 B7 printed by the Consumers ’Cooperatives of the Ministry of Economic Affairs and the Fate of Wealth and Wealth. V. Description of the Invention U). (Please read the precautions on the back before filling this page) In the method of manufacturing a semiconductor device of the present invention, consider the relationship between the film thickness of the titanium film and the internal stress of the conductive film, The upper limit is set to be defined by the internal stress of the film of the conductive film. That is, the film thickness of the titanium film is set so that peeling does not occur in the titanium silicide film depending on the internal stress of the film of the conductive film. In this way, the stress generated near the interface between the titanium silicide film and silicon can be controlled to be less than or equal to the stress caused by peeling, and the peeling of the titanium silicide film can be prevented. In the method for manufacturing a semiconductor device described above, the upper limit of the film thickness of the titanium film 値 (nm) is preferably set to γ = 60-0.012 σ 1 according to the film internal stress σ (MPa) ′ of the conductive film after film formation. As defined. In the method for manufacturing a semiconductor device according to the present invention, the upper limit of the hole diameter of the contact hole is preferably 0.4 / m. 8 工 消 # Cooperative in the Intellectual Property Bureau of the Ministry of Economic Affairs prints a semiconductor device according to the present invention. Inside the contact hole provided in the insulating film, the silicon and the conductive film are connected by a titanium silicide film, and the upper limit of the thickness of the titanium silicide film and the titanium The upper limit of the film thickness of the film is set respectively as defined by the internal stress of the film of the conductive film. Therefore, the interface between silicon and titanium silicide can be prevented from peeling. In addition, by controlling the thickness of the titanium silicide film thickness, the contact resistance between silicon and the conductive film can be reduced, so a semiconductor device with a good contact structure can be provided. This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) printed by the Consumer Cooperatives of the 1st Bureau of Wisdom and Finance of the Ministry of Economic Affairs; r. 417 ;: A7 B7___ 5. Description of the invention (5) [Preferred embodiment] The following A first embodiment of the present invention will be described with reference to FIGS. 1 to 5. 1 and 2A to 2D are respectively a contact structure (a structure near a contact hole) and a manufacturing method thereof in the semiconductor device of this embodiment. This semiconductor device, as shown in FIG. 1, includes a silicon substrate 1, a gate oxide film 11 and a gate electrode formed on the silicon substrate 1, and an insulating film (interlayer insulating film) 4 formed on the surface of the silicon substrate 1. . The insulating film 4 is provided with a contact hole 5. The silicon substrate 1 is formed with an element isolation region 2 and diffusion layers 3a and 3b. A titanium film 7 and a conductive film 8 are formed on the inner surface of the contact hole 5, the surface of the diffusion layer 3a on the bottom surface of the contact hole 5, and the surface of the insulating film 4. A titanium silicide film 6 is formed between the diffusion layer 3 a and the titanium film 7 inside the contact hole 5. The diffusion layer 3 a is connected to a conductive film (for example, a T i N film) 8 through the titanium silicide film 6.

圖1之半導體裝置之接觸孔構造，可藉圖2A〜2D 之製造方法製造，亦即， Λ (1 )於矽基板1上形成元件分離區域2，於矽基板 1之露出部形成閘極氧化膜1 1及閘極1 2。之後，以閘 極1 2及元件分離區域2爲覆罩於矽基板1植入雜質，以 形成擴散層3 a，3b。其斷面圖示於圖2Α。 (2 )在上述形成有各元件之矽基板1上面，形成例 如氧化矽絕緣膜4。之後，於絕緣膜4設接觸孔5。其斷 面面如圖2B。又，接觸孔5之孔徑上限較好爲0 . 4 μ m 。 (3 )'在絕緣膜4上面，接觸孔5內部之絕緣膜4之 i紙張尺度適用巾ϋ國家揉準（CNS ) ( 21GX297公兼)7〇~. -- (請先閱讀背面之注意事項再填寫本頁)The contact hole structure of the semiconductor device of FIG. 1 can be manufactured by the manufacturing method of FIGS. 2A to 2D. That is, Λ (1) forms an element separation region 2 on a silicon substrate 1 and forms a gate oxide on an exposed portion of the silicon substrate 1. Membrane 11 and gate 12. Thereafter, impurities are implanted on the silicon substrate 1 by using the gate electrode 12 and the element isolation region 2 as covers to form diffusion layers 3 a and 3 b. A cross-sectional view is shown in FIG. 2A. (2) On the silicon substrate 1 on which the elements are formed, a silicon oxide insulating film 4 is formed, for example. Thereafter, a contact hole 5 is provided in the insulating film 4. Its cross section is shown in Figure 2B. The upper limit of the pore diameter of the contact hole 5 is preferably 0.4 μm. (3) 'On the insulating film 4, the paper size of the insulating film 4 inside the contact hole 5 is suitable for national standards (CNS) (21GX297) and 70 ~.-(Please read the precautions on the back first (Fill in this page again)

A7A7

J- 4J? / TT _ B7 五、發明説明（6 ) 側壁·以及接觸孔底面之擴散層3 a上面沈積與之接觸之 鈦膜7 ’再於該鈦膜7沈積與其接觸之導電性膜8 =其斷 面圖示於圖2 C。 (4 )之後，進行熱處理使鈦膜7與擴散層3 a之矽 作矽化物反應，俾於鈦膜7與擴散層3 a之界面形成矽化 鈦膜6。其斷面圖示於圖^ D。又，矽化物反應之熱處理 溫度爲5 5 0 °C以上較好。 上述（1 )〜（4)工程之後，進行所要工程（未圖 示出）以完成半導體裝置。例如，形成第1層配線及絕緣 膜後，必要時進行第2層以後之配線及絕緣膜之形成，以 完成Μ 0 S電晶體構造等。 但是，半導體裝置之製造順序並不限定於上述說明者 ，配線層數亦不限於一層。又，亦可將該半導體裝置使用 於DRAM、 SRAM，或微電腦等。 此處，鈦膜7之膜厚上限値（nm)係設定爲，依接 於鈦膜7之導電性膜8之膜內部應力σ (MPa)，以 y = 6〇 — 0 . 012σ 所界定之値。例如，導電性膜8具1 〇 〇 〇 M P a之 膜內部應力（拉伸應力）時，鈦膜7之膜厚約爲5 0 nm 以下。藉使該膜厚5 Ο n m以下之鈦膜7作矽化物反應’ 則矽化鈦6之膜厚約爲1 2 5 nm以下。此乃因就理論而 言，假設鈦膜7之膜厚爲1，約消費厚2·3之矽’形成 (請先閱讀背面之注意事項再填寫本頁) '裝—--- ..11 本紙張尺度適用中囷囷家標率（CNS ) Μ規格（210X297公釐） -9- 417177 B7 經濟部智慧时4局負工消費合作社印製 五 發明説明（7 ) 1 I 厚 約 2 5 矽 化鈦 膜 6 0 匡 1 I 接 著 參 昭 圖 3 圖 5 說 明 本 實 施 形 態 之 作 用 效 果 〇 1 1 I 圖 3 爲 伴 隨 矽 化物 反 m 九匕、 之 矽 化鈦 膜 6 之 膜 內 部 應 力 ( 1 I 請 1 I 實 驗 之 測 定 値 ) 圖 0 由 圖 3 可 知 當 熱 處 理 溫 度 5 5 0 °c 先 聞 1 1 讀 1 I 以 上 時 膜 內 部 應 力 急 速 增 加 〇 由 此 實 驗 可 證 明 於 背 面 1 | 5 5 0 °C 以 上 產 生 矽 化物 反 應 i 故 於 矽 化鈦 膜 6 內 部 產 生 意 1 事 1 最 大 1 0 0 0 Μ P a 之 拉 伸 應 力 〇 項 再 1 圖 4 爲 考 量 圖 3 所 求 得 應 力 之 最 大値 1 0 0 0 寫 本 ϊ 装 Μ Ρ a 及 接 觸 搆 ''ih 依 有 限 要 m 1 -4 1 析 矽 化 鈦 與 矽 之 買 1 ί 界 面 所 產 生 RS 入已、 力 ( 切 斷 應 力 ) 之 結 果 〇 由 圖 4 可 知 伴 隨 1 j W 化 鉢 膜 6 之 膜 厚 增 加 或 伴 隨 接 於 矽 化 1 太 膜 6 之 導 電 性 1 I 膜 8 之 內 部 力 之增 加 則 界 面 產 生 之 應 力 亦增 加 &lt;5 爲 使 1 訂 | 不 產 生 矽 化 鈦 膜 6 之 剝 離 則 只 需 叹 計 ( 界定 ) 矽 化 鈦 膜 1 1 6 之 膜 厚 及 導 電 性 膜 8 之 膜 內 部 库 力 使 上 述 界 面所 產 生 1 1 ffffi 力 爲 剝 離 產 生 之 臨 界 應 力 値以 下 即 可 〇 1 1 圖 5 爲 使 不 致 產 生 矽 化 欽 膜 之 剝 離 時 之 矽 化 欽 膜 6 之 li 1 膜 厚 及 導 電 性 膜 ( T N 膜 ) 8 之 膜 內 部 應 力 間 之 關 係 〇 1 1 I 由 圖 5 可 知 導 電 性 膜 8 之 膜 內 部 應 力 越 小 5 不 產 生 剝 離 1 1 之 矽 化 鈦 膜 6 之界 定 膜 厚 越 厚 〇 此 時 矽 化鈦 膜 6 之 膜 厚 1 1 上 限 値 t ( η m ) 與 導 電 性 膜 8 之 膜 內 部 應 力 σ ( 1 1 Μ Ρ a ) 間 之 關 係 由 實 驗 及解析 可知 爲 1 1 I t — 1 5 0 — 0 0 3 〇 1 I 1 1 1 1 本紙張尺度適用中困國家榇準（CNS ) A4规格（2丨0X297公釐） -10- 417 A7 B7 經濟部智慈財產局8工消費合作社印製 五、發明説明（8 ) 由此關係式，若考量由鈦膜7之於矽化鈦膜6之反應 ，則沈積之鈦膜7之膜厚上限値y ( n m )與導電性膜之 膜內部應力σ ( Μ P a )間之關係’可以 y = 6〇 — 0 0 1 2 〇 表示，亦即，爲防止矽化鈦膜6之剥離’矽上（擴散層3 a上）所沈積鈦膜7之膜厚上限値’有必要設定爲依導電 性膜8之肉部應力σ ( Μ P a )而以上式決定之値。另外 ，導電性膜8之膜內部應力’可藉例如使用X線繞射測定 結晶格子之失真（亦即結晶之格子定數）而容易求得。 但是，藉由矽化鈦膜之導電性膜與矽之間之接觸電阻 ，當矽化鈦膜之膜厚爲2 0 nm以下時會上昇’此乃由經 驗可確認，因此，有必要將矽化鈦膜6之膜厚設爲2 0 n m以上=當矽化鈦膜6之膜厚爲2 0 nm時’由圖5可 知，不產生剝離之導電性膜8之膜內部應力爲4 3 0 0 MP a。因此*爲實現低接觸電阻’且不產生剝離之接觸 構造，導電性膜8之內部應力需爲4 3 0 OMP a以下。 特別是，爲實現低電阻化’較好是將導電性膜8之膜內部 應力σ設爲1 0 0 OMP a以下，將沈積之鈦膜7之膜厚 設爲5 0 n m左右，將所形成矽化鈦膜6之膜厚確保爲 1 2 5 n m左右。 依以上之本實施形態，將鈦膜7及矽化鈦膜6之膜厚 上限設爲對應於導電性膜8之膜內部應力所界定之値，則 (讀先聞讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家樣準&lt; CNS ) A4規格（210XW7公釐） .H -J- 4J? / TT _ B7 V. Description of the invention (6) Side wall · and the diffusion layer on the bottom surface of the contact hole 3 a Titanium film 7 in contact with it is deposited thereon, and a conductive film 8 in contact with it is deposited on the titanium film 7 = The cross-sectional view is shown in Figure 2C. (4) After that, heat treatment is performed to make the titanium film 7 and the silicon of the diffusion layer 3a react as silicide, and a silicon silicide film 6 is formed at the interface between the titanium film 7 and the diffusion layer 3a. Its cross-section is shown in Figure ^ D. In addition, the heat treatment temperature of the silicide reaction is preferably at least 5 0 ° C. After the above steps (1) to (4), a desired process (not shown) is performed to complete the semiconductor device. For example, after forming the first-layer wiring and insulating film, if necessary, the second-layer wiring and the insulating film are formed to complete the MOS transistor structure. However, the manufacturing order of the semiconductor device is not limited to those described above, and the number of wiring layers is not limited to one. The semiconductor device may be used in DRAM, SRAM, or a microcomputer. Here, the upper limit 値 (nm) of the film thickness of the titanium film 7 is set to be defined by y = 60-0.012 σ depending on the film internal stress σ (MPa) of the conductive film 8 connected to the titanium film 7. value. For example, when the conductive film 8 has a film internal stress (tensile stress) of 1000 MPa, the film thickness of the titanium film 7 is about 50 nm or less. If the titanium film 7 having a film thickness of 50 nm or less is subjected to silicide reaction ', the film thickness of the titanium silicide 6 is approximately 125 nm or less. This is because, theoretically, assuming that the film thickness of the titanium film 7 is 1, it consumes approximately 2 · 3 of silicon. 'Formation (please read the precautions on the back before filling this page) This paper scale is applicable to the standard of Chinese standard (CNS) M (210X297 mm) -9- 417177 B7 Printed by the Ministry of Economic Affairs, 4 Bureau of Consumers ’Cooperatives, Five Invention Instructions (7) 1 I Thickness about 2 5 Siliconized Titanium film 6 0 Kuang 1 I Next see Figure 3 Figure 5 illustrates the effect of this embodiment 0 1 1 I Figure 3 is the internal stress of the titanium silicide film 6 (1 I Please 1 I The measurement of the experiment 値) Figure 0 From Figure 3, we can know that when the heat treatment temperature is 5 5 0 ° c, the first news is 1 1 and the reading 1 is above I. The internal stress of the film increases rapidly. From this experiment, it can be proved that the back surface is 1 | 5 5 0 ° C or more. The silicide reaction i occurs in the titanium silicide film. The tensile stress of P a is 0 and then 1 Figure 4 is the maximum value of the stress obtained by considering Figure 3 値 1 0 0 0 transcript ϊ M ρ a and contact structure '' ih according to the limit m 1 -4 1 analysis of titanium silicide The result of the RS input force and the force (cutting stress) generated at the interface with the buy of silicon. From Figure 4, it can be seen that with the increase of the film thickness of the 1 j W chemical bowl film 6 or the conductivity of the silicon film 1 and the film 6 The increase in internal force of 1 I film 8 will increase the stress generated at the interface. <5 In order to make 1 order | no peeling of titanium silicide film 6 is required, the thickness of titanium silicide film 1 1 6 and The internal coercive force of the film of the conductive film 8 causes the 1 1 ffffi force generated at the above interface to be the critical stress generated by peeling. The following may be used. 1 1 Figure 5 is the siliconized film 6 when the siliconized film does not peel off. 1 Relationship between film thickness and conductive film (TN film) 8 Internal stress of film 〇1 1 I It can be seen from FIG. 5 that the smaller the internal stress of the film of the conductive film 8 is, the larger the defined film thickness of the titanium silicide film 6 that does not cause peeling 1 is. The thickness of the titanium silicide film 6 at this time 1 1 upper limit 1t The relationship between (η m) and the internal stress σ (1 1 Μ ρ a) of the conductive film 8 is known from experiments and analysis as 1 1 I t — 1 5 0 — 0 0 3 〇1 I 1 1 1 1 The paper scale is applicable to the standard of the poor countries (CNS) A4 (2 丨 0X297 mm) -10- 417 A7 B7 Printed by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) If the reaction from the titanium film 7 to the titanium silicide film 6 is considered, the relationship between the upper limit of the film thickness 値 y (nm) of the deposited titanium film 7 and the internal stress σ (MPa) of the conductive film can be y = 6〇— 0 0 1 2 〇 means, that is, in order to prevent the peeling of the titanium silicide film 6 'the upper limit of the film thickness of the titanium film 7 deposited on silicon (on the diffusion layer 3 a), it is necessary to set it according to the conductivity The stress σ (Μ P a) of the meat portion of the membrane 8 is determined by the above formula . In addition, the film internal stress' of the conductive film 8 can be easily obtained by measuring the distortion of the crystal lattice (that is, the crystal lattice constant) using X-ray diffraction. However, due to the contact resistance between the conductive film and silicon of the titanium silicide film, it will increase when the thickness of the titanium silicide film is less than 20 nm. This is confirmed by experience. Therefore, it is necessary to make the titanium silicide film The film thickness of 6 is set to 20 nm or more = When the film thickness of the titanium silicide film 6 is 20 nm ', it can be seen from FIG. 5 that the internal stress of the film of the conductive film 8 without peeling is 4 300 MP a. Therefore * In order to achieve a contact structure with low contact resistance 'and no peeling, the internal stress of the conductive film 8 needs to be 4 3 OMP a or less. In particular, in order to reduce the resistance, the film internal stress σ of the conductive film 8 is preferably set to 100 OMP a or less, and the thickness of the deposited titanium film 7 is set to about 50 nm. The thickness of the titanium silicide film 6 is ensured to be about 1 2 5 nm. According to the above embodiment, the upper limit of the film thickness of the titanium film 7 and the titanium silicide film 6 is set to be defined by the internal stress of the film corresponding to the conductive film 8. Page) This paper size is in accordance with China National Standards &lt; CNS) A4 size (210XW7mm) .H-

41 7 1 7 T 經濟部智慧財產局員工消費合作社印製 Α7 Β7五、發明説明（9 ) 可使矽化鈦膜6與矽基板1上之擴散層3 a間之界面附近 所產生應力成爲剝離產生應力値以下，可防止矽化鈦膜6 之剝離。 又，上述係以矽化物反應中未使用之未反應鈦膜7存 在於導電性膜8與矽化鈦膜6之間之場合作說明，但未反 應之鈦膜未必存在。所有鈦膜均使用於矽化物反應，且矽 化鈦膜6和導電性膜直接接觸之構成亦可。再者，鈦膜7 亦可爲含有鈦以外之成分者。 以下，參照圖6〜圖8說明本發明第2實施形態。圖 6及圖7 A〜7 D分別爲本實施形態之半導體裝置中之接 觸構造（接觸孔附近之構造）及其製造方法，圖8爲圖6 之變形例。爲簡單起見，於圖6〜圖8，與圖1〜圖2A 〜2 D相同之構件附加同一符號。 本半導體裝置，如圖6所示，具有：矽基板1，形成 於矽基板1上之閘極氧化膜1 1及閘極1 2，及形成於矽 基板1表面之絕緣膜（層間絕緣膜）4。於絕緣膜4設接 觸孔5 =另，於矽基板1上形成元件分離區域2、擴散層 3 a、3b，於接觸孔5內部之擴散層3 a上沈積多晶矽 1 0，於接觸孔5內面，接觸孔5底面之多晶矽1 0表面 ，及絕緣膜4表面形成有鈦膜7及導電性膜8 »又，於接 觸孔5內部，於多晶矽1 0與鈦膜7之間形成矽化鈦膜6 ，多晶矽10與導電性膜8藉由矽化鈦膜6連接 圖6之半導體裝置之接觸構造，可藉圖7A〜7D之 製造方法製造，亦即， 本紙張尺度適用中國國家標準（CNS ) A4規格（210乂 297公釐) · 12 - (讀先鬩讀背面之注意事項再填寫本頁) '417177 λ7 ____Β7 五、發明説明（1〇 ) (请先閱讀背面之注意事項再填寫本頁) (5 )於矽基板1上形成元件分離區域2，於矽基板 1之露出部形成閘極氧化膜1 1及閘極1 2。接著，以間 極1 2及元件分離區域2爲覆罩於矽基板1植入雜質，以 形成擴散層3 a、3b。其斷面圖示於圖7A。 (6 )於上述形成有各元件之矽基板1上面，形成例 如氧化矽構成之絕緣膜4，於絕緣膜4設接觸孔5。之後 ’於絕緣膜4上面，接觸孔5內部之絕緣膜4側壁，及接 觸孔5底面之擴散層3 a上面，藉例如CVD法沈積與之 接觸之多晶矽1 0，將多晶矽埋入接觸孔5內部。之後， 藉蝕刻除去沈積於絕緣膜4上面之多餘多晶矽。於此階段 ，如圖7 B之斷面圖所示，成爲多晶矽1 〇沈積於接觸孔 5內部之狀態。又，接觸孔5之孔徑上限較好爲◦. 4 # m。 (7 )沈積接觸於絕緣膜4上面，接觸孔5內部之絕 緣膜4之側壁，及接觸孔底面之多晶矽1 0上面之鈦膜7 &lt; ，之後，沈積接觸於該鈦膜7之導電性膜8。其斷面圖示 於圖7 C。 經濟部智慧財產局員工消費合作社印製 (8 )之後，進行熱處理以使鈦膜7與多晶矽1 0之 矽作矽化物反應，於鈦膜7與多晶矽1 0之界面形成矽化 鈦膜6。其斷面圖示於圖7D。又，矽化物反應之熱處理 溫度較好爲5 5 0 °C以上。 ‘ 上述（5 )〜（8 )工程之後，進行所要工程（圖示 省略）以完成半導體裝置。例如，形成第1層配線及絕緣 膜後，必要時進行第2層以後之配線及絕緣膜之形成，以 本紙張尺度逋用中國國家樣準（CNS ) A4規《格（210X297公釐） _ 13 · 經濟部智慧財產局8工消費合作社印製 I 乂… A7 _B7_ 五、發明説明（彳1 ) 完成Μ 0 S電晶體構造等。 但是，半導體裝置之製造順序’並不限定爲上述說明 者，配線層數亦不限於一層。另’該半導體裝置亦可使用 於DRAM、 SRAM，或微電腦等。 此時，和第1實施形態同樣’鈦膜7之膜厚上限値（ n m )，係依接觸於鈦膜7之導電性膜8 (例如T i N膜 等）之膜內部應力σ (MPa)，設定爲 y = 60-0 . 012σ 所界定之値。另外，此時之矽化鈦膜6之膜厚上限値t ( n m )，係依導電性膜8之膜內部應力¢7 ( Μ P a )，設 定爲 t=150-0.03a 所界定之値。 本實施形態之變形例，如圖8之構成。亦即，於圖6 之半導體裝置之導電性膜（例如T i N膜等）8之上，再 沈積鎢膜9，以鈦膜7、導電性膜8、及鎢膜9構成3層 構造之電氣配線1 3。 依上述本實施形態，則可得和第1實施形態同樣之作 用效果，可防止矽化鈦膜6之剝離。又，於本實施形態可 .獲得，沈積多晶矽1 0之工程爲必要之，於多晶矽1 0埋 (請先閱讀背面之注意事項再填寫本頁)41 7 1 7 T Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (9) The stress near the interface between the titanium silicide film 6 and the diffusion layer 3 a on the silicon substrate 1 can be caused by peeling Below the stress, the peeling of the titanium silicide film 6 can be prevented. The above description is based on the fact that the unreacted titanium film 7 not used in the silicide reaction exists in the field cooperation between the conductive film 8 and the titanium silicide film 6, but the unreacted titanium film does not necessarily exist. All titanium films are used for silicide reaction, and a structure in which the titanium silicide film 6 and the conductive film are in direct contact with each other may be used. The titanium film 7 may be a component containing a component other than titanium. Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 6 to 8. 6 and 7A to 7D are respectively a contact structure (structure near a contact hole) and a manufacturing method thereof in the semiconductor device according to this embodiment, and FIG. 8 is a modification example of FIG. 6. For simplicity, in FIGS. 6 to 8, the same components as those in FIGS. 1 to 2A to 2D are denoted by the same reference numerals. As shown in FIG. 6, this semiconductor device includes a silicon substrate 1, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer insulating film) formed on the surface of the silicon substrate 1. 4. A contact hole 5 is set in the insulating film 4. In addition, element isolation regions 2, diffusion layers 3 a and 3 b are formed on the silicon substrate 1, and polycrystalline silicon 10 is deposited on the diffusion layer 3 a inside the contact hole 5. A titanium film 7 and a conductive film 8 are formed on the surface of the polycrystalline silicon 10 on the bottom surface of the contact hole 5 and on the surface of the insulating film 4. In the contact hole 5, a titanium silicide film is formed between the polycrystalline silicon 10 and the titanium film 7. 6. The contact structure of the polycrystalline silicon 10 and the conductive film 8 connected to the semiconductor device of FIG. 6 through the titanium silicide film 6 can be manufactured by the manufacturing method of FIGS. 7A to 7D, that is, the paper standard applies to the Chinese National Standard (CNS) A4 Specifications (210 乂 297mm) · 12-(Read the notes on the back before filling this page) '417177 λ7 ____ Β7 V. Description of the invention (1〇) (Please read the notes on the back before filling this page) (5) An element isolation region 2 is formed on the silicon substrate 1, and a gate oxide film 11 and a gate electrode 12 are formed on the exposed portion of the silicon substrate 1. Next, the silicon substrate 1 is implanted with the intermediate electrode 12 and the element isolation region 2 as covering to form the diffusion layers 3a and 3b. A cross-sectional view is shown in FIG. 7A. (6) On the silicon substrate 1 on which the elements are formed, an insulating film 4 made of, for example, silicon oxide is formed, and a contact hole 5 is provided in the insulating film 4. After that, on the insulating film 4, on the sidewalls of the insulating film 4 inside the contact hole 5, and on the diffusion layer 3 a on the bottom surface of the contact hole 5, polycrystalline silicon 10 in contact with it is deposited by, for example, CVD, and the polycrystalline silicon is buried in the contact hole 5 internal. After that, the excess polycrystalline silicon deposited on the insulating film 4 is removed by etching. At this stage, as shown in the cross-sectional view of FIG. 7B, polycrystalline silicon 10 is deposited in the inside of the contact hole 5. The upper limit of the pore diameter of the contact hole 5 is preferably ◦. 4 # m. (7) The titanium film 7 &lt; deposited on the insulating film 4, the sidewall of the insulating film 4 inside the contact hole 5, and the polycrystalline silicon 10 on the bottom of the contact hole is deposited, and then the conductivity of the titanium film 7 is deposited. Film 8. A cross-sectional view is shown in Fig. 7C. After printing (8) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, heat treatment is performed to make the titanium film 7 react with the silicon of the polycrystalline silicon 10 as silicide, and a silicided titanium film 6 is formed at the interface between the titanium film 7 and the polycrystalline silicon 10. A cross-sectional view is shown in FIG. 7D. The heat treatment temperature of the silicide reaction is preferably 5 50 ° C or higher. ‘After the above steps (5) to (8), perform the required process (not shown) to complete the semiconductor device. For example, after forming the first layer of wiring and insulation film, if necessary, perform the formation of the second layer of wiring and insulation film, and use the Chinese National Standard (CNS) A4 rule "Grid (210X297 mm)" at this paper size. _ 13 · Printed by the 8th Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs I 乂… A7 _B7_ V. Description of the invention (彳 1) Complete the M 0 S transistor structure. However, the manufacturing sequence of the semiconductor device is not limited to the one described above, and the number of wiring layers is not limited to one. The semiconductor device can also be used in DRAM, SRAM, or microcomputer. At this time, the upper limit of the film thickness 钛 (nm) of the titanium film 7 is the same as that of the first embodiment, which depends on the internal stress σ (MPa) of the film in contact with the conductive film 8 (such as a T i N film) of the titanium film 7. , Set to 値 defined by y = 60-0. 012σ. In addition, the upper limit of the film thickness 値 t (n m) of the titanium silicide film 6 at this time is set to 値 defined by t = 150-0.03a according to the film internal stress ¢ 7 (MPa) of the conductive film 8. A modified example of this embodiment has a structure as shown in FIG. 8. That is, a tungsten film 9 is further deposited on the conductive film (such as a T i N film, etc.) 8 of the semiconductor device of FIG. 6, and a titanium film 7, a conductive film 8, and a tungsten film 9 constitute a three-layer structure. Electrical wiring 1 3. According to this embodiment, the same effect as that of the first embodiment can be obtained, and peeling of the titanium silicide film 6 can be prevented. Also, it can be obtained in this embodiment. The process of depositing polycrystalline silicon 10 is necessary, and buried in polycrystalline silicon 10 (please read the precautions on the back before filling this page)

i紙張尺度適用中國國家標率{ CNS ) A4規格（210X297公釐) _彳4 - 41 7 A7 B7 經濟部智慈財產局8工消费合作社印製 五、發明説明（12 ) 入有接觸孔，其深度變淺，故次工程之鈦膜及導電性膜8 之沈積變爲容易。 又，於本實施形態中，不一定存在未反應之鈦膜，亦 可構成爲使用全部鈦膜於矽化物反應俾使矽化鈦膜6與導 電性膜8直接接觸。鈦膜7亦可含有鈦以外之成分。 以下，參照圖9及圖，1 0A〜1 0D說明本發明第3 實施形態，本實施形態係關於Μ 0 S電晶體之閘極接觸構 造，圖9及圖1 0Α〜1 0D分別爲本實施形態之半導體 裝置中之接觸構造（接觸孔附近之構造）及其製造方法。 但是，爲簡單起見，圖9及圖1 Ο Α〜1 0 D中’和圖1 及圖2 A〜2 D相同之構造附加同一符號。 本半導體裝置，如圖9所示，具備：矽基板1 ’形成 於矽基板1上之閘極氧化膜1 1及閘極1 2，及形成於矽 基板1表面之絕緣膜（層間絕緣膜）4。於絕緣膜4之閘 極1 2上設接觸孔5。另外，於接觸孔5內面’接觸孔底 面之閘極1 2表面，及絕緣膜4表面形成鈦膜7及導電性 膜8。於接觸孔5內部，於閘極1 2與鈦膜7之間形成矽 ~^||丨·-------- 化鈦膜6，閘極1 2及導電性膜（例如T i N膜等）8係 藉由矽化鈦膜6連接。 圖9之半導體裝置之接觸構造，可藉圖1 〇A〜1 0 D之製造方法。亦即， (9 )於矽基板1上形成約1 5 nm厚之矽氧化膜’ 之後，藉CVD法等於矽氧化膜上形成多晶矽膜’藉光蝕 刻法形成阻劑圖型，爲該阻劑圖型爲覆罩藉乾蝕刻法對多 (請先閱讀背面之注意事項再填寫本頁) -5 本紙張尺度速用中國國家橾隼（CNS ) A4規格（210X297公釐） .15- 417177 經濟部智慧財產局員工消費合作社印焚 A7 B7五、發明説明（彳3 ) 晶矽膜及矽氧化膜進行圖型化處理以形成由閘極氧化膜 1 1及多晶矽構成之閘極1 2。其斷面圖示於圖1 0A。 (1 0 )於矽基板1上面形成例如氧化矽之絕緣膜4 。之後，於絕緣膜4設深及閘極1 2之接觸孔5。其斷面 圖示於圖10B。又，接觸孔5之孔徑上限較好爲0 . 4 β m ° (1 1 )於絕緣膜4上面，接觸孔5內部之絕緣膜4 之側壁，及接觸孔底面之閘極1 2上面沈積與其接觸之鈦 膜7，之後：沈積與該鈦膜7接觸之導電性膜8。其斷面 圖示於圖1 0 C。 (1 2 )之後，進行熱處理使鈦膜7及閘極1 2之矽 起矽化物反應，以鈦膜7及閘極1 2之界面形成矽化鈦膜 6。其斷面圖示於圖1 0D。又，矽化物反應之熱處理溫 度爲5 5 0 t以上。 上述（9 )〜（1 2 )工程之後，進行所要之工程（ 圖中省略）以完成半導體裝置。例如，形成第1層配線及 絕緣膜後，必要時形成第2層以後之配線及絕緣瞑，以完 成MO S電晶體構造。 但是，半導體裝置之製造順序不限於上述所說明者， 配線層數亦不限於一層》又，該半導體裝置亦可使用於 DRAM、SRAM、或微電腦等。 此時 &gt; 和第1實施形態用樣地，鈦膜7之膜厚上限値 (nm)、及矽化鈦膜6之膜厚上限値t (nm)，係依 接於鈦膜7之導電性膜8 (例如T i N膜等）之膜內部應 ---------iar.裝---- (請先閱讀背面之注意事項再填寫本頁} 訂 本紙張尺度適用中困國家橾準（CNS)A4規格&lt;210Χ297公釐） -16- 「41717/ A7 B7 經濟部智恶財產局員工消費合作杜印製 五、 發明説明 (14 ) I 1 力 〇 ( Μ Ρ a ) 設 定 爲 上 述 式所界定 之値 〇 依 本 實 施 形 1 1 態 9 則 可 得 和 第 1 實 施 形 態 相 同 之作 用 效果 1 防 止 矽化 鈦 1 1 膜 6 之 剝 離 〇 V 1 I 請 1 I 又 * 本 實 施 形 態 中 ， 未 必 一 定存在未反 應 之 鈦 膜 f 亦 先 閲 1 | 可 將 全 部 鈦 膜 使 用 於砂 化物 反 施 m 而形 成 矽化 鈦 膜 6 與 導 電 背 面 1 | 性 膜 8 直 接 接 觸 之 構 造 &gt; 又 » 鈦 膜7 亦 可含鈦 以 外 之 成 分 '意 1 事 I 項 | 再 接 著 y 以 圖 1 1 及 圖 1 2 A 〜1 2 D說 明 本 發 明 第 4 寫 本 霄 裝 實 施 形 態 0 本 實 施 形 態 爲 關 於 Μ 0 S 電 晶體 之 閘 極 之 接 觸 頁 1 1 1 構 造 者 圖 1 1 及 圖 1 2 A 1 2D 分 別爲 本 實 施 形 態 之 1 1 半 導 體 裝 置 中 之 接 觸 構 造 ( 接 觸 孔附 近 構造 ) 及 其 製 造 方 1 I 法 0 但 是 爲 簡 單 起 見 圖 1 1 及圖 1 2 A 1 2 D 中 ， 1 訂 | 和 圖 1 及 圖 2 A 2 D 相 同 之 構 件附加 同一 符 號 0 1 本 半 導 體 裝 置 如 圖 1 1 所 示， 具 備. 矽 基 板 1 形 1 1 成 於矽 基 板 1 上 之 閘 極 氧 化 膜 1 1及 閘 極1 2 及 形 成 於 ! 矽 基 板 1 表 面 之 絕 緣 膜 ( 層 間 絕 緣膜 ) 4 ° 絕 緣 膜 4 之 閘 ▲ 1 極 1 2 上 5几 叹 接 觸 孔 5 9 另 於 接 觸孔 5 內部 之 閘 極 1 2 上 1 I | 沈 積 多 晶 矽 1 0 於 接 觸 孔 5 內 面， 接 觸孔 5 底 面 之 多 晶 1 1 矽 1 0 表 面 T 及 絕 緣 膜 4 表 面 形 成鈦 膜 7及 導 電 性 膜 8 〇 1 1 再 者 ♦ 接 觸 孔 5 內 部 9 於 多 晶砂 10 與 鈦膜 7 之 間 形 成 矽 1 1 化 §太 膜 6 &gt; 多 晶 矽 1 0 及 導 電 性 膜（ 例如T i N 膜 等 ) 8 1 I 係 藉 由 矽 化 鈦 膜 6 連 接 〇 1 1 I 圖 1 1 之 半 導 體 裝 置 之 接 itmi 觸 構造 &gt; 係依 圖 1 2 A 1 1 1 2 D 之 製 造 方法 製 造 0 亦即 $ 1 1 1 本紙張尺度速用中國國家標準（CNS)A4洗格（210X297公釐） _ 17 ί 41717 Α7 經濟部智慧財產局員工消費合作社印製 Β7_五、發明説明（15 ) (1 3 )於矽基板1上形成約1 5 nm厚之:矽氧化膜 ，之後，藉C V D法於矽氧化膜上形成多晶矽膜，以光蝕 刻法形成阻劑圖型，以該阻劑圖型爲覆罩藉乾蝕刻法對多 晶矽膜及矽氧化膜進行圖型化處理以形成由閘極氧化膜 1 1及多晶矽構成之閘極1 2。其斷面圖示於圖1 2A。 (14)於矽基板1上面形成例如氧化矽之絕緣膜4 ，於絕緣膜4設深及閘極1 2之接觸孔5。之後，藉C V D法沈積連接於絕緣膜4上面，接觸孔5內部絕緣膜4側 壁1及接觸孔5底靣之閘極1 2上靣的多晶矽1 0 ’使多 晶矽埋入接觸孔5內部。之後，藉蝕刻除去沈積於絕緣膜 4上面之多餘多晶矽。於此階段，如1 2 B之斷面圖所示 成爲多晶矽10沈積於接觸孔5內部之狀態。又，接觸孔 5之孔徑上限較好爲0 . 4 // m。 (1 5 )沈積連接於絕緣膜4上面，接觸孔5內部之 絕緣膜4之側壁，及接觸孔底面之多晶矽1 0上面的鈦膜 7，之後，沈積連接於該鈦膜7之導電性膜8。其斷面圖 示於圖1 2 C。 (1 6 )之後，進行熱處理使鈦膜7及多晶矽1 0之 矽起矽化物反應，俾於鈦膜7與多晶矽1 0之界面形成矽 化鈦膜6。其斷面圖示於圖1 2 D。又’矽化物反應之熱 處理溫度爲5 5 0 °C以上》 上述（1 3)〜（1 6)工程之後’進ίτ所要工程（ 圖示省略）以完成半導體裝置。例如，形成第1層配線及 絕緣膜後，必要時形成第2層以後之配線及絕緣膜以完成 (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國囡家橾準（CNS ) Α4规格（2丨0X297公漦） .18- 經濟部智慧財度局負工消費合作杜印製 ί 417 17 7 at _Β7__五、發明説明（16 ) Μ 0 S電晶體構造。 但是，半導體裝置之製造順序不限於上述說明者，配 線層數亦不限於一層。又1該半導體裝置亦可使用於 DRAM、SRAM、或微電腦等。 此時，和第1實施形態同樣地，鈦膜7之膜厚上限値 (n m )、及矽化鈦膜6之膜厚上限値（n m )，係依連 接於鈦膜7之導電性膜8 (例如T i N膜等）之膜內部應 力σ (MPa)，設定爲上述式所界定之値。依本實施形 態，則可得和第一實施形態相同之作用效果，可防止矽化 欽膜6之剝離。又，本實施形態中亦可得，沈積多晶砂 1 0之工程爲必要之，接觸孔5爲多晶矽1 0埋入使其深 度變淺，使次一工程之鈦膜7及導電性膜8之沈積變容易 之效果。 又，於本實施形態中，未必存在未反應之鈦膜，亦可 使用全部鈦膜於矽化物反應以形成矽化鈦膜6與導電性膜 8直接接觸之構成。鈦膜7亦可含有鈦以外之成分。 以下1參照圖1 3說明本發明第5實施形態。本實施 形態係關於形成有DRAM之半導體基板之主要部分（記 億陣列及周邊電路之一部分）之接觸構造’爲具第1實施 形態及第2實施形態兩方之構成之實施形態。 圖1 3之矽基板1 0 1之主面形成有記憶陣列1 〇 〇 A (圖之中央左側）及周邊電路區域10 0B (圖之中央 右側）。於記億陣列1 0 0 A之主動區域形成多數 D R A Μ之記憶格，各記億格係由1個記億體選擇用 {請先閲讀背面之注意事項异填寫本頁) 本紙張尺反適用中菌因家標牟（CNS)A4規格（2丨0X297公釐） _19_ 經濟部智慧財1局員工消脅合作社印製 A7 _____ B7 _五、發明説明（17 ) MO S電晶體Q t及配置於其上部之1個資訊儲存用電容 元件C所構成。亦即，記億格1 〇 〇 A，係以記憶體選擇 用MO S電晶體Q t之上部配置有資訊儲存用電容元件C 之疊層電容器構造來構成，各MO S電晶體Q t係由場氧 化膜1 0 2作元件分離。 記憶格1 Ο Ο A中之記億格選擇用Μ〇S電晶體Q t 係由閘極氧化膜1 1 1、閛極1 1 2 a ，及一對擴散層 1 0 3 a ，1 〇 3 b (源極、汲極區域）構成。閘極 1 1 2 a係由例如多晶矽膜搆成，與字元線W L —體構成 〇 於周邊電路區域1 Ο Ο B之主動區域形成有多數 MO S電晶體Q 1 ，Q 2 .......。此DRAM之週邊電路 區域1 Ο Ο B亦可由組合η通道型MO S電晶體與P通道 型MO S電晶體之CMO S電路構成。周邊電路區域 1 Ο Ο Β之M〇 S電晶體Q 1 ，Q 2........係由閘極氧 化膜1 1 1、閘極1 12b、及一對擴散層103c、 103d(源極、汲極區域）構成。 在記憶格1 0 0 A中之Μ 0 S電晶體Q t之閘極 112a，及周邊電路區域100B之MOS電晶體Q1 ，Q 2 .......之閘極1 1 2 b之上部及側壁，分別形成氧 化矽膜1 0 5。又，在覆蓋記億格選擇用MOS電晶體 Q t之氧化矽膜1 0 5上部形成資訊儲存用電容元件C 1 資訊儲存用電容元件C係接於記憶格選擇用Μ 0 S電晶體 Qt之一方之擴散層103a。因此’記憶格100Α之 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逍用中國國家標準（CNS &gt; A4规格（210X W7公釐） -20 - f 417ίί7 A7 B7_ 五、發明説明（18 ) 資訊儲存用電容元件C，及周邊電路區域1 0 0 B之 Μ 0 S電晶體Q 1 ，Q 2 .......，之上部全面分別形成有 (請先閏讀背面之注^^項再填寫本頁) 例如 B P S G ( Boron doped Phospho Silicate Glass ) 膜等之絕緣膜104。 在記憶格選擇用MO S電晶體Q t之另一方擴散層 103b上方，於絕緣膜104上設有接觸孔201，於 該接觸孔201內部埋入多晶矽1 10。擴散層l〇3bi The paper scale is applicable to China's national standard {CNS) A4 specification (210X297mm) _ 彳 4-41 7 A7 B7 Printed by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) There are contact holes, Its depth becomes shallow, so the deposition of the titanium film and the conductive film 8 in the sub-process becomes easy. In this embodiment, an unreacted titanium film does not necessarily exist, and it is also possible to use a structure in which all titanium films are reacted with silicide to bring the titanium silicide film 6 and the conductive film 8 directly into contact. The titanium film 7 may contain components other than titanium. Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 9 and FIG. 10A to 10D. This embodiment relates to the gate contact structure of the M 0 S transistor, and FIG. 9 and FIG. A contact structure (a structure near a contact hole) in a semiconductor device of a specific form and a method for manufacturing the same. However, for the sake of simplicity, in FIG. 9 and FIG. 10A to 10D, the same structure as that of FIG. 1 and FIG. 2A to 2D is denoted by the same reference numeral. As shown in FIG. 9, this semiconductor device includes a silicon substrate 1 ′, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer insulating film) formed on the surface of the silicon substrate 1. 4. A contact hole 5 is provided in the gate electrode 12 of the insulating film 4. A titanium film 7 and a conductive film 8 are formed on the surface of the gate electrode 12 on the inner surface of the contact hole 5 and the bottom surface of the contact hole 5 and the surface of the insulating film 4. Inside the contact hole 5, a silicon is formed between the gate electrode 12 and the titanium film 7 ~ ^ || 丨 ------------ titanium oxide film 6, the gate electrode 12 and a conductive film (such as T i N film, etc.) 8 are connected by a titanium silicide film 6. The contact structure of the semiconductor device of FIG. 9 can be obtained by the manufacturing method of FIGS. 10A to 10D. That is, (9) After forming a silicon oxide film having a thickness of about 15 nm on the silicon substrate 1, the CVD method is equivalent to forming a polycrystalline silicon film on the silicon oxide film. The photoresist method is used to form a resist pattern, which is the resist. The pattern is cover-to-multiple by dry etching (please read the precautions on the back before filling this page) -5 This paper size is fast-moving China National Standard (CNS) A4 specification (210X297 mm). 15- 417177 Economy Intellectual Property Cooperative of the Ministry of Intellectual Property Bureau, A7, B7, V5. Invention Description (发明 3) The crystalline silicon film and silicon oxide film are patterned to form a gate electrode 12 composed of a gate oxide film 11 and polycrystalline silicon. A cross-sectional view is shown in FIG. 10A. (1 0) An insulating film 4 made of, for example, silicon oxide is formed on the silicon substrate 1. Then, a contact hole 5 is formed in the insulating film 4 and the gate electrode 12 is deep. The cross-sectional view is shown in Fig. 10B. In addition, the upper limit of the aperture of the contact hole 5 is preferably 0.4 β m ° (1 1) on the insulating film 4, the sidewalls of the insulating film 4 inside the contact hole 5, and the gate electrode 12 on the bottom surface of the contact hole are deposited thereon. The titanium film 7 in contact, and thereafter: a conductive film 8 in contact with the titanium film 7 is deposited. The cross-section is shown in Figure 10C. (12) After that, heat treatment is performed to cause silicide of the silicon of the titanium film 7 and the gate electrode 12 to form a titanium silicide film 6 at the interface between the titanium film 7 and the gate electrode 12. A cross-sectional view is shown in FIG. 10D. The heat treatment temperature of the silicide reaction is 5 5 0 t or more. After the above steps (9) to (12), a desired process (omitted from the figure) is performed to complete the semiconductor device. For example, after forming the first-layer wiring and insulating film, if necessary, forming the second-layer wiring and the insulating layer to complete the MOS transistor structure. However, the manufacturing order of the semiconductor device is not limited to those described above, and the number of wiring layers is not limited to one layer. The semiconductor device can also be used in DRAM, SRAM, or microcomputer. At this time, as in the first embodiment, the upper limit of the film thickness 钛 (nm) of the titanium film 7 and the upper limit of the film thickness 値 t (nm) of the titanium silicide film 6 depend on the conductivity of the titanium film 7 The inside of the film 8 (such as T i N film, etc.) should be --------- iar. Installed ---- (Please read the precautions on the back before filling this page} National Standards (CNS) A4 Specification &lt; 210 × 297 mm) -16- "41717 / A7 B7 Printed by the Consumer Consumption Co-operation of Intellectual Property Office of the Ministry of Economic Affairs V. Invention Description (14) I 1 Force 0 (Μ Ρ a) It is set to be defined by the above formula. According to Embodiment 1 1 State 9 of this embodiment, the same effect and effect as those in the first embodiment can be obtained. 1 Prevention of peeling of titanium silicide 1 1 Film 6 OV 1 I Please 1 I Again * This implementation In the form, there may not necessarily be an unreacted titanium film f. Also read 1 | All titanium films can be used for sanding to apply m to form titanium silicide film 6 and conductive back surface 1 | &gt; Also »Titanium film 7 may also contain components other than titanium. 'I matter 1 item I | Next, the fourth embodiment of the present invention will be described with reference to FIGS. 1 1 and 1 2 A to 1 2 D. 0 This implementation The form is about the contact of the gate of the M 0 S transistor. Figure 1 1 and Figure 1 2 A 1 2D are the contact structures (structure near the contact hole) in the semiconductor device 1 and 1 of this embodiment, respectively. Its manufacturing method 1 I method 0 but for the sake of simplicity in Figure 1 1 and Figure 1 2 A 1 2 D, 1 order | the same components as in Figure 1 and Figure 2 A 2 D with the same symbol 0 1 This semiconductor device is shown in Figure As shown in 1 1, it has: silicon substrate 1 shape 1 1 gate oxide film 11 and gate 12 formed on silicon substrate 1 and insulating film (interlayer insulating film) formed on the surface of silicon substrate 1 4 ° insulation Gate of membrane 4 ▲ 1 pole 1 2 5 sigh contact hole 5 9 another Contact gate 5 inside gate 1 2 on 1 I | deposit polycrystalline silicon 1 0 on the inside of contact hole 5, polycrystalline silicon on the bottom of contact hole 1 1 silicon 1 0 surface T and insulating film 4 titanium film 7 and conductivity Film 8 〇1 1 In addition, ♦ contact hole 5 inside 9 forms silicon 1 1 between polycrystalline sand 10 and titanium film 7 太 Tai film 6 &gt; polycrystalline silicon 10 and conductive film (such as T i N film, etc.) 8 1 I is connected by titanium silicide film 6 〇 1 1 I Figure 1 1 Itmi contact structure of the semiconductor device &gt; is manufactured according to the manufacturing method of Figure 1 2 A 1 1 1 2 D 0, that is, $ 1 1 1 Quickly use the Chinese national standard (CNS) A4 (4) (210X297 mm) of this paper scale _ 17 ί 41717 Α7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs B7_V. Description of the invention (15) (1 3) on a silicon substrate A silicon oxide film having a thickness of about 15 nm is formed on the substrate 1, and then, a polycrystalline silicon film is formed on the silicon oxide film by CVD, and a resist pattern is formed by the photoetching method, and the resist pattern is used as a cover for dry etching. law The polycrystalline silicon film and the silicon oxide film are patterned to form a gate oxide film 11 and a gate electrode 12 made of polycrystalline silicon. A cross-sectional view is shown in FIG. 12A. (14) An insulating film 4 such as silicon oxide is formed on the silicon substrate 1, and a contact hole 5 is formed in the insulating film 4 with a depth and a gate electrode 12. Thereafter, polycrystalline silicon 10 0 ′ which is connected to the upper surface of the insulating film 4 and is connected to the insulating film 4 by the C VD method, and the gate 1 of the insulating film 4 inside the contact hole 5 and the gate 12 of the bottom of the contact hole 5 is buried in the polycrystalline silicon. Thereafter, the excess polycrystalline silicon deposited on the insulating film 4 is removed by etching. At this stage, as shown in the cross-sectional view of 1 2 B, the polycrystalline silicon 10 is deposited inside the contact hole 5. The upper limit of the pore diameter of the contact hole 5 is preferably 0.4 / m. (1 5) Deposit a titanium film 7 connected to the insulating film 4, the sidewall of the insulating film 4 inside the contact hole 5, and the polycrystalline silicon 10 on the bottom surface of the contact hole, and then deposit a conductive film connected to the titanium film 7. 8. The sectional view is shown in Figure 1 2C. (16) After that, heat treatment is performed to make the silicon of the titanium film 7 and the polycrystalline silicon 10 react with silicide, and a titanium silicide film 6 is formed at the interface between the titanium film 7 and the polycrystalline silicon 10. The cross-sectional view is shown in Fig. 1 2D. The heat treatment temperature of the silicide reaction is above 5 50 ° C. After the above (1 3) to (16) processes, the required process (not shown) is completed to complete the semiconductor device. For example, after forming the first layer of wiring and insulating film, if necessary, form the second layer of wiring and insulating film to complete (read the precautions on the back first and then fill out this page). CNS) Α4 specifications (2 丨 0X297) 漦. 18- Du Yinzhu, Co-operation and Consumption Cooperation, Ministry of Economic Affairs, Ministry of Economic Affairs 417 17 7 at _Β7__ V. Description of the invention (16) M 0 S transistor structure. However, the manufacturing order of the semiconductor device is not limited to those described above, and the number of wiring layers is not limited to one. The semiconductor device can also be used in DRAM, SRAM, or microcomputer. At this time, as in the first embodiment, the upper limit 値 (nm) of the film thickness of the titanium film 7 and the upper limit 値 (nm) of the film thickness of the titanium silicide film 6 depend on the conductive film 8 ( For example, the film internal stress σ (MPa) of T i N film is set to 値 defined by the above formula. According to this embodiment, the same effect as that of the first embodiment can be obtained, and peeling of the silicidated film 6 can be prevented. Also, in this embodiment, the process of depositing polycrystalline sand 10 is necessary, and the contact hole 5 is buried with polycrystalline silicon 10 to make the depth shallow, so that the titanium film 7 and the conductive film 8 of the next process are buried. The effect of easy deposition. In this embodiment, an unreacted titanium film does not necessarily exist, and all titanium films may be reacted with silicide to form a structure in which the titanium silicide film 6 and the conductive film 8 are in direct contact. The titanium film 7 may contain components other than titanium. Hereinafter, a fifth embodiment of the present invention will be described with reference to Figs. This embodiment is a contact structure of a main part of a semiconductor substrate on which a DRAM is formed (a part of a 100 million array and peripheral circuits) ', which is an embodiment having both the first embodiment and the second embodiment. The main surface of the silicon substrate 101 of FIG. 13 is formed with a memory array 100 A (the center on the left side of the figure) and a peripheral circuit area 100B (the center on the right side of the figure). Most of the DRA M memory cells are formed in the active area of 100 A of 100 million arrays. Each one of the 100 million cells is selected by a single one. (Please read the precautions on the back first and fill in this page) This paper rule is not applicable CNS A4 Specification (2 丨 0X297mm) _19_ Printed by A7, Employees' Co-operative Cooperative, Ministry of Economic Affairs, Ministry of Economic Affairs, A7 _____ B7 _V. Description of the Invention (17) MO S transistor Q t and configuration A capacitor C for information storage is formed on the upper part. That is to say, the 100A grid is composed of a multilayer capacitor structure in which an information storage capacitor element C is arranged above the MOS transistor Qt for memory selection. Each MOS transistor Qt is composed of The field oxide film 102 is separated as an element. The memory cell 1 〇 〇 A billion grid selection MOS transistor Q t is composed of the gate oxide film 1 1 1, the cathode 1 1 2 a, and a pair of diffusion layers 1 0 3 a, 1 〇 3 b (source, drain region). The gate electrode 1 1 a is composed of, for example, a polycrystalline silicon film, and is formed with the word line WL as a body. A large number of MO S transistors Q 1, Q 2 are formed in the active area of the peripheral circuit area 1 〇 〇 B. .... The peripheral circuit area 1 0 B of this DRAM may also be composed of a CMO S circuit that combines an η-channel MOS transistor and a P-channel MOS transistor. The MOS transistors Q 1, Q 2 of the peripheral circuit area 1 〇 Β are composed of a gate oxide film 1 1 1, a gate 1 12 b, and a pair of diffusion layers 103 c and 103 d ( Source, drain region). Gate 112a of M 0 S transistor Q t in memory cell 100 A, and gate 1 1 2 b of MOS transistor Q 1, Q 2... In peripheral circuit area 100B And sidewalls, respectively, forming a silicon oxide film 105. In addition, an information storage capacitor element C 1 is formed on the silicon oxide film 1 0 5 covering the MOS transistor Q t for selection of terabytes, which is connected to the M 0 S transistor Qt for memory cell selection. One diffusion layer 103a. Therefore, 'memory cell 100A (please read the precautions on the back before filling this page) This paper size is free of Chinese national standards (CNS &gt; A4 size (210X W7 mm) -20-f 417ί 7 A7 B7_ V. Description of the invention (18) Capacitor element C for information storage, and M 0 S transistors Q 1, Q 2... In the surrounding circuit area 100 B. The upper part is formed separately (please read the back part first) Note ^^ Please fill in this page again) For example, an insulating film 104 such as a BPSG (Boron doped Phospho Silicate Glass) film. Above the other diffusion layer 103b of the memory cell selection MOS transistor Qt, set on the insulating film 104 There is a contact hole 201, and polycrystalline silicon 10 is buried inside the contact hole 201. The diffusion layer 103b

係藉由接觸孔2 0 1內之多晶矽1 1 0連接於位元線B L 0 於周邊電路區域1 0 0 B ’於MO S電晶體Q 1之一 方擴散層1 0 3 C上方之絕緣膜1 0 4上設有接觸孔 202，藉由該接觸孔202連接位元線BL。乂，於 M〇S電晶體Q 1之另一方擴散層1 〇 3 d上方之絕緣膜 1 0 4設接觸孔2 0 3 ’藉由該接觸孔2 0 3連接第1層 配線1 1 3a »再者’於M0S電晶體Q2之擴散層 4 經濟部智慧財產局員工消費合作社印製 1 0 3 C上方之絕緣膜1 0 4上設接觸孔2 0 4 ’藉由該 接觸孔2 04連接第1層配線1 1 3 a ’且於M〇S電晶 體Q 2之擴散層1 〇 3 d上方之絕緣膜1 0 4上設接觸孔 2 0 5 ’藉由該接觸孔2 0 5連接第1層配線1 1 3 b ° 上述位元之線BL，及第一層配線1 1 3 a ’ 1 1 3 b，係由下層側起依序沈積τ丨膜T iN膜 108、W膜109之構造。該等爲同一構造之配線層。 於記憶格1 0 〇 A ’在記憶格選擇用Μ 0 S電晶體 Q t之擴散層1 〇 3 b上方之多晶矽1 1 0 ’與構成位元 本紙張尺度適用中國國家標準（CNS)A4说格（210X297公釐）_ 21 A7 B7 經濟部智慧財產马SK工消費合作钍印製 五、發明説明（19 ) 線B L之一部之T i膜1 0 7之界面形成有矽化肽膜 106a 。又，在周邊電路區域100B之MOS電晶體 Q 1 &gt; Q 2 ........之擴散層l〇3c，l〇3d，與構 成位元線BL或第一層配線113a ，113b之一部分 之Ti膜107之界面形成有矽化鈦膜層106b。 上述實施形態，亦和第1實施形態相同，將T 1膜 107之膜厚上限値（nm) ’及矽化鈦膜l〇6a， 106b之膜厚上限値t (nm)，依TiN膜（導電性 膜）8之膜內部應力σ ( Μ P 3 )，設定爲上述式所界定 之値。依本實施形態，可得和第1及第2實施形態相同之 作用效果，可防止矽化鈦膜106a、 106b之剝離。 本發明不限於上述各實施例，申請專利範圍中之所有 變形例均包含於本發明。 〔圖面之簡單說明〕 圖1 本發明第1實施形態之半導體裝置之接觸構造（接觸 孔附近之構造）之斷面圖。 圖2 A〜2 D - 圖1之半導體裝置之製造方法之圖。 圖3 矽化物反應伴隨產生之矽化鈦膜之膜內部應力（實驗 (請先聞讀背面之注意事項再填寫本頁) 訂 本纸張尺度逍用中國國家棣準（(：阳）人4规格（210父297公釐&gt; _ 22 - 417177 A7 B7 五、發明説明（2〇 ) 之測定値）之圖。 (請先閱讀背面之注意事項再填寫本頁) 圖4 矽基板和矽化鈦膜之界面所產生界面應力，與導電性 膜之內部應力之間之關係圖。 圖5 不致產生剝離之矽化鈦膜之膜厚，與導電性膜（ T i膜）之膜內部應力之間之關係圖。 圖6 本發明第2實施形態之半導體裝置之接觸構造（接觸 孔附近之構造）之斷面圖。It is connected to the bit line BL 0 through the contact hole 2 0 1 to the bit line BL 0 to the peripheral circuit area 1 0 0 B 'to the MOS transistor Q 1 and the diffusion layer 1 0 3 C over the insulating film 1 A contact hole 202 is provided on the 04, and the bit line BL is connected through the contact hole 202. That is, a contact hole 2 0 3 is provided on the insulating film 1 0 4 on the other diffusion layer 1 0 3 d of the MOS transistor Q 1 'and the first-layer wiring 1 1 3a is connected through the contact hole 2 0 3 » Furthermore, 'printed on the diffusion layer of the M0S transistor Q2 4 printed by the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 0 3 C above the insulating film 1 0 4 is provided with a contact hole 2 0 4' 1 layer wiring 1 1 3 a ′ and a contact hole 2 0 5 on the insulating film 1 0 4 above the MOS transistor Q 2 〇 3 d is connected to the first through the contact hole 2 0 5 Layer wiring 1 1 3 b ° The above-mentioned bit line BL and the first layer wiring 1 1 3 a '1 1 3 b are structures in which τ 丨 film T iN film 108 and W film 109 are sequentially deposited from the lower layer side. . These are wiring layers of the same structure. In memory cell 1 0 〇A 'In the memory cell selection, use M 0 S transistor Q t diffusion layer 1 〇3 b polycrystalline silicon 1 1 0' and the constituent paper size is applicable to China National Standard (CNS) A4 said Grid (210X297 mm) _ 21 A7 B7 Printed by Intellectual Property of the Ministry of Economic Affairs, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, etc. V. Invention (19) A silicon film 106a is formed on the interface of the Ti film 107 on one of the lines BL. In addition, the MOS transistors Q 1 &gt; Q 2... In the peripheral circuit area 100B, and the diffusion layers 103c, 103d, and the bit lines BL or the first-layer wiring 113a, 113b A titanium silicide film layer 106b is formed at the interface of a part of the Ti film 107. The above embodiment is also the same as the first embodiment. The upper limit of the film thickness 厚 (nm) ′ of the T 1 film 107 and the upper limit of the film thickness 値 t (nm) of the titanium silicide films 106a and 106b are determined according to the TiN film (conductive The internal stress σ (MP 3) of the film is set to 値 defined by the above formula. According to this embodiment, the same effect as that of the first and second embodiments can be obtained, and peeling of the titanium silicide films 106a and 106b can be prevented. The present invention is not limited to the above embodiments, and all modifications in the scope of the patent application are included in the present invention. [Brief Description of Drawings] Fig. 1 is a sectional view of a contact structure (structure near a contact hole) of a semiconductor device according to a first embodiment of the present invention. 2A to 2D are diagrams of a method of manufacturing the semiconductor device of FIG. 1. Figure 3 The internal stress of the titanium silicide film accompanying the silicide reaction (experiment (please read the precautions on the back before filling out this page) (210 father 297 mm &gt; _ 22-417177 A7 B7 5. The description of the invention (2) measurement 値). (Please read the precautions on the back before filling this page) Figure 4 Silicon substrate and titanium silicide film The relationship between the interfacial stress generated by the interface and the internal stress of the conductive film. Figure 5 The relationship between the film thickness of the titanium silicide film that does not cause peeling and the internal stress of the conductive film (Ti film) Fig. 6 is a sectional view of a contact structure (structure near a contact hole) of a semiconductor device according to a second embodiment of the present invention.

圖7 A〜7 D 圖6之半導體裝置之製造方法之圖。 經濟部智慧財產局員工消費合作社印製 圖8 圖6之半導體裝置之變形例之圖。 圖9 本發明第3實施形態之半導體裝置之接觸構造（接觸 孔附近之構造）之斷面圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ 23 - 經濟部智慧財產笱員工消費合作社印製 A7 B7五、發明説明（21 ) 圖1 0A〜1 〇D 圖9之半導體裝置之製造方法之圖。 圖1 1 本發明第4實施形態之半導體裝置之接觸構造（接觸 孔附近之構造）之斷面圖。 圖1 2 A〜1 2 D 圖11之半導體裝置之製造方法之圖。 圖1 3 本發明第5實施形態之半導體裝置之斷面圖。 主要元件對照表 (請先閱讀背面之注意事項再瑱寫本頁) '裝 -訂 1 矽基板 2 元件分離區域 3 a 擴散層 3 b 擴散層 4 絕緣膜 5 接觸孔 6 矽化鈦膜 了 鈦膜 8 導電性膜 9 W膜 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） -24 · 經濟部智慧財產屙員工消費合作社印製 417177五、發明説明（22 ) 10 多晶矽 11 閘極氧化膜 12 閘極 13 電氣配線 1 0 0 A 記憶陣列 1 0 0 B 周邊電路區域 10 1 矽基板 102 場氧化膜 1 0 3 a 擴散層 103b 擴散層 103c 擴散層 103d 擴散層 10 4 絕緣膜 105 氧化矽膜 06a 矽化鈦膜 0 6b 矽化鈦膜 0 7 T i 膜 0 8 T 1 N 膜 0 9 W膜 10 多晶矽 11 閘極氧化膜 12a 閘極 12b 閘極 13a 第1層配線 A7 B7 裝---- (請先閱讀背面之注意事項再填寫本頁) -訂 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐） -25-7A to 7D are diagrams of a method of manufacturing the semiconductor device of FIG. 6. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 8 Figure 6 shows a modification of the semiconductor device. Fig. 9 is a sectional view of a contact structure (structure near a contact hole) of a semiconductor device according to a third embodiment of the present invention. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) _ 23-Printed by the Intellectual Property of the Ministry of Economy 笱 Employee Consumer Cooperative A7 B7 V. Description of the invention (21) Figure 1 0A ~ 1 〇D Figure 9 semiconductor Diagram of device manufacturing method. Fig. 11 is a sectional view of a contact structure (structure near a contact hole) of a semiconductor device according to a fourth embodiment of the present invention. FIGS. 1A to 12D are views of a method of manufacturing the semiconductor device of FIG. 11. FIG. Fig. 13 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. Comparison table of main components (please read the precautions on the back before writing this page) 'Binding-booking 1 Silicon substrate 2 Element separation area 3 a Diffusion layer 3 b Diffusion layer 4 Insulating film 5 Contact hole 6 Titanium silicide film 8 Conductive film 9 W film The size of this paper is applicable to China National Standard (CNS) A4 (210X297 mm) -24 · Printed by the Intellectual Property of the Ministry of Economic Affairs / Employee Consumer Cooperative 417177 V. Description of the invention (22) 10 Polycrystalline silicon 11 Gate Electrode oxide film 12 Gate electrode 13 Electrical wiring 1 0 0 A Memory array 1 0 0 B Peripheral circuit area 10 1 Silicon substrate 102 Field oxide film 1 0 3 a Diffusion layer 103b Diffusion layer 103c Diffusion layer 103d Diffusion layer 10 4 Insulation film 105 Silicon oxide film 06a titanium silicon film 0 6b titanium silicon film 0 7 T i film 0 8 T 1 N film 0 9 W film 10 polycrystalline silicon 11 gate oxide film 12a gate 12b gate 13a layer 1 wiring A7 B7 -(Please read the precautions on the back before filling out this page) -The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm) -25-

Claims (1)

六、申請專利範圍 附件1 a ./1¾ (請先閲讀背面之注意事項再填寫本頁) 第861 16486號專利申請案 中文申請專利範圍修正本 民國89年 q月修正 1 ‘ ~種半導體裝置，其矽層和導電性膜係藉由絕緣 膜積層而成，於上述絕緣膜設有接觸孔，於上述接觸孔內 部’上述矽層和上述導電性膜係藉由矽化鈦膜連接者，其 特徵在於：上述矽化鈦膜係具有依成膜後之上述導電性膜 之膜內部應力所界定之膜厚上限値。 2 .如申請專利範圍第1項之半導體裝置，其中上述 矽層包含有上述絕緣膜及導電性膜所積層之半導體裝置之 矽基板。 3 ·如申請專利範圍第2項之半導體裝置，其中於上 述接觸孔內部中之上述矽基板上方沈積有多晶矽，上述矽 化鈦膜係形成於上述多晶矽層與上述導電性膜之間。 經濟部智慧財產局員工消费合作社印製 4.如申請專利範圍第2或3項之半導體裝置，其中 於上述矽基板上設有多晶矽形成之閘極，上述接觸孔係設 於上述閘極上面。 5 .—種半導體裝置，其係具備在mo s電晶體上部 配置有資訊儲存用電容元件之推疊電容器構造之記憶格， 在用以連接上述MO S電晶體之擴散層及位元線之接觸孔 內部沈積多晶矽層之同時，與週邊電路之M〇 s電晶體之 擴散層連接之電氣配線及上述位元線係以同一W/T i N 本紙張尺度適用中國國家標準{ CNS ) A4規格（210X297公釐） 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) /T i之配線層構成，上述位元線及電氣配線係藉由矽化 鈦膜分別連接於上述多晶矽層及上述周邊電路之擴散層； 其特徵爲：上述矽化鈦膜係具有依成膜後之上述導電性膜 之膜內部應力所界定之膜厚上限値。 6 .如申請專利範圍第1、2、3或5項中任一項之 半導體裝置，其中上述矽化鈦膜之膜厚上限値t (nm) 係依成膜後之上述導電性膜之膜內部應力σ (MPa)， 設定爲 t = 150 — 0 . 03(7 所界定之値。 7·如申請專利範圍第1、 2、 3或5項中任一項乏 半導體裝置，其中上述接觸孔之孔徑上限爲0 . 4 。 經濟部智葸財產局員工消費合作社印製 8 . —種半導體裝置之製造方法，其係在矽基板上設 絕緣膜，於該絕緣膜開設接觸孔，至少在上述接觸孔內部 沈積觸接於上述矽基板之鈦膜，沈積觸接於上述鈦膜之導 電性膜後，對沈積有上述鈦膜及導電性膜之上述矽基板進 行熱處理，藉上述鈦膜與上述矽基板間之矽化物反應來形 成矽化鈦膜者，其特徵爲：上述鈦膜之膜厚上限値，係設 定爲對應於成膜後之上述導電性膜之膜內部應力所界定之 9.如申請專利範圍第8項之半導體裝置之製造方法 ，其中上述鈦膜之膜厚上限値y(nm)係依成膜後之上 本紙浪尺度適用中國囷家標準（CNS &gt; A4说格（210Χ297公釐） -2- 417 177 ?88 D8 六、申請專利範圍 述導電性膜之膜內部應力σ (MPa)，設定爲 y = 6〇-〇 012σ 所界定之値。 10.如申請專利範圍第8或9項之半導體裝置之製 造方法，其中上述接觸孔之孔徑上限爲〇.4 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家揉車（CNS ) A4现格（210X297公釐） -3 -6. Annex 1a of the scope of patent application (please read the notes on the back before filling out this page) No. 861 16486 Patent Application Chinese Application for Patent Scope Amendment 1 '~ 2018 semiconductor devices, The silicon layer and the conductive film are laminated by an insulating film. A contact hole is provided in the insulating film. Inside the contact hole, the silicon layer and the conductive film are connected by a titanium silicide film. The reason is that the above-mentioned titanium silicide film has an upper limit of the film thickness 依 defined by the internal stress of the film of the conductive film after film formation. 2. The semiconductor device according to item 1 of the patent application scope, wherein the silicon layer includes a silicon substrate of a semiconductor device laminated with the above-mentioned insulating film and conductive film. 3. The semiconductor device according to item 2 of the patent application, wherein polycrystalline silicon is deposited above the silicon substrate in the inside of the contact hole, and the titanium silicide film is formed between the polycrystalline silicon layer and the conductive film. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 4. For the semiconductor device in the scope of patent application No. 2 or 3, a gate formed of polycrystalline silicon is provided on the silicon substrate, and the contact hole is provided on the gate. 5. A semiconductor device comprising a memory cell with a push-up capacitor structure in which a capacitor element for information storage is arranged on a top of a MOS transistor, and is in contact with a diffusion layer and a bit line for connecting the above-mentioned MOS transistor. At the same time as the polycrystalline silicon layer is deposited inside the hole, the electrical wiring and the above bit lines connected to the diffusion layer of the Mos transistor of the peripheral circuit are the same W / T i N. This paper applies the Chinese national standard {CNS) A4 specification ( 210X297 mm) 6. Scope of patent application (please read the precautions on the back before filling this page) / T i wiring layer structure, the above bit lines and electrical wiring are connected to the above polycrystalline silicon layer and titanium silicon film respectively The diffusion layer of the peripheral circuit, wherein the titanium silicide film has a film thickness upper limit defined by the internal stress of the film of the conductive film after film formation. 6. The semiconductor device according to any one of claims 1, 2, 3, or 5, in which the upper limit of the film thickness 値 t (nm) of the titanium silicide film is based on the inside of the above-mentioned conductive film after film formation The stress σ (MPa) is set as t = 150 — 0.03 (7). 7. As in the case of a semiconductor device in any one of the scope of patent application 1, 2, 3 or 5, wherein the contact hole The upper limit of the aperture is 0.4. Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 8. A method for manufacturing a semiconductor device, which is provided with an insulating film on a silicon substrate, and a contact hole is opened in the insulating film, at least in the above contact Inside the hole, a titanium film that is in contact with the silicon substrate is deposited. After the conductive film that is in contact with the titanium film is deposited, the silicon substrate on which the titanium film and the conductive film are deposited is heat-treated. Those who react with silicide between substrates to form a titanium silicide film are characterized in that the upper limit of the film thickness of the titanium film 値 is set to correspond to the internal stress of the film of the conductive film after film formation. Semiconductor device under patent item 8 The manufacturing method, in which the upper limit of the film thickness 値 y (nm) of the above-mentioned titanium film is based on the Chinese paper standard (CNS &gt; A4 grid (210 × 297 mm) -2- 417 177? 88 D8 6. The internal stress σ (MPa) of the conductive film described in the scope of the patent application is set to 値 defined by y = 60-0012σ. 10. Manufacture of semiconductor devices such as the 8th or 9th in the scope of the patent application Method, in which the upper limit of the contact hole diameter is 0.4 (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to China National Rolling Mill (CNS) A4 (210X297 mm) -3-
TW086116486A 1996-11-08 1997-11-05 Semiconductor device with silicide contact structure and method for producing the same TW417177B (en)

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US9209175B2 (en) 2013-07-17 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices having epitaxy regions with reduced facets
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