TW416141B - Device and method for replacing damaged DRAM memory cells with SRAM and the DRAM module thereof - Google Patents

Abstract

The present invention relates to a device and method for replacing damaged DRAM memory cells with SRAM and the DRAM module thereof. The device for replacing damaged DRAM memory cells with SRAM and the DRAM module thereof comprises at least non-volatile memory and DRAM control logic circuit. The processes for replacing damaged DRAM memory cells with SRAM are: comparing the damaged address data with DRAM address data and using the location of SRAM to access the data and turning off the output enabling signal of DRAM if the result is matched. By using the device and method for replacing damaged DRAM memory cells with SRAM and DRAM module thereof, good memory address for accessing could be found in the computer that can ensure the computer system for normal operation.

Description

Continuing, the key members are requested to indicate whether the original substance will be changed after the amendment of this case. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 Β7 0 2 Repair iLOLEL ^ i 'Supplement No 20 25 30 40 50 60: 41 ° 6lf4f to 88104639 ≫) Brief description marked in the icon:

10 DRAM

DRAM control logic circuit System bus Built-in address memory SRAM matching bit Inverting amplifier Π0 Damaged address recorder 120 Built-in address memory 130 DRAM control logic circuit 140 SRAM 150 DRAM 160 System bus

Π0 Device for replacing damaged DRAM memory cell with SRAM 180 Block diagram of DRAM module for replacing damaged DRAM memory cell with SRAM The first embodiment, please refer to FIG. 2, which is shown as containing the address memory 3 0 (content addressable memory (CAM) and SRAM 40 connection diagram. First, the built-in address memory 30 is introduced. It is a special and infrequent memory. It is very useful for high-speed look-up tables. The embedded address memory 30 can accept a data word as an input (A (l ~ An). When the embedded address memory is stored in an array (----) ---- ---- 褒 -------- Order --------- line (Please read the precautions on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (21〇χ 297mm) Consumption Cooperation Printed by Employees of the Central Procurement Bureau of the Ministry of Economic Affairs 41 & 141〇c / 0 0 8 B7 V. Description of the Invention (I) The present invention relates to a device and method for memory replacement. In particular, it relates to a device and method for replacing damaged DRAM memory cells with SRAM and its DRAM module. The development of personal computers, the occupation of dynamic random access memory (DRAM) and its important part Copies, from the early units of kilobytes (Kbytes) to the units of millions of bytes (Mbytes). The continuous expansion of memory capacity, coupled with the continuous acceleration of the central processing unit (CPU), makes Modern computers have made great progress in data processing and computing capabilities. Especially the size of DRAM is an indicator of CPU processing capacity. DRAM With a large capacity, the computer can process more data and open more programs. A conventional DRAM module, as shown in Figure 1, its access method is: When used as a read operation, the DRAM controls The logic circuit 20 receives a bit of address data from the system bus 25, decodes the address data, and corresponds to the position of the address data in the DRAM 10. When the DRAM control signal is a read command, the DRAM 1 0 sets this position The data in it is placed in the system bus 25 via the DRAM control logic circuit 20 to complete the reading operation. As a write operation, the DRAM control logic circuit 20 receives a bit of data from the system bus 25 and sets the bit The address data is decoded and corresponds to the location of this address data in the DRAM 10. When the DRAM control signal is a write command, the DRAM 10 places the data in the system bus 25 through the DRAM control logic circuit 20 to the address data 3 (Please read the notes on the back before filling out this page) " ° This paper size is applicable to China National Standard (CNS) A4 specifications (210X297) 嫠 4 4 4 〇3 Industrial and consumer cooperatives繁 B7 V. Description of the invention (7), complete the writing operation. However, once the memory cell in the DRAM module is damaged, data access errors in the DRAM will occur, or incorrect data will be accessed. Therefore, the entire module must be discarded and a new DRAM module must be replaced to enable the computer to operate normally. Or a semiconductor factory has some damaged memory cells in the DRAM process. These damaged DRAMs cannot be manufactured because of their defects. The DRAM module must be discarded, which is not very economical. From the above discussion, it can be known that the conventional DRAM module cannot be effectively used when some damaged memory cells appear, and it can only be discarded. This is really a pity. The invention proposes a device and method for replacing a damaged DRAM memory cell with SRAM and a DRAM module thereof. The damaged address data is compared with the DRAM address data. If the data matches, the SRAM is used to access the data. , And turn off the output enable signal of DRAM. In order to achieve the invention, a device and method for replacing a damaged DRAM memory cell with SRAM and a DRAM module thereof are proposed, by comparing the damaged address data with the DRAM address data. When the data matches, the SRAM location is used to access the data, and the output enable signal of the DRAM is turned off. The device that replaces the damaged DRAM memory cell with SRAM and its DRAM module include at least non-volatile memory and DRAM control logic circuits. The non-volatile memory is used as the initial program guide. The damaged address data stored in advance is transmitted through the power-on signal 4 (Please read the precautions on the back before filling this page). Applicable to Chinese National Standards (CNS > A4 specifications (2 丨 0X297 mm), Employee Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs, Yinfan 416141 4440twf.doc / 00B V. Description of invention (Λ) action, send the damaged address data Including address memory. Including address memory, connected to non-volatile memory, DRAM and SRAM, is to write the damaged address data, and receive DRAM address data, and to put the damaged address data Compare with DRAM address data and send specific matching signal. DRAM control logic circuit is connected to the system bus, contains address memory, DRAM and SRAM, and is used to receive address data, DRAM control signals and data signals ， According to DRAM control signal, do data signal access on SRAM or according to DRAM address data and DRAM control signal, do data signal access on DRAM or according to DRAM control signal and DRA M address data, the data signal is written into the embedded address memory. The method of replacing damaged DRAM memory cells with SRAM in the present invention is to compare a plurality of damaged address data with DRAM address data Yes, specific matching data is sent to enable a specific position in the SRAM and disable the output enable signal in the DRAM. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are enumerated below. The following is a detailed description in conjunction with the attached diagram t: The diagram is briefly explained: Fig. 1 shows the conventional DRAM module. Fig. 2 shows the connection diagram of the internal address memory and SRAM. Figure 3 is a block diagram of a DRAM module using SRAM to replace a damaged DRAM cell. 5 * (Please read the precautions on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS ) A4 specification (2 丨 0X297mm) Continue to ask the clarified members to indicate whether the original substance will be changed after the amendment of this case. Printed by the Consumers 'Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 Β7 0 2 Repair iLOLEL ^ i' Supplement No 20 25 30 40 50 60: 41 ° 6lf4f to 88104 639 V. Description of the invention (>) Brief description marked in the picture:

10 DRAM

DRAM control logic circuit System bus Built-in address memory SRAM matching bit Inverting amplifier Π0 Damaged address recorder 120 Built-in address memory 130 DRAM control logic circuit 140 SRAM 150 DRAM 160 System bus

Π0 Device for replacing damaged DRAM memory cell with SRAM 180 Block diagram of DRAM module for replacing damaged DRAM memory cell with SRAM The first embodiment, please refer to FIG. 2, which is shown as containing the address memory 3 0 (content addressable memory (CAM) and SRAM 40 connection diagram. First, the built-in address memory 30 is introduced. It is a special and infrequent memory. It is very useful for high-speed look-up tables. The embedded address memory 30 can accept a data word as an input (A (l ~ An). When the embedded address memory is stored in an array (----) ---- ---- 褒 -------- Order --------- line (Please read the precautions on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (21〇χ 297 mm)

416141 444〇twf.doc / 〇〇S A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Shellfish Consumer Cooperative. V. When the information and the word group of the invention description (^) are the same, a specific match signal will be generated. The data and data blocks that represent the location are the same. The internal address memory 30 can also be accessed as a general SRAM, but its structure is more complicated than that of SRAM. The circuit structure of the SRAM 40 is to read the data in the memory cell from the bit line (DfD ,,) or select the bit line through the selection of the word line (word line (SRAM WL0 ~ SRAM WLn)). Data is written into the memory cell. In this embodiment, the embedded address memory 30 can write damaged address data into the embedded memory 30 during a write cycle. The operation at this time is the same as that of ordinary SRAM. Select one of the word lines (CAM WL0 ~ CAM WLn) and place the damaged address data on the bit line (A ^ A ,,) and write it into the memory cell. During non-comparison periods, all specific matching signals are precharged to high voltage. When in the comparison cycle, all the word lines will be closed. At this time, the DRAM address data used for comparison is placed on the bit line (A, ~ An). If they match exactly, one specific matching signal will be ground, and the other specific matching signals will maintain high voltage. When this specific matching signal goes to ground, it passes through an inverting amplifier 60 and becomes one of the SRAM word lines (SRAM WL0 ~ SRAM WLn). Then, bit lines (DG ~ Dn) can be used in the word line. Access to the specified SRAM cell. In addition, we also provide a parity bit of 50 in the memory cell containing the billionth body. The above circuit can be better modified. When the data of the memory cell is damaged address data A digital letter 7 is placed with a matching bit (please read the precautions on the back before filling this page) Order -v This paper size is applicable to the China National Standard (CNS > A4 size (210X297 mm)) Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative 416141 A7 4440twf.d〇c / 0C8 B7 V. Description of invention (() No. "ι", when the data of the memory cell is meaningless, the allocation bit places a digital signal "〇". The bit line corresponding to the matching bit (the digital signal "1" is placed on the AJ. When the damaged address data matches the DRAM address data and the matching bit is a digital signal "1", the specific matching signal will be Action. It is used to prevent errors caused when meaningless data and DRAM address data are the same. Please refer to FIG. 3, which shows a preferred embodiment of the present invention. A SRAM is used to replace a damaged DRAM memory cell. Block 170 and its DRAM module 1 80. When the electricity When turned on, a power-up pulse wave is generated, and this pulse wave will define a pulse wave period, so that the damaged address data stored in the non-volatile memory 110 in advance can be loaded into the internal address memory 120 The damaged address also contains a matching bit. Then the DRAM control logic circuit 130 receives the DRAM address data from the system bus 160 and transmits the DRAM address data to the internal address memory 120 to do Comparison. When one of the DRAM address data and the damaged address data completely matches, a specific matching signal will enable a specific position of the SRAM, and this specific matching signal will disable the DRAM output enable signal. Then DRAM control Logic circuit 130 receives DRAM control signals and data signals from system bus 160 and sends these signals. SRAM 140 can access data signals after receiving DRAM control signals. DRAM 150 is disabled because the DRAM output enable signal is disabled. Therefore, there is no way to access the data signals. When the DRAM address data and the damaged address data do not match, the specific matching signal will not enable the SRAM. DRAM 111¾¾ Ken 8 (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 416141 A7 4 4 4 0 twf. Doc / 〇 〇 8 B7 5. The invention description (public) number. Then the DRAM control logic circuit 130 receives the DRAM control signals and data signals from the system bus 160 and sends out these signals. The DRAM 150 according to the DRAM address data , And the received DRAM control signal can be used for data signal access. SRAM 150 is not capable of accessing data signals because certain matching signals are not enabled. In the present invention, the embedded memory 120 is used to improve the efficiency between the non-volatile memory Π0 and the system, so that the system can access the memory faster. If the speed of the non-volatile memory Π0 and the system can match each other The internal memory 120 can also be removed, and the function of address comparison can be implemented by the DRAM control logic circuit 130. An advantage of the present invention is to provide a device and method for replacing a damaged DRAM memory cell with SRAM, and a DRAM module thereof. The damaged address can be stored in a non-volatile memory in advance, and the memory can be damaged by including a memory bank. The address data is compared with the DRAM address data. If the data matches, the SRAM location is used to access the data, and the output enable signal of the DRAM is turned off. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the appended patent application. Order. &Quot;. (Please read the notes on the back before filling out this page) 9 This paper size applies to China National Standard (CNS) A4 specifications (21〇 ×; 297 mm)

Claims (1)

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Group, coupled to a system bus and activated with a power-on signal, including: a damaged address recorder for storing a plurality of damaged address data in advance, and sending the damaged bits through the power-on signal Address data; an internal address memory, coupled to the damaged address recorder, used to write the damaged address data, and receive a DRAM address data, and the damaged address data and the DRAM The address data is compared to send a specific matching signal; an SRAM is coupled to the embedded address memory to receive the specific matching signal, and according to the activation of the specific matching signal and a DRA M control signal, To access a data signal; a DRAM coupled to the embedded address memory to receive the specific matching signal and the DRAM address data ', and according to the closing of the specific matching signal, the DRA M address data and the DRAM control signal to access the data signal; and a DRAM control logic circuit coupled to the system bus, the embedded address memory, the DRAM and the SRAM, and receives the DRAM address data, the DRAM control signal and the data signal are used for accessing the data signal on the SRAM and accessing the data signal on the DRAM and using the data signal as the embedded address memory The body writes' three choices' 2. The DRAM module described in item 1 of the scope of patent application 'wherein the damaged address recorder is a flash memory. 1-^ ----------- ^ ------ ΐτ ------ line (please read the precautions on the back before filling in this page) The paper scale quickly uses the Chinese country 梂Rate (CNS) Α4 specifications (210X 297 mm) & ??? Group, coupled to a system bus and activated with a power-on signal, including: a damaged address recorder for storing a plurality of damaged address data in advance, and sending the damaged bits through the power-on signal Address data; an internal address memory, coupled to the damaged address recorder, used to write the damaged address data, and receive a DRAM address data, and the damaged address data and the DRAM The address data is compared to send a specific matching signal; an SRAM is coupled to the embedded address memory to receive the specific matching signal, and according to the activation of the specific matching signal and a DRA M control signal, To access a data signal; a DRAM coupled to the embedded address memory to receive the specific matching signal and the DRAM address data ', and according to the closing of the specific matching signal, the DRA M address data and the DRAM control signal to access the data signal; and a DRAM control logic circuit coupled to the system bus, the embedded address memory, the DRAM and the SRAM, and receives the DRAM address data, the DRAM control signal and the data signal are used for accessing the data signal on the SRAM and accessing the data signal on the DRAM and using the data signal as the embedded address memory The body writes' three choices' 2. The DRAM module described in item 1 of the scope of patent application 'wherein the damaged address recorder is a flash memory. 1-^ ----------- ^ ------ ΐτ ------ line (please read the precautions on the back before filling in this page) The paper scale quickly uses the Chinese country 梂(CNS) Α4 specification (210X 297 mm) mm ABCD Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for patent scope 3. The DRAM module described in item 1 of the scope of patent application, where the damaged address The recorder is an electrically erasable programmable read-only memory. 4. The DRAM module described in item 1 of the scope of patent application, wherein the damaged address recorder is an electrically programmable read-only memory. 5. The DRAM module described in item I of the patent application scope, wherein the damaged address recorder is a programmable logic array. 6. The DRAM module described in item 1 of the scope of patent application, wherein the damaged address recorder is a programmable fuse. 7. The DRAM module described in item 1 of the scope of patent application, wherein The damaged address data in the embedded address memory includes writing the damaged address data into the embedded address memory by a software loading method. 8. According to the DRAM module described in item 1 of the scope of patent application, when the DRAM address data is the same as one of the damaged address data, the specific matching signal will be activated, that is, the SRAM-specific Position and disable one of the DRAMs to output an enable signal. 9. According to the DRAM module described in item 1 of the scope of patent application, when the comparison result between the DRAM address data and the damaged address data is different, the specific matching signal will be turned off, that is, the SRAM is not Is enabled and the DRAM is operating normally. 10. As for the DRAM module described in item 1 of the scope of the patent application, the damaged address data provides a matching bit for determining whether the damaged address data is one of valid data and invalid data. --------- ¾ ------ '玎 ------. Ii (Please read the notes on the back before filling out this page) The paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Liquor 41614 ^ 0 0 2 ιι D8 VI. Patent application scope π. According to the DRAM module described in item 10 of the patent application scope, when the damaged address When the data is invalid, the matching bit will turn off the specific matching signal. 12. — A method of replacing damaged DRAM memory cells with SRAM, comparing a plurality of damaged address data with a DRAM address data and sending a specific matching data to enable a specific location of an SRAM and disable a DRAM One outputs an enable signal. 13. According to the method described in item 12 of the scope of patent application, when the comparison result between the damaged address data and the DRAM address data is different, then the specific matching signal is turned off, that is, the SRAM is not enabled. And the DRAM is operating normally. 14. A device for replacing a damaged DRAM memory cell with SRAM, coupled to a SRAM, a DRAM, and a system bus, and activated by a power-on signal, including: a damaged address recorder for pre-storage A plurality of damaged address data are sent out through the power-on signal: an internal address memory, coupled to the damaged address recorder, the DRAM and the SRAM, for writing into the Some damaged address data, and receive a DRAM address data, compare the damaged address data with the DRAM address data, and send a specific matching signal; and a DRAM control logic circuit coupled to the system bus Row, the embedded address memory, the DRAM and the SRAM, receiving the DRAM address data, the DRAM control signal and the data signal for accessing the data signal on the SRAM and the data signal The DRAM-^ --------- install ------, order ------ line (please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210X297 mm) ABCD ffeiix002 6 1. Access in the scope of patent application and write the data signal into the embedded address memory, choose one of the three ...! 5. The device described in item I4 of the scope of patent application, wherein the damaged address Record ϊίί1 彳 糸 one flash memory. 16. The device according to item 14 of the scope of patent application, wherein the damaged address recorder is an electrically erasable programmable read-only memory. 17 · The device as described in item I 4 of the scope of patent application, wherein the damaged address recorder is an electrically programmable read-only memory. 18. The device according to item M of the patent application scope, wherein the damaged address recorder is a programmable logic array. 19. The device according to item 14 of the scope of patent application, wherein the damaged address recorder is a programmable fuse. 20. The device according to item 14 of the scope of patent application, wherein the damaged address data in the embedded address memory includes writing the damaged address data in a software loading manner. This contains address memory. 21. According to the device described in claim 14 of the scope of patent application, when the DRAM address data is the same as one of the damaged address data, the specific matching signal will be activated, that is, the SRAM-a specific location, And one of the DRAMs is disabled from outputting an enable signal. 22 · As for the device described in item 14 of the scope of patent application, when the comparison result between the DRAM address data and the damaged address data is different, the specific matching signal will be turned off, that is, the SRAM is not Enable and the DRAM is operating normally. The size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public holiday) — ^ -------.—— installation ------ ir ------, ii (Please read it first Note on the back then fill in this I) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs f 1/0 0 2 A8 B8 CS D8 VI. Application scope of patent 23. For the device described in item 14 of the scope of patent application, these Defective address data provision-A sort bit is used to determine whether the damaged address data is one of valid data and invalid data. 24. As for the device described in item 23 of the scope of patent application, when the damaged address data is invalid, the matching bit will turn off the specific matching signal. (Please read the notes on the back before filling this page): D Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (2 丨 0X 297 mm)