經濟部智慧財產局員工消費合作社印製 416119 A7 --------B7________ 五、發明說明（i ) 本發明是有關於一種半導體製程，且特別是有關於一種 具雜合結構之低介電常數内金屬介電層製程。 在積體電路的應用上，導體、半導體及絕緣層等材料已 被廣泛地使用，其中薄膜沉積技術例如化學氣相沉積法等製 程，主要即是將上述各材料分層沉積於待製晶圓表面，以形 成半導體元件如電晶體等。 此外，在深次微米製程中，積體電路積集度增加，製作 電晶體之基底面積則需不斷減少以提高密度，因此目前廣泛 採用立體架構’如多層金屬内連線的方式來連接各元件，其 中用來隔離各金屬層之介電材料稱之為内金屬介電層 (IMD)，傳統製程一般為使用旋塗式玻璃或氧化層。 然而，此内金屬介電層是位在兩金屬層前，因此介電層 的介電係數(k值）之高低便與rc延遲時間有關。故尋找低介 電係數之介電材料以減少RC延遲時間，乃是深次微求製程 中之重要考量。 低”電係數材料所構成的介電層，在最近的内金屬介電 層（IMD)的應用上變得非常重要。目前，半導體業界常使用 的低介電常數之材料例如有旋塗式場氧化物（Spin_〇n F〇x) 以及含氟矽玻璃（FSG)。 第1A圖〜1C圖顯示習知一種使用旋塗式場氧化物作為 低介電常數之介電層之剖面製程。 首先’ s奢先參照弟1A圖’提供一含半導體元件之半導 體基底10，然後再形成具特定圖案之金屬内連線於半導 體基底10上。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ^ Γ— M.--------tx---------族 .(請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 416119 a? _____B7 五、發明說明（2) 其次，請參照第1B圖以及第iC圖，形成一旋塗式場 氧化層14於上述製程所形成之基底ι〇以及金屬内連線12 表面。然後，再利用快速熱退火製程（RTp)或加熱板(H〇t plate) 加熱，使旋塗式場氧化層固化（curing)，並且轉變成孔狀的超 低介電常數之介電層14,。 上述的旋塗式場氧化層14雖具有較佳的溝填特性，且 最終具超低介電常數的介電層14，之平坦度也極佳，然而經 過快速熱退火或加熱板加熱處理後所形成的孔狀結構使得 介電層14’無法忍受環境中的濕氣，且在後續製程中常用的 熱循環處理以及與其它化合物接觸時並不穩定，造成其薄膜 的應力不穩定，且與其它薄膜間的附著力也不佳。 第2A〜2B圖顯示習知一種使用化學氣相沉積法形成低 介電常數之介電層的剖面製程。 首先，請參照第2A圖，提供一如第1A圖所示的半導 體基底ίο,其上並形成有具特定圖案之金屬内連線12〇 接著，再以化學氣相沉積法形成一低介電常數材料層 16(例如氟摻雜的氧化矽；FSG)於上述製程所形成之基底 以及金屬内連線12之表面，作為金屬内連線的内金屬介電 層。 上述製程所形成的低介電常數材料層16可在較低的溫 度形成，且其具有較密實的結構，且其在半導體後續製程中 的熱循環或與化合物接觸時具有較佳的穩定度。然而，其介 電常數高於懸塗式材料所構成的介電層，且其在高密度半導 體中的溝填特性也劣於懸塗式材料所構成的介電層，易形成 4 本紙張尺度適用中關家標準（CNS)A4規格⑵Qx297公餐） (請先閱讀背面之注項再填寫本頁) 裝-------訂----I----線 A7 416119 B7 五、發明說明（4 ) 如第2B圖所示的孔洞（via) 1 8，且在高方位比率(aSpect rati〇) 時，其溝填不佳的情況將更明顯。 有鑑於此’本發明揭示一種具雜合結構之低介電常數内 金屬介電層製程，其步驟包括：提供一包含有元件之半導體 基底；形成具特定圖案之金屬内連線於該半導體基底上；形 成一第一介電層適順性地覆蓋該半導體基底以及該金屬内 連線；形成一第二介電層於該金屬内連線間的區域，並且將 該些區域填滿；以及形成一第三介電層於該上述步驟所形成 的結構表面’經平坦化後便完成一由該第一介電層、該第二 介電層以及該第三介電層所形成的具雜合結構之低介電常 數内金屬介電層。如上所述之製程中，第一介電層是厚度約 100Α〜2000Α之低介電常數化學氣相沉積的氧化物層或高密 度電漿化學氣相沉積的含氟矽玻璃所構成，其k值約為 3.5〜4.0;第二介電層是由厚度約2κ〜12KA之低介電常數旋 塗式玻璃層所構成，其k值約為2.0〜2.5 ;第三介電層是由厚 度約5K〜20KA之低介電常數化學氣相沉積的氡化物層或高 密度電漿化學氣相沉積的含氟矽玻璃所構成，其k值約為 3.5〜4_0。此外，第二介電層形成後，更包括一熱處理步驟， 例如快速熱退火或放在加熱板上加熱，使其固化且内部結構 形成孔狀的低介電常數材料。 本發明更揭示另一種具雜合結構之低介電常數内金屬 介電層製程，其步驟包括：提供一包含有元件之半導體基 底，形成具特定圖案之金屬内連線於該半導體基底上；利用 化學氣相沉積法形成一第一介電層適順性地覆蓋該半導體 5 &97公釐） ^ ^ 11 Μ--------訂 ----I---旋 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張财關¥鮮（CNS)A4規格 經濟部智慧財產局員工消費合作社印製 416113 a： —_一 ___B7____ 五、發明說明（5 ) 基底以及該金屬内連線；塗佈一第二介電層該半導體基底 上’並且將該些區域填滿；對該半導體基底施一熱處理；形 成一第三介電層於該上述步驟所形成的結構表面，經平坦化 後便完成一由該第一介電層、該第二介電層以及該第三介電 層所形成的具雜合結構之低介電常數内金屬介電層。如上所 述之製程中，第一介電層是厚度約100〜2000A之低介電常數 化學氣相沉積的氧化物層或高密度電漿化學氣相沉積的含 氟矽玻璃所構成，其k值約為3·5〜4.0 ;第二介電層是由厚度 約2Κ〜12ΚΑ之低介電常數旋塗式玻璃層所構成，其k值約 為2.0〜2.5 ;第三介電層是由厚度約5K〜20KA之低介電常數 化學氣相沉積的氧化物層或高密度電漿化學氣相沉積的含 氣發玻璃所構成’其k值約為3.5〜4_0。此外，第二介電詹形 成後的熱處理步驟是利用例如快速熱退火或放在加熱板上 加熱，使得塗佈於基底上的第二介電層固化，且可使其内部 結構形成孔狀的低介電常數材料。 為了使本發明之優點以及特徵更明顯易懂，玆將配合較 佳實施例以及相關圖式，詳細說明如下。 圖式之簡單說明： 第1A圖〜1C圖顯示習知一種使用旋塗式場氧化物作為 低介電常數材料層之剖面製程。 第2A〜2B圖顯示習知一種使用化學氣相沉積法形成低 介電常數值的介電層之剖面製程。 第3A〜3D圖顯示根據本發明之一實施例的具雜合結構 之低介電常數值的内金屬介電層之刮面製程。 6 本紙張又㈣用中國國家標準（CNS)A4規ίΓ(210 X297公f ) ----- I--^---- ---- 訂--------線 <請先閱讀背面之注意事項再填寫本頁> A7 416119 B7_ 五、發明說明（6 ) 實施例： 首先，請先參照第3A圖，提供一包含有半導體元件之 半導體基底30，然後再形成具特定圖案之金屬内連線32於 基底30上。 其次，請參照第3B圖，利用化學氣相沉積法形成一厚 度約100〜2000A之介電層34適順性地覆蓋半導體基底30以 及金屬内連線32表面。其中，介電層34例如可為利用電漿 加強式化學氣相沉積法（PECVD)或高密度電漿化學氣相沉 積法(HDP-CVD)所形成的低介電常數材料，例如化學氣相沉 積的氟摻雜矽玻璃（PE-FSG)或高密度電漿化學氣相沉積的 氟摻雜矽玻璃出〇?48〇)，其尺值約為3.5〜4.0。 然後，請參照第3C圖，形成一厚度約2K〜12K之塗佈式低 介電常數材料層所構成之介電材料於第3B圖所示的結構表 面（未顯示）’使其將金屬内連線32間的溝渠填滿，然後再以 快速熱退火或加熱板加熱處理，使塗佈的低介電常數材料層 固化、平坦化，並且使其内部結構轉變成孔狀結構，而成為 一溝填於金屬内連線32間的超低介電常數材料層36，其K 值約為2.0〜2.5。 最後，請參照第3D圖，再利用化學氣相沉積法形成一 厚度約5K〜20KA之介電層38於介電層34以及介電層36 上，其中介電層38例如可為低介電常數的矽玻璃所構成。 平坦化後，便可完成一由介電層34、介電層36以及介電層 38所構成之低介電常數的内金屬介電層雜合(hybride)結構 40。其中介電層38與介電層32之材料可為類似的矽玻璃所 7 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐） ----------I I---------J 訂---I-----線 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 ^- 丘、發明説明（7 ) 構成，例如其可為利用電漿加強式化學氣相沉積法(PECVD) 或高密度電漿化學氣相沉積法（HDP-CVD)所形成的梦玻 璃，例如化學氣相沉積的氟摻雜矽玻璃（PE-FSG)或高密度電 漿化學氣相沉積的氟摻雜矽玻璃（HDP_FSG)’其K值約為 3>5~4.〇。至此，根據本發明之製程所形成的低介電常數材料 層雜合結構4〇,其兼具低介電常數塗佈的場氧化介電材料以 及低介電常數之化學氣相沉積材料之優點，可具有低介電常 數，且對後續的熱循環或與其它化學藥品接觸時具有較高的 穩定度，且應用於高密度積體電路佈局時，也不會在溝填金 屬内連線間的溝渠時發生孔洞。 綜上所述，本發明之具雜合結構之低介電常數之内金屬 介電層製程可提供一低介電常數材料層，而又彳改善習之製 程之缺點，可用於積集度越來越高的VLSI以及ULSI製程 上。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。 (諳先閱讀背面之注意事項再填寫本頁) 裝·-------訂·！-線 經濟部智慧財產局員工消費合作社印製 8 — 本紙張尺度適用中囤國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 416119 A7 -------- B7________ V. Description of the Invention (i) The present invention relates to a semiconductor process, and in particular to a low-medium with a hybrid structure Process of metal dielectric layer with constant electric constant. In the application of integrated circuits, materials such as conductors, semiconductors, and insulation layers have been widely used. Among them, thin film deposition techniques such as chemical vapor deposition processes are mainly used to deposit the above materials in layers on the wafer to be produced. Surface to form semiconductor elements such as transistors. In addition, in the deep sub-micron process, the integration degree of integrated circuits is increased, and the substrate area for making transistors needs to be continuously reduced to improve density. Therefore, three-dimensional structures such as multilayer metal interconnects are widely used to connect components. The dielectric material used to isolate each metal layer is called an inner metal dielectric layer (IMD), and the traditional process generally uses a spin-on glass or an oxide layer. However, the metal dielectric layer is located in front of the two metal layers, so the dielectric constant (k value) of the dielectric layer is related to the rc delay time. Therefore, finding a low-k dielectric material to reduce the RC delay time is an important consideration in the deep microfining process. Dielectric layers made of “low” dielectric materials have become very important in recent applications of internal metal dielectric layers (IMD). Currently, materials with low dielectric constants commonly used in the semiconductor industry, such as spin-on field oxidation (Spin_〇n F〇x) and fluorine-containing silicon glass (FSG). Figures 1A to 1C show a conventional cross-sectional process using a spin-on field oxide as a low dielectric constant dielectric layer. First, ' First, provide a semiconductor substrate 10 containing semiconductor elements with reference to Figure 1A, and then form a metal interconnect with a specific pattern on the semiconductor substrate 10. 3 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ^ Γ— M .-------- tx --------- clan. (Please read the precautions on the back before filling out this page) Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Cooperative printed 416119 a? _____B7 V. Description of the invention (2) Secondly, please refer to Figure 1B and Figure iC to form a spin-on field oxide layer 14 on the substrate and the surface of the metal interconnect 12 formed by the above process. . Then, use the rapid thermal annealing process (RTp) or heating plate (H t plate) is heated to cure the spin-coated field oxide layer and transform it into a porous ultra-low dielectric constant dielectric layer 14. Although the above-mentioned spin-coated field oxide layer 14 has better trench filling characteristics The dielectric layer 14 having an ultra-low dielectric constant is excellent in flatness. However, the porous structure formed after rapid thermal annealing or heat treatment on the heating plate makes the dielectric layer 14 ′ intolerable in the environment. Moisture, and the thermal cycle treatment commonly used in subsequent processes and contact with other compounds are not stable, causing the stress of the film to be unstable, and the adhesion to other films is not good. Figures 2A to 2B show the conventional A cross-sectional process for forming a low dielectric constant dielectric layer using a chemical vapor deposition method. First, referring to FIG. 2A, a semiconductor substrate as shown in FIG. 1A is provided, and a pattern having a specific pattern is formed thereon. Metal interconnect 12. Next, a low dielectric constant material layer 16 (such as fluorine-doped silicon oxide; FSG) is formed by chemical vapor deposition on the substrate formed by the above process and the surface of metal interconnect 12 As The inner metal dielectric layer of the metal interconnect. The low dielectric constant material layer 16 formed by the above process can be formed at a lower temperature, and it has a denser structure, and its thermal cycling or It has better stability when in contact with compounds. However, its dielectric constant is higher than that of a dielectric layer made of a suspension coating material, and its trench filling characteristics in high-density semiconductors are also inferior to those of a suspension coating material. Dielectric layer, easy to form 4 This paper size is applicable to Zhongguanjia Standard (CNS) A4 specification ⑵Qx297 meal) (Please read the note on the back before filling this page) -I ---- line A7 416119 B7 V. Description of the invention (4) The hole (via) 1 8 shown in Figure 2B, and its groove filling is poor at a high aspect ratio (aSpect rati〇) Will be more obvious. In view of this, the present invention discloses a process for manufacturing a metal dielectric layer with a low dielectric constant with a hybrid structure. The steps include: providing a semiconductor substrate including a component; and forming a metal interconnect with a specific pattern on the semiconductor substrate. Forming a first dielectric layer to comfortably cover the semiconductor substrate and the metal interconnects; forming a second dielectric layer between the metal interconnects and filling the regions; and Forming a third dielectric layer on the structure surface formed by the above steps, after planarizing, a heterogeneous layer formed by the first dielectric layer, the second dielectric layer, and the third dielectric layer is completed. Low dielectric constant metal dielectric layer of the composite structure. In the above-mentioned process, the first dielectric layer is composed of a low dielectric constant chemical vapor deposition oxide layer or a high-density plasma chemical vapor deposition fluorine-containing silicon glass with a thickness of about 100 Å to 2000 Å. The value is about 3.5 ~ 4.0; the second dielectric layer is composed of a low dielectric constant spin-on glass layer with a thickness of about 2κ ~ 12KA, and its k value is about 2.0 ~ 2.5; the third dielectric layer is about 5K ~ 20KA is composed of a low dielectric constant chemical vapor deposited halide layer or a high density plasma chemical vapor deposited fluorine-containing silicon glass, and its k value is about 3.5 ~ 4_0. In addition, after the second dielectric layer is formed, it further includes a heat treatment step, such as rapid thermal annealing or heating on a hot plate to cure it and form a low-dielectric-constant material with a hole-like internal structure. The present invention further discloses another process for manufacturing a low dielectric constant inner metal dielectric layer with a hybrid structure. The steps include: providing a semiconductor substrate including a component, and forming a metal interconnect with a specific pattern on the semiconductor substrate; A chemical vapor deposition method is used to form a first dielectric layer to cover the semiconductor compliantly (5 & 97 mm) ^ ^ 11 M -------- Order ---- I --- Spin ( Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed on this paper. __B7____ 5. Description of the invention (5) The substrate and the metal interconnect; coating a second dielectric layer on the semiconductor substrate and filling the areas; applying a heat treatment to the semiconductor substrate; forming a third dielectric After the electrical layer is planarized on the structure surface formed by the above steps, a low dielectric having a hybrid structure formed by the first dielectric layer, the second dielectric layer, and the third dielectric layer is completed after planarization. A metal dielectric layer within an electrical constant. In the process described above, the first dielectric layer is composed of a low dielectric constant chemical vapor deposited oxide layer having a thickness of about 100 to 2000 A or a high density plasma chemical vapor deposited fluorine-containing silicon glass. The value is about 3.5 ~ 4.0; the second dielectric layer is composed of a low dielectric constant spin-on glass layer with a thickness of about 2K ~ 12KA, and its k value is about 2.0 ~ 2.5; the third dielectric layer is made of An oxide layer with a low dielectric constant chemical vapor deposition or a high density plasma chemical vapor deposited gas-containing glass with a thickness of about 5K to 20KA 'has a k value of about 3.5 to 4_0. In addition, the heat treatment step after the formation of the second dielectric is to use, for example, rapid thermal annealing or heating on a hot plate, so that the second dielectric layer coated on the substrate is cured, and its internal structure can be formed into a pore shape. Low dielectric constant material. In order to make the advantages and features of the present invention more comprehensible, the preferred embodiments and related drawings are described in detail below. Brief description of the drawings: Figures 1A to 1C show a conventional cross-sectional process using a spin-on field oxide as a low dielectric constant material layer. Figures 2A to 2B show a conventional cross-sectional process of forming a dielectric layer with a low dielectric constant value using a chemical vapor deposition method. Figures 3A to 3D show a process of scraping the inner metal dielectric layer with a low dielectric constant value of a hybrid structure according to an embodiment of the present invention. 6 This paper uses the Chinese National Standard (CNS) A4 Regulation (210 X297 male f) ----- I-^ ---- ---- Order -------- line < Please read the notes on the back before filling in this page> A7 416119 B7_ V. Description of the Invention (6) Example: First, please refer to FIG. 3A to provide a semiconductor substrate 30 containing a semiconductor element, and then form a semiconductor substrate 30 A specific pattern of metal interconnects 32 are on the substrate 30. Next, referring to FIG. 3B, a dielectric layer 34 having a thickness of about 100 to 2000 A is formed by chemical vapor deposition to cover the surface of the semiconductor substrate 30 and the metal interconnect 32 in a conformable manner. The dielectric layer 34 may be, for example, a low dielectric constant material formed by using plasma enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDP-CVD), such as a chemical vapor phase. The deposited fluorine-doped silica glass (PE-FSG) or high-density plasma chemical vapor deposition of fluorine-doped silica glass has a size of about 3.5 to 4.0. Then, referring to FIG. 3C, a dielectric material composed of a coating-type low-dielectric-constant material layer having a thickness of about 2K to 12K is formed on the surface of the structure (not shown) shown in FIG. 3B to make it into the metal. The trenches between the lines 32 are filled, and then rapid thermal annealing or heating plate heat treatment is performed to cure and flatten the coated low dielectric constant material layer, and transform its internal structure into a porous structure, becoming a The trench is filled in the ultra-low-dielectric-constant material layer 36 between the metal interconnects 32, and its K value is about 2.0 to 2.5. Finally, referring to FIG. 3D, a chemical vapor deposition method is used to form a dielectric layer 38 having a thickness of about 5K to 20KA on the dielectric layer 34 and the dielectric layer 36. The dielectric layer 38 may be, for example, a low dielectric layer. Made of constant silica glass. After the planarization, a low dielectric constant inner metal dielectric layer hybrid structure 40 composed of the dielectric layer 34, the dielectric layer 36, and the dielectric layer 38 can be completed. The materials of the dielectric layer 38 and the dielectric layer 32 may be similar to those of silica glass. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm. --------- -I I --------- J Order --- I ----- line {Please read the notes on the back before filling in this page) Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs ^- Yau, invention description (7), for example, it can be a dream glass formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD), such as chemical gas Phase-deposited fluorine-doped silica glass (PE-FSG) or high-density plasma chemical vapor deposition of fluorine-doped silica glass (HDP_FSG) 'has a K value of about 3 > 5 ~ 4.0. So far, the low dielectric constant material layer hybrid structure 40 formed according to the process of the present invention has the advantages of both a low dielectric constant coated field oxidation dielectric material and a low dielectric constant chemical vapor deposition material. , Can have a low dielectric constant, and has a high stability to subsequent thermal cycling or contact with other chemicals, and when applied to high-density integrated circuit layout, it will not be used in trench fill metal interconnects. Holes in the trenches. To sum up, the process for manufacturing a metal dielectric layer with a low dielectric constant with a hybrid structure according to the present invention can provide a layer of a low dielectric constant material, and further improves the shortcomings of the conventional manufacturing process. Higher and higher VLSI and ULSI processes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (谙 Please read the precautions on the back before filling in this page.) -Line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 — This paper size applies to the national standard (CNS) A4 specification (210 X 297 mm)