經濟部中央橾準局負工消费合作社印製 415080 at Β7 五、發明説明（/ ) 技術領域= 本發明係關於一種積體電路（1C)的製程技術，特別是 關於在深溝渠電容器(deep trench capacitor)的製程中， 減少複晶矽上層電極多晶矽成長及化學機械研磨製程步驟 的製造方法。 發明背景： 典型動態隨機存取記憶體(DRAM)是在矽半導體基板上 製造一個金氧場效電晶體與電容器，並利用所述場效電晶 體的源極來連接電容器的上層儲存電極（storage node) 以形成動態隨機存取記憶體的記憶元（memory cell)，數 目龐大的記憶元聚集成爲記憶體積體電路。 傳統的動態隨機存取記憶體(DRAM)電容器可分爲堆疊 式和深溝渠電容器兩種型態，所謂的堆疊式電容器是直接 在半導體基板表面形成電容器，而所謂的深溝渠電容器是 在半導體基板內部形成電容器，這兩種型態的電容器各有 其優缺點，因此，在現今的半導體工業也都受到不同廠商 的使用。 最近幾年，動態隨機存取記憶體的集積密度（packing density)快速增加，目前已進入六仟四佰萬位元(64MB)的 量產，要達到動態隨機存取記憶體高度積集化的目的，必 需縮小記憶元的尺寸，亦即，必需縮小場效電晶體與電容 器的尺寸，然而電容器尺寸的縮小將降低電容值，使得記 憶元對於記憶電路的訊號/雜訊（Signal Noise ; S/N)容 忍比例降低，造成資料誤判或資料不穩定等缺點。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） —-----^----tr-- - r 請先閱讀背面之注意事項再填寫本頁) 丁 -* 線ο· 經濟部中央標隼局員工消费合作社印製 4i508C A7 ____^_B7 五、發明説明（> ) 爲了在縮小降低電容器的尺寸時能維持或增加電容器 的電容值，堆疊式電容器以日本的富士通公司（Fujitsu) 的Masao Taguchi等人在美國專利第5,021，357號所揭露 之鰭型電容器結構（fin structure)來增加電容器的表面 積最具代表性，另外，H. ffatanabe等人在IEDM 1992也 揭露了一種新穎的電容器結構。但是爲了在縮小及降低電 容器的尺寸時能同時維持或增加電容器的電容值，使得這 些電容器結構的製程十分繁複，不利於產業的量產之用。 另一方面，堆疊式電容器同時也佔用了許多半導體基板寶 貴的面積，無法進一步的提昇動態隨機存取記憶體的集積 密度以及整合CMOS元件的能力》 相對而言，深溝渠電容器以美國的萬國商業機器公司 (IBM)的Louis Hsu等人在美國專利第5,395,786號所 揭露爲代表性，請參閱圚一，爲一典型習知技藝形成深溝 渠電容器的製程方法，首先，在半導體基板10上形成氧化 矽14以及氮化矽16薄膜，經過黃光、蝕刻形成深溝渠電容 的圖案，然後，蝕刻所述半導體基板10以形成深溝渠，再 於溝渠內表面成長一層0N0(0xide - Nitride - 0xide)18 之介電層。下一步是沈積第一複晶矽層20於所述深溝渠的 底部，以作爲電容器的上層電極，最後，形成氧化矽側壁 子(collar oxide)22於所述深溝渠的側壁，如圖一(A)所 示》接著，沈積第二複晶矽層24填入所述深溝渠，如圖一 (B)所示。之後，先利用化學機械研磨技術（chemical mechanical polishing ; CMP)以及乾蝕刻回蝕法形成第二 -----3- 本紙浪尺度適用中國國家標绛（CNS ) A4規格（2〗0X297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝厂 訂 線-ο-· 經濟部中央標準局兵工消費合作社印製 415080 A7 ________B7 五、發明説明（j ) 複晶矽層閂柱24a於所述深溝渠內，再部份蝕刻所述氧化層 側壁子?2a，使其表面略低於所述第二複晶矽層閂柱24a， 以打開未來電容器與源極/汲極的接觸窗，如圖一(C)所 示。然後，再沈積一第三複晶矽層26填入溝渠之內並如同 第二複晶矽層24—般以化學機械研磨(CMP)，如圖一(D)所 示。最後，以乾蝕刻回蝕法將第三複晶矽層回蝕至稍低於 矽基板10的表面，如圖一(E)所示，而此時所述第三複晶矽 層26a會與即將製作的源/汲極有著電性接觸，所述深溝渠 電容器的製造於焉完成。如再將後績的隔離區（isolation) 以及金氧場效電晶體(未標出)製作於上述之基板，則電容 器的電荷即可經由深溝渠電容器的路徑在源極/汲極與基 板之間進行充電和放電的動作，也就可以執行存入或讀取 動態隨機存取記憶體的資料了。 然而，以上述習知技術所得之深溝渠電容器，其缺點 在於： 1. 必須經由三次複晶矽層的沈積與兩次化學機械研磨 (CMP)，有著許多繁複的製程步驟，增加了晶圓產生缺陷或 是受到汚染的機會，是故將使得產品特性較爲不穩定。 2. 需要佔用生產線機臺較長的時間，使成本上升。 因此，本發明揭露一套減少製程步驟之深溝渠電容器 的製造方法，可以避免習知方法的各種缺點。 發明的簡要說明： 本纸張尺度適用中國國家標孪（CNS ) A4規格（2!ΟΧ297公釐） ；n.、 .ITI I i^~ (請先閲讀背面之注意事項再填寫本頁) 4415080 at Β7 printed by the Central Labor Bureau of the Ministry of Economic Affairs, Consumer Cooperatives V. INTRODUCTION (/) TECHNICAL FIELD = This invention relates to a process technology for integrated circuits (1C), especially in deep trench capacitors (deep trench capacitors) In the manufacturing process of a capacitor, a manufacturing method of reducing polycrystalline silicon growth and chemical mechanical polishing process steps of a polycrystalline silicon upper electrode. Background of the invention: A typical dynamic random access memory (DRAM) is a metal oxide field effect transistor and a capacitor manufactured on a silicon semiconductor substrate, and the source of the field effect transistor is used to connect the upper storage electrode of the capacitor. node) to form a memory cell of a dynamic random access memory. A large number of memory cells are aggregated into a memory volume circuit. Traditional dynamic random access memory (DRAM) capacitors can be divided into two types: stacked and deep trench capacitors. The so-called stacked capacitors form capacitors directly on the surface of the semiconductor substrate, and the so-called deep trench capacitors are on the semiconductor substrate. Capacitors are formed internally. These two types of capacitors each have their advantages and disadvantages. Therefore, in the current semiconductor industry, they are also used by different manufacturers. In recent years, the packing density of dynamic random access memory has increased rapidly. At present, it has entered the mass production of 64 million bits (64MB). To achieve the high accumulation of dynamic random access memory, For the purpose, the size of the memory cell must be reduced, that is, the size of the field effect transistor and the capacitor must be reduced. However, the reduction in the size of the capacitor will reduce the capacitance value, which makes the memory cell signal / noise to the memory circuit (Signal Noise; S / N) The tolerance rate is reduced, which leads to misjudgments or unstable data. This paper size applies to China National Standard (CNS) A4 (210X 297 mm) —----- ^ ---- tr---r Please read the precautions on the back before filling this page) D- * line ο · Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4i508C A7 ____ ^ _ B7 V. Description of the invention (&); In order to maintain or increase the capacitance of the capacitor while reducing the size of the capacitor, the stacked capacitors are based on Fujitsu from Japan Masao Taguchi et al. (Fujitsu) disclosed the fin structure disclosed in US Patent No. 5,021,357 to increase the surface area of the capacitor. In addition, H. ffatanabe et al. Also disclosed in IEDM 1992 A novel capacitor structure is presented. However, in order to maintain or increase the capacitance value of the capacitor while reducing and reducing the size of the capacitor, the manufacturing process of these capacitor structures is very complicated, which is not conducive to industrial mass production. On the other hand, stacked capacitors also occupy a lot of valuable area of semiconductor substrates. It is not possible to further increase the density of dynamic random access memory and the ability to integrate CMOS devices. In contrast, deep trench capacitors Louis Hsu et al. Of IBM Corporation are disclosed in U.S. Patent No. 5,395,786 as a representative. Please refer to the first method for forming a deep trench capacitor in a typical conventional technique. First, an oxide is formed on the semiconductor substrate 10 The silicon 14 and silicon nitride 16 films are yellow-etched and etched to form a deep trench capacitor pattern. Then, the semiconductor substrate 10 is etched to form a deep trench, and a layer of 0N0 (0xide-Nitride-0xide) 18 is grown on the inner surface of the trench. Dielectric layer. The next step is to deposit a first polycrystalline silicon layer 20 on the bottom of the deep trench as the upper electrode of the capacitor. Finally, a silicon oxide sidewall 22 is formed on the side wall of the deep trench, as shown in Figure 1 ( As shown in A), a second polycrystalline silicon layer 24 is deposited to fill the deep trench, as shown in FIG. 1 (B). After that, the chemical mechanical polishing (CMP) technology and the dry etching etch-back method were used to form the second ----- 3- This paper wave scale is applicable to the Chinese National Standard (CNS) A4 specification (2) 0X297 mm ) (Please read the precautions on the back before filling out this page). Assembly line -ο- · Printed by the Military Industry Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 415080 A7 ________B7 V. Description of the invention (j) Polycrystalline silicon layer latch post 24a is in the deep trench, and the oxide sidewall 2a is partially etched so that its surface is slightly lower than the second polycrystalline silicon layer latch post 24a to open the future capacitor and source / drain electrodes. The contact window is shown in Figure 1 (C). Then, a third polycrystalline silicon layer 26 is deposited into the trench and chemical mechanical polishing (CMP) is performed like the second polycrystalline silicon layer 24, as shown in FIG. 1 (D). Finally, the third polycrystalline silicon layer is etched back to a surface slightly lower than the surface of the silicon substrate 10 by a dry etching etch-back method, as shown in FIG. 1 (E). At this time, the third polycrystalline silicon layer 26a and The source / drain to be produced has electrical contact, and the manufacturing of the deep trench capacitor is completed. If the subsequent isolation and metal oxide field effect transistors (not shown) are fabricated on the above substrate, the capacitor's charge can pass between the source / drain and the substrate via the path of the deep trench capacitor. You can perform charging and discharging operations at intervals, and you can also store or read data from dynamic random access memory. However, the deep trench capacitors obtained by the above-mentioned conventional techniques have the following disadvantages: 1. It must pass through three depositions of the polycrystalline silicon layer and two chemical mechanical polishing (CMP) processes. There are many complicated process steps, which increase the wafer production. Defects or the chance of contamination will make the product characteristics more unstable. 2. It takes a long time for the production line machine to increase the cost. Therefore, the present invention discloses a method for manufacturing a deep trench capacitor with reduced manufacturing steps, which can avoid various disadvantages of the conventional method. Brief description of the invention: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2! 〇 × 297mm); n., .ITI I i ^ ~ (Please read the precautions on the back before filling this page) 4
經濟部中夬標準局Μ工消费合作社印製 41508G at ______ B7_ 五、發明説明（$ ) 本發明之主要目的爲提供一種深溝渠電容器的製造方 法’以犧牲層取代了第二複晶矽，減少複晶矽沈積及蝕刻 步驟的次數。 本發明之次要目的爲提供一種深溝渠電容器的製造方 法，可減少製程的成本* 本發明之再一目的爲提供一種深溝渠電容器的製造方 法’可減少晶圓產生缺陷或是受到污染的機會，進而提昇 產品的品質及良率。 本發明係運用以下的製程方式，而達成上述之各種目 的：首先，在半導體基板上成長氧化矽及氮化矽薄膜並以 黃光、蝕刻形成深溝渠，再於深溝渠內表面成長一層ΟΝΟ介 電層，下一步是沈積第一複晶矽層於所述深溝渠的底部， 以作爲電容器的上層電極，然後，形成氧化矽側壁子 (collar oxide)於所述深溝渠的側壁，接著，形成犠牲層 閂柱於所述深溝渠內，此步驟爲本發明之重點所在，此犧 牲層閂柱(sacri f icial plug)可在後續部份蝕刻介電層側 壁子以打開電容器與源極/汲極的接觸窗後，以溼蝕刻方 式輕易的除去，較習知技藝的製程省略了第二複晶矽的沈 積與蝕刻以及化學機械研磨，大幅減少了製程步驟及時 間，所述犧牲層54的材質必須是能作爲電漿蝕刻及濕蝕刻 的幕罩卻又能被溼蝕刻方式輕易的除去，通常是光阻或是 有機的底部抗反射層(bottom anti-refleetive coating ; BARC)，然後，部份蝕刻所述介電層側壁子，使其表面略低 於所述犧牲層閂柱，以打開未來電容器與源極/汲極的接 (請先閲讀背面之注意事項再填寫本頁)Printed by 41508G at ______ B7_, China Industrial Standards Bureau, Ministry of Economic Affairs, V. 5. Description of the invention ($) The main purpose of the present invention is to provide a method for manufacturing deep trench capacitors. Number of polycrystalline silicon deposition and etching steps. A secondary object of the present invention is to provide a method for manufacturing deep trench capacitors, which can reduce the cost of the process. * Another object of the present invention is to provide a method for manufacturing deep trench capacitors, which can reduce the chance of wafer defects or contamination. , Thereby improving product quality and yield. The present invention uses the following process methods to achieve the above-mentioned various objectives: first, silicon oxide and silicon nitride films are grown on a semiconductor substrate and deep trenches are formed by yellow light and etching; and a layer of ΝΟΟ is grown on the inner surface of the deep trenches. The next step is to deposit a first polycrystalline silicon layer on the bottom of the deep trench as the upper electrode of the capacitor, and then form a silicon oxide sidewall on the side wall of the deep trench, and then form The sacrificial layer latch is in the deep trench. This step is the focus of the present invention. The sacri ficcial plug can etch the sidewall of the dielectric layer in the subsequent part to open the capacitor and the source / drain. The contact window of the electrode is easily removed by wet etching. Compared with the conventional manufacturing process, the deposition and etching of the second polycrystalline silicon and the chemical mechanical polishing are omitted, which greatly reduces the process steps and time. The material must be a curtain that can be used for plasma etching and wet etching, but can be easily removed by wet etching. Usually it is a photoresist or an organic bottom anti-reflection layer (bottom anti-r efleetive coating; BARC), and then partially etch the dielectric layer sidewalls so that its surface is slightly lower than the sacrificial layer latch post to open the future capacitor and source / drain connection (please read the back (Please fill in this page again)
，1T 線"ο~· 本紙張尺度適用中國國家標準（CNS ) Α4规格（2】0Χ297公釐） 麪滴部中央標準局員工消費合作社印則4 415080 五、發明説明（爻） 觸窗，且又能確保儲存在電容器的電荷能正確的讀寫，接 著，將所述犧牲層閂柱除去之後，再沈積一第二複晶矽層 填入溝渠之內，最後，將所述第二複晶矽層以回蝕刻或是 化學機械研磨(CMP)形成第二複晶矽閂柱於所述深溝渠內， 所述第二複晶矽閂柱與源/汲極有著電性接觸，本發明所述 之深溝渠電容器的製造方法於焉完成。 圖示的簡要說明： 圖一 (A)至圖一 (E)爲習知技藝中利用三次複晶矽層的 沈積與兩次化學機械研磨(CMP)步驟形成深溝渠 電容器的製程剖面圖。 圖二(A)爲本發明實施例於沈積第一複晶矽和形成介 電層側壁子於所述深溝渠側壁後的剖面圖。 圖二(B)爲本發明實施例於形成犧牲層閂柱後的剖面 圖。 圖二(C)爲本發明實施例於部分蝕刻介電層側壁子的 剖面圖。 圖二(D)爲本發明實施例於沈積第二複晶矽化學機械 研磨後的剖面圖。 圖二(Ε)爲本發明實施例於回蝕第二複晶矽及完成的 結構剖面圖。 圖三爲本發明實施例深溝渠電容器以及金氧場效電晶 體的完成剖面圖。 圖號說明： 10-半導體基板 14-氧化矽層 {請先聞讀背面之注意事項再填寫本頁) 6 、1Τ 本纸張尺度適用中國國家標準{ CNS ) Λ4規格（210X297公釐） 415080 A7 B7 五、發明説明（乙） 16-氮化矽層 18-0N0介電層 20-第一複晶矽 22-氧化矽側壁子 24-第二複晶矽 26-第三複晶矽 40-半導體基板 44-犧牲氧化矽層 46-犠牲氮化矽層 48.介電層 50-第一複晶矽 52-介電層側壁子 54-犧牲層閂柱 56-第二複晶矽 58-淺溝絕緣層 60-閘氧化層 62-金氧場效電晶體閛極 64-源/汲極 70-電荷行進方向 +(請先閲讀背面之注意事項再填寫本頁) 0- 1-一 發明的詳細說明： 以下的實施例係以一動態隨機存取記憶體的深溝渠電 容器來作說明，但本發明的製程方式亦可以用在其他型態 的積體電路元件之溝渠電容器β 請參閱圖二，如同傳統製程，首先我們提供一ρ型半 導體基板40，接著，在半導體基板40上成長氧化矽44及氮 化矽46薄膜並以黃光、蝕刻形成深溝渠，再於深溝渠內表 面成長一層電容器介電層48，下一步是沈積第一複晶矽層 50於所述深溝渠的底部，以作爲電容器的上層電極 (storage node)，最後，形成介電層側壁子（collar dielectric)52於所述深溝渠的側壁，如圖二所示。 部份蝕刻所述半導體基板40以形成深溝渠的步驟，通 常是利用非均向性的電漿蝕刻，如：磁場輔助活性離子式 本紙張尺度適用中國國家標準（CNS M4規格（210X297公费） AU. 經濟部中央標準局負工消费合作社印袈 經濟部中央標隼局員工消費合作社印製 415080 A7 B7 五、發明説明（ij ) 電漿蝕刻技術(MERIE)、電子迺旋共振電漿蝕刻技術(ECR) 或傳統的活性離子式電漿蝕刻技術(RIE)，其反應氣體通常 是CF4、CHF3和Ar。所述電容器介電層48通常是氧化矽一 氣化砍一氧化砂(Oxide - Nitride - Oxide ; ΟΝΟ)的複層 結構，其等效厚度大約爲20埃到150埃之間，但所述電容 器介電層48亦可由五氧二鉬(Ta2〇5)等高介電係數的材料組 成。 所述第一複晶矽50通常是利用同步磷攙雜（in-situ phosphorus doped)之低壓化學氣相沉積法形成，其反應氣 體是（15% PH3/85% SiH4：^(5% PH3/95% N2)的混合氣體， 反應溫度大約550°C，其厚度介於30G0到5000埃之間◎所 述介電層側壁子52通常是利用電漿輔助化學氣相沈積法 (PECVD)所形成的四乙氧基矽烷(TE0S)，但也可以是其他型 態的氧化矽，甚至是氮化矽或是氧化氮化矽亦可，再藉以 垂直非均向性電槳蝕刻法技術，可將多餘基板表面及深溝 渠底部的介電層去除，以完成側壁子的形成。 請參閱圖二(B)，形成犧牲層閂柱54於所述淺溝渠內， 此歩驟爲本發明之重點所在，此犧牲層閂柱54可在後續部 份蝕刻介電層側壁子以打開電容器與源/汲極64的接觸窗 後，以溼蝕刻方式輕易的除去，較習知技藝的製程省略了 第二複晶矽的沈積與蝕刻以及化學機械研磨大幅減少了製 程步驟及時間。所述犧牲層54的材質必須是能作爲電獎触 刻及溼蝕刻的幕罩卻又能被溼蝕刻方式輕易的除去*通常 是光阻或是有機的底部抗反射層(bottom ant i-ref 1 eet ive —^-------r------訂^——線 〇~ (請先閱讀背面之注意事項再填寫本頁)， 1T line " ο ~ · This paper size is applicable to Chinese National Standard (CNS) Α4 specification (2) 0 × 297 mm. Face Drop Department Central Standards Bureau Staff Consumer Cooperatives Seal 4 415080 5. Description of invention (爻) Touching the window, It can also ensure that the charge stored in the capacitor can be read and written correctly. Then, after the sacrificial layer latch is removed, a second polycrystalline silicon layer is deposited to fill the trench, and finally, the second complex is filled. The crystalline silicon layer is etched back or chemical mechanical polishing (CMP) to form a second polycrystalline silicon latch post in the deep trench. The second polycrystalline silicon latch post is in electrical contact with a source / drain. The present invention The manufacturing method of the deep trench capacitor is completed. Brief description of the figure: Figures 1 (A) to 1 (E) are cross-sectional views of a process for forming a deep trench capacitor using three depositions of a polycrystalline silicon layer and two chemical mechanical polishing (CMP) steps in the conventional art. FIG. 2 (A) is a cross-sectional view after depositing a first polycrystalline silicon and forming a dielectric layer sidewall on the sidewall of the deep trench according to an embodiment of the present invention. FIG. 2 (B) is a cross-sectional view of a sacrificial layer latch post according to an embodiment of the present invention. FIG. 2 (C) is a cross-sectional view of a portion of a dielectric layer sidewall etched according to an embodiment of the present invention. Figure 2 (D) is a cross-sectional view of a second embodiment of the present invention after chemical mechanical polishing of a deposited second polycrystalline silicon. FIG. 2 (E) is a cross-sectional view of the second polycrystalline silicon and the completed structure according to the embodiment of the present invention. FIG. 3 is a completed sectional view of a deep trench capacitor and a metal oxide field effect transistor according to an embodiment of the present invention. Description of drawing number: 10-semiconductor substrate 14-silicon oxide layer {Please read the precautions on the back before filling this page) 6, 1T This paper size is applicable to the Chinese National Standard {CNS} 4 specifications (210X297 mm) 415080 A7 B7 V. Description of the invention (B) 16-silicon nitride layer 18-0N0 dielectric layer 20-first polycrystalline silicon 22-silicon oxide sidewall 24-second polycrystalline silicon 26-third polycrystalline silicon 40-semiconductor Substrate 44-sacrificial silicon oxide layer 46-silicon nitride layer 48. Dielectric layer 50-first polycrystalline silicon 52-dielectric layer sidewall 54-sacrificial layer latch 56-second polycrystalline silicon 58-shallow trench Insulating layer 60-gate oxide layer 62-metal oxide field-effect transistor 64electrode 64-source / drain 70-direction of charge + (Please read the precautions on the back before filling this page) 0- 1-Detailed invention Note: The following embodiments are described by using a deep trench capacitor of dynamic random access memory, but the manufacturing method of the present invention can also be used for trench capacitors of other types of integrated circuit components. Please refer to FIG. As in the traditional process, first we provide a p-type semiconductor substrate 40, and then, form a semiconductor substrate 40 on the semiconductor substrate 40. Long silicon oxide 44 and silicon nitride 46 films were formed by deep light and etching to form deep trenches. A capacitor dielectric layer 48 was grown on the inner surface of the deep trenches. The next step was to deposit a first polycrystalline silicon layer 50 on the deep trenches. The bottom of the capacitor is used as a storage node of the capacitor. Finally, a dielectric layer 52 is formed on the side wall of the deep trench, as shown in FIG. 2. The step of partially etching the semiconductor substrate 40 to form deep trenches usually uses non-isotropic plasma etching, such as: magnetic field assisted active ion type. This paper applies Chinese national standards (CNS M4 specification (210X297)) AU Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed 415080 A7 B7 V. Invention Description (ij) Plasma Etching Technology (MERIE), Electron Resonance Plasma Etching Technology ( ECR) or conventional reactive ion plasma etching technology (RIE), the reaction gases of which are usually CF4, CHF3, and Ar. The capacitor dielectric layer 48 is usually silicon oxide-gas-cut sand oxide (Oxide-Nitride-Oxide ΟΝΟ) multi-layer structure, the equivalent thickness of which is between about 20 angstroms to 150 angstroms, but the capacitor dielectric layer 48 may also be composed of a high dielectric constant material such as molybdenum pentoxide (Ta205). The first polycrystalline silicon 50 is usually formed by a low pressure chemical vapor deposition method using in-situ phosphorus doped. The reaction gas is (15% PH3 / 85% SiH4: ^ (5% PH3 / 95 % N2) The temperature is about 550 ° C, and its thickness is between 30G0 and 5000 angstroms. ◎ The dielectric sidewall 52 is usually a tetraethoxysilane (TE0S) formed by plasma-assisted chemical vapor deposition (PECVD). However, it can also be other types of silicon oxide, even silicon nitride or silicon nitride oxide. With the help of vertical anisotropic paddle etching technology, the dielectric between the surface of the excess substrate and the bottom of the deep trench can be used. The electrical layer is removed to complete the formation of the sidewall. Referring to FIG. 2 (B), a sacrificial layer latch post 54 is formed in the shallow trench. This step is the focus of the present invention. Subsequent partial etching of the sidewall of the dielectric layer opens the contact window between the capacitor and the source / drain 64, and is easily removed by wet etching. Compared with the conventional manufacturing process, the second polycrystalline silicon deposition and etching and chemical are omitted. Mechanical grinding greatly reduces the process steps and time. The material of the sacrificial layer 54 must be a curtain that can be used for electrical engraving and wet etching, but can be easily removed by wet etching. * Usually photoresist or organic Bottom anti-reflection layer (bottom ant i-ref 1 eet ive — ^ ------- r ------ Order ^ —— line 〇 ~ (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CTNS ) A4規格（210X2^公釐） 415080 B7 經濟，哪中央標準局貞工消f合作社印製 五、發明説明（ί ) coating ; BARC)，底部抗反射層(BARC)是高分子聚合物 (polymqr)如乙基乳酸鹽(ethyl lactate)之類的物質。 請參閱圖二(C)，部份蝕刻所述介電層側壁子52a，使 其表面略低於所述犧牲層閂柱，以打開未來電容器與源/汲 極64的接觸窗。蝕刻所述介電層側壁子52a的步驟，則仍是 利兩前述之非均向性電槳蝕刻技術操作之。 請參閱圖二(D)及圖二(E)，將所述犧牲層閂柱除去之 後，再沈積一第二複晶砍層56填入溝渠之內，如圖二(D)所 示，最後，將所述第二複晶矽層56以回蝕刻或是化學機械 研磨(CMP)形成第二複晶矽閂柱56a於所述深溝渠內，所述 第二複晶矽閂柱與源/汲極有著電性接觸，如圖二(E)所 示，本發明所述之深溝渠電容器的製造方法於焉完成。 除去所述光阻或底部抗反射層(BARC)犧牲層閂柱的步 驟，通常是以硫酸(H2S04)和雙氧水〇!202)的混合溶液操作 之，即可以輕易地將光阻以及底部抗反射層(BARC)除去。 請參閱圖三，本發明在深溝渠電容器後，可繼續形成 如再將後續的隔離區（isolation)58以及金氧場效電晶體製 作於上述之基板，則電容器的電荷即可經由深溝渠電容器 的路徑70在源極/汲極與基板之間進行充電和放電的動 作，也就可以執行存入或讀取動態隨機存取記憶體的資料 了。所述金氧場效電晶體包含有閘氧化層6G、閘極62、與 源極/汲極64，至於形成金氧場效電晶體的步驟，屬於習 知技藝的範疇，在此不加以贅述。 相對於習用技術，本發明具有下列優點： 張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) -ην 訂 -線 ο-· 415080 A7 B7 五、發明説明（ (1) 根據習用技術’至少需要用到三次複晶矽層的沈積 與兩次化學機械研磨(CMP) ’然而，根據本發明，由於應用 了犧牲層取代了第二複晶矽，減少了複晶矽沈積及蝕刻步 驟的次數，可減少製程的成本。 (2) 由於減少製程的步驟，所以製程時間（work-in-process time) 大幅 減少’ 自然交貨時間 （ turn-around time)也就較短’較短的交貨時間對於積體電路元件製造者 而言，是極力想達到的目標之一。 (3) 複晶矽層的沈積與化學機械研磨(CMP)使用的減 少，也可以減少因標準製程所引入的微粒，整個晶圓的缺 陷也會大爲減少，是故減少額外的製程變數，將使得產品 特性較爲穩定》 上述說明係以較佳實施例來闡述本發明，而非限制本 發明，並且，熟知積體電路技藝之人士皆能明瞭，適當而 作些微的改變及調整，仍將不失本發明之要義所在，亦不 脫離本發明之精神和範圍。 經濟部中央標华局負工消费合作社印製 木紙張尺度適用中國國家標準（CNS ) A4規格（2】0Χ297公釐） (請先閲讀背面之注意事項再填寫本頁}This paper scale applies Chinese National Standard (CTNS) A4 specification (210X2 ^ mm) 415080 B7 Economy, which is printed by the Central Standards Bureau Zhengong Xiao F Cooperative V. Description of Invention (ί) coating; BARC), bottom anti-reflective layer ( BARC) is a polymer (polymqr) such as ethyl lactate. Referring to FIG. 2 (C), the dielectric layer side wall 52a is partially etched so that its surface is slightly lower than the sacrificial layer latch post to open the contact window between the future capacitor and the source / drain 64. The step of etching the dielectric layer sidewalls 52a is still performed by using the two aforementioned anisotropic electric pad etching techniques. Please refer to FIG. 2 (D) and FIG. 2 (E). After the sacrificial layer latch is removed, a second polycrystalline cutting layer 56 is deposited into the trench, as shown in FIG. 2 (D), and finally The second polycrystalline silicon layer 56 is etched back or chemical mechanical polishing (CMP) to form a second polycrystalline silicon latch post 56a in the deep trench. The second polycrystalline silicon latch post and the source / The drain electrode has electrical contact. As shown in FIG. 2 (E), the manufacturing method of the deep trench capacitor according to the present invention is completed. The step of removing the photoresist or the bottom anti-reflection layer (BARC) sacrificial layer latch post is usually performed by using a mixed solution of sulfuric acid (H2S04) and hydrogen peroxide (202), that is, the photoresist and bottom anti-reflection can be easily removed. The layer (BARC) was removed. Please refer to FIG. 3, after the deep trench capacitor according to the present invention, if the subsequent isolation region 58 and the metal oxide field effect transistor are fabricated on the above substrate, the capacitor's charge can pass through the deep trench capacitor. The path 70 performs charging and discharging operations between the source / drain and the substrate, and thus can perform storing or reading data in the dynamic random access memory. The metal oxide field effect transistor includes a gate oxide layer 6G, a gate electrode 62, and a source / drain 64. As for the step of forming the metal oxide field effect transistor, it belongs to the conventional art and will not be repeated here. . Compared with conventional technology, the present invention has the following advantages: Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) -ην Order-line ο- · 415080 A7 B7 V. Description of the invention ((1) According to the conventional technology, 'at least three depositions of the polycrystalline silicon layer and two chemical mechanical polishing (CMP)' are required. 'However, according to the present invention, the second Crystalline silicon reduces the number of polycrystalline silicon deposition and etching steps, which can reduce the cost of the process. (2) Because the number of process steps is reduced, the work-in-process time is greatly reduced. -around time) is also a short 'short delivery time' is one of the goals that integrated circuit component manufacturers want to achieve. (3) Deposition of polycrystalline silicon layer and chemical mechanical polishing (CMP) The reduction of use can also reduce the particles introduced by the standard process, and the defects of the entire wafer will be greatly reduced. Therefore, reducing additional process variables will make the product characteristics more stable. The present invention is described in the preferred embodiments, but not to limit the present invention. Those skilled in the art of integrated circuit will understand that appropriate changes and adjustments will not lose the essence of the present invention, nor will it Depart from the spirit and scope of the present invention. The standard of printed wood paper used by the Central Bureau of Standardization of China's Ministry of Economic Affairs and Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the notes on the back before filling in this page}