412848 A7 B7 經濟部中央樣準局員工消費合作社印製 五、發明説明（f ) 本發明是有關於一種快閃記憶體（Flash Memory)之 製造方法，且特別是有關於一種結合自行對準源極 (Self-align Source ;簡稱 SAS)和淺溝渠隔離（Shallow Trench Isolation )製程之快閃記憶體的製造方法。 一般傳統的快閃記憶體結構，閘極包括用來儲存電荷 (Charge)的浮置閘（Floating Gate)和用來控制資料存取 的控制閘（Control Gate)。其中浮置閘位於控制閘和基底 之間，且處於浮置狀態，沒有和任何電路相連接；而控制 閘則與字元線（Word Line)相接。 以NOR ( N〇t-OR)型陣列之快閃記憶體爲例，傳統之 NOR型陣列快閃記憶體的電路佈局設計如第1圖所示，其 中，每個快閃記憶體10的控制閘都連接到字元線Wk或 WL2，每個快閃記憶體10的汲極（Drain)則連接到位元線 BL,或BL2，而兩個相鄰的快閃記憶體10採取共用源極 (Common Source )的設計，因此於兩條位元線和BL2 之間有一條共用源極線CS來控制源極。通常位元線BL,、 BL2與共用源極線CS會平行分佈，且與字元線WL,、WL2 互相垂直，而共同組成NOR型陣列快閃記憶體。 第2圖係繪示習知結合自行對準源極和場氧化層製程 的快閃記憶體之上視圖。圖中虛線方框130的區域是爲共 用源極的兩個快閃記憶胞。首先，於矽基底100中形成數 條連續之長條形場氧化層，用以大約隔離出元件主動區， 其中場氧化層與後續形成之控制閘110相垂直。接著於矽 基底100上形成暴露出場氧化層的多晶矽層，再於多晶矽 層上依序形成介電層和控制閘110。在形成控制閘110的 3 n^i— I ^^^1 - -- ^^^1 : ^irr— i (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4祝格（2丨0 X 297公嫠） 412848 經濟部中央標準局貝工消費合作社印聚 五、發明説明（）） 過程中，同時將多晶矽層圖案化成浮置閘1 12。之後，將 位於欲形成共用源極線116的場氧化層剝除，於是形成如 圖示之場氧化層102。進行離子植入製程，用以形成共用 源極線Π6和汲極114。之後，於整個元件上方覆蓋一層 絕緣層，再於絕緣層上方形成一條與控制閘110垂直的位 元線120，並經由接觸窗122與汲極114接觸。 然而’以場氧化層102做爲快閃記憶體的電性隔離會 占據矽基底1〇〇太多空間，爲了提高元件的積集度，因此 需要製作出極小尺寸的快閃記憶體。 爲達成上述和其他目的，本發明提供一種快閃記憶 體’包括：在表面已形成氧化層的基底中形成複數個連續 條狀淺溝渠隔離結構，於氧化層上形成第一導電層，此第 一導電層暴露出淺溝渠隔離結構的表面。於第一導電層的 表面依序形成介電層和第二導電層，並定義第二導電層以 形成複數個條狀控制閘，使其與淺溝渠隔離結構相垂直， 繼續對介電層和第一導電層進行定義，使第一導電層形成 複數個浮置閘。於控制閘、介電層和浮置閘的側壁形成複 數個間隙壁，再進行一第一離子植入製程，以於控制閘之 一側下方的基底中形成複數個汲極區。將控制閘之另一側 下方的淺溝渠隔離結構中之氧化物剝除，以形成暴露出基 底表面的複數個開口，之後進行斜角的旋轉離子植入製 程，用以於開U的基底中和控制閘之另一側下方的基底中 形成離子佈植區，此離子佈植區與控制閘平行，且爲兩相 鄰之控制閘所共用，其爲一共用源極線。 依照本發明的一較佳實施例，其中斜角的旋轉離子植 4 I - - ^^1 I- - —^1 - - ------i I- n^i n ——ί (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS) Α4規格（210Χ297公釐） 經濟部中央標準局貝工消費合作社印聚 412848 A7 梢―_ _ B7__ 五、發明説明（^ ) 入製程的離子植人角度約爲15度至45度，所植入的離子 爲N型，比如是磷離子（P+)或砷離子（As+)，所植入 的劑量約爲丨E15至1E16原子/平方公分。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係繪示傳統之NOR型陣列快閃記憶體的電路佈 局設計； 第2圖係繪示習知結合自行對準源極和場氧化層製程 的快閃記憶體之上視圖； 第3A圖至第3F圖係繪示根據本發明較佳實施例之一 種結合自行對準源極和淺溝渠隔離的製程之快閃記憶體 的製造流程剖面圖； 第4圖係繪示第3F圖之未位於淺溝渠隔離結構的橫 向切面圖； 第5圖係繪示第3 F圖之位於淺溝渠隔離結構的橫向 切面圖；以及 第6圖係繪示第3F圖之共用源極線的縱向切面圖。 其中，各圖標號與構件名稱之關係如下： 1〇 =快閃記憶體 WL,、WL2 :字元線 BL, ' BL2、120 :位元線 CS ' 1 16 :共闬源極線 1〇〇 :矽基底 5 本紙張财關家料（CNS ) A峨格（210X297公嫠） ^ (請先閱讀背面之注意事項再填寫本頁} .裝· l1T- A7 412648 4iystwi.ii.ic/oox B7 五、發明説明（& ) 110 :控制閘 1 1 2 :浮置閘 102 :場氧化層 1 1 4、2 1 8 :汲極 122 :接觸窗 200 ·•基底 202、202a :淺溝渠隔離結構 204 :氧化層 206、206a :導電層（浮置閘） 210 :導電層（控制閘） 208 :介電層 2 1 2 :間隙壁 214 :開口 216:離子佈植區 實施例 第3 A圖至第3 F圖所不，爲根據本發明一較佳實施例 之一種結合自行對準源極和淺溝渠隔離的製程之快閃記 憶體的製造流程剖面圖。在此係以NOR型陣列快閃記憶體 爲例。 首先請參照第3 A圖，提供一基底200，比如是半導體 石夕基底，於基底200表面形成一層氧化層204，做爲穿遂 氧化層之用，其形成方法比如是熱氧化法。接著於基底200 中形成連續的長條形淺溝渠隔離結構2〇2,其中塡充有絕 緣材質（比如氧化物）做爲電性隔離之用，其方法比如是 利用傳統的淺溝渠製程，在此不多贅言。 6 本紙張h適用¥國國家標準（CNS ) A4規格（210父297公^_) " " ^1. - - «II I - ! n I I I J, I I - -I ^^1 ! I X {諳先聞讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印裝 經濟部中央標準局員工消费合作社印製 412848 A7 4 1^5lu ('.(.1nc/i)〇X gy 五、發明説明（^ ) 接著請參照第3B圖，於氧化層204上形成一層導電 層，其材質比如是摻雜的多晶矽，將此導電層圖案化，使 其大約暴露出淺溝渠隔離結構202的表面，以形成如圖式 之導電層206。 接著請參照第3C圖，於導電層206的表面形成一層 介電層，其材質比如是氧化矽-氮化矽-氧化矽、氧化矽或 氮化矽等，其形成方法比如是低壓化學氣相沈積法。之 後，於整個基底200結構表面形成另一層導電層，其材質 比如是摻雜的多晶矽，利用罩幕將此導電層圖案化，用以 定義出做爲控制閘之用的導電層210，在定義導電層210 的同時，繼續以相同的罩幕定義介電層和導電層206，使 其分別形成介電層208和導電層206a。其中導電層206a 係做爲浮置閘之用。即快閃記憶體的閘極係由圖示之導電 層（控制閘）2】0、介電層208和導電層（浮置閘）206a 的堆疊結構所構成。 接著請參照第3D圖，於導電層210、介電層208和導 電層206a的側壁形成一間隙壁212,其材質比如是氮化 矽，其方法比如於整個基底200表面形成一層共形的氮化 矽層，再進行非等向性蝕刻製程。之後，於整個基底200 結構表面形成一層罩幕層230，比如是光阻，此罩幕層暴 露出欲形成汲極的區域，以此罩幕層、導電層210、間隙 壁212和淺溝渠隔離結構202a爲植入罩幕，進行離子植入 製程1用以於導電層210之一側下方的基底200中形成汲 極218，所植入的離子之導電型較佳的是N型，所植入的 離子比如是磷離子或是砷離子。 7 -11 - I . - —i - 士^1_ -I n I xw (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消费合作社印製 412848 4μ)Μνν1.ϋικ/<ί〇Κ i五、發明説明（）412848 A7 B7 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 5. Description of the Invention (f) The present invention relates to a method for manufacturing a flash memory, and more particularly to a method for combining self-aligned sources Manufacturing method of flash memory in Self-align Source (SAS) and Shallow Trench Isolation processes. In general conventional flash memory structures, the gate includes a floating gate for storing charges and a control gate for controlling data access. The floating gate is located between the control gate and the base and is in a floating state without being connected to any circuit. The control gate is connected to the Word Line. Taking a flash memory of a NOR (Not-OR) array as an example, the circuit layout design of a conventional NOR array flash memory is shown in FIG. 1, where each flash memory 10 is controlled by The gates are connected to the word line Wk or WL2, the drain of each flash memory 10 is connected to the bit line BL, or BL2, and two adjacent flash memories 10 use a common source ( Common Source), so there is a common source line CS between the two bit lines and BL2 to control the source. Generally, the bit lines BL, and BL2 and the common source line CS are distributed in parallel, and are perpendicular to the word lines WL, and WL2 to form a NOR-type array flash memory. Figure 2 is a top view of a conventional flash memory combining a self-aligned source and field oxide process. The area of the dashed box 130 in the figure is two flash memory cells for a common source. First, a plurality of continuous strip-shaped field oxide layers are formed in the silicon substrate 100 to approximately isolate the active area of the device, wherein the field oxide layer is perpendicular to the control gate 110 formed subsequently. Then, a polycrystalline silicon layer is formed on the silicon substrate 100 to expose the field oxide layer, and then a dielectric layer and a control gate 110 are sequentially formed on the polycrystalline silicon layer. 3 n ^ i— I ^^^ 1--^^^ 1: ^ irr— i (Please read the notes on the back before filling this page) to form the control gate 110 CNS) A4 Zhuge (2 丨 0 X 297 Gong) 412848 In the process of printing, polycrystalline silicon layer is patterned into floating gate 1 12 during the process of polysilicon layer patterning. After that, the field oxide layer on the common source line 116 to be formed is stripped, and a field oxide layer 102 is formed as shown in the figure. An ion implantation process is performed to form a common source line Π6 and a drain 114. After that, an insulating layer is covered over the entire element, and a bit line 120 perpendicular to the control gate 110 is formed over the insulating layer, and is in contact with the drain electrode 114 through the contact window 122. However, the electrical isolation using the field oxide layer 102 as the flash memory will occupy too much space on the silicon substrate. In order to increase the accumulation degree of the device, it is necessary to make a flash memory of a very small size. In order to achieve the above and other objects, the present invention provides a flash memory including: forming a plurality of continuous strip-shaped shallow trench isolation structures in a substrate having an oxide layer formed on the surface; and forming a first conductive layer on the oxide layer. A conductive layer exposes the surface of the shallow trench isolation structure. A dielectric layer and a second conductive layer are sequentially formed on the surface of the first conductive layer, and the second conductive layer is defined to form a plurality of stripe-shaped control gates, which are perpendicular to the shallow trench isolation structure. The first conductive layer is defined so that the first conductive layer forms a plurality of floating gates. A plurality of gap walls are formed on the side walls of the control gate, the dielectric layer and the floating gate, and then a first ion implantation process is performed to form a plurality of drain regions in the substrate below one side of the control gate. The oxide in the shallow trench isolation structure under the other side of the control gate is stripped to form a plurality of openings exposing the surface of the substrate, and then a beveled rotary ion implantation process is performed in the substrate to open the U An ion implantation region is formed in the substrate below the other side of the control gate. This ion implantation region is parallel to the control gate and shared by two adjacent control gates, which is a common source line. According to a preferred embodiment of the present invention, the beveled rotating ion plant 4 I--^^ 1 I---^ 1-------- i I- n ^ in —— (Please first Read the notes on the reverse side and fill in this page) This paper size is applicable to China National Standards (CNS) A4 (210 × 297 mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, 412848 A7 Pin __ _ B7__ V. Description of the invention (^) The implantation angle of the ion implantation process is about 15 to 45 degrees. The implanted ions are N-type, such as phosphorus ions (P +) or arsenic ions (As +). The implanted dose is about 丨 E15. To 1E16 atoms / cm². In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 Figure 2 shows the circuit layout design of a conventional NOR-type flash memory; Figure 2 is a top view of a conventional flash memory combining self-aligned source and field oxide processes; Figures 3A to 3F FIG. 4 is a cross-sectional view showing a manufacturing process of a flash memory combining a self-aligned source and a shallow trench isolation process according to a preferred embodiment of the present invention; FIG. 4 is a view of FIG. 3F which is not located in a shallow trench A cross-sectional view of the isolation structure; FIG. 5 is a cross-sectional view of FIG. 3 F showing a shallow trench isolation structure; and FIG. 6 is a longitudinal cross-sectional view of the common source line of FIG. 3F. The relationship between each icon number and the component name is as follows: 10 = flash memory WL ,, WL2: character line BL, 'BL2, 120: bit line CS' 1 16: common source line 100. : Silicon substrate 5 sheets of papers (CNS) A Ege (210X297) ^ (Please read the precautions on the back before filling out this page}. L1T- A7 412648 4iystwi.ii.ic / oox B7 V. Description of the invention & 110: Control gate 1 1 2: Floating gate 102: Field oxide layer 1 1 4, 2 1 8: Drain 122: Contact window 200 · • Substrate 202, 202a: Shallow trench isolation structure 204: oxide layer 206, 206a: conductive layer (floating gate) 210: conductive layer (control gate) 208: dielectric layer 2 1 2: spacer 214: opening 216: embodiment of ion implantation area Figure 3F is a cross-sectional view of the manufacturing process of a flash memory in accordance with a preferred embodiment of the present invention in combination with a self-aligned source and shallow trench isolation process. Here, a NOR-type array flash is used. The memory is taken as an example. First, referring to FIG. 3A, a substrate 200 is provided, such as a semiconductor stone substrate, and an oxide layer 204 is formed on the surface of the substrate 200. In order to penetrate the oxide layer, its formation method is, for example, a thermal oxidation method. Then, a continuous strip-shaped shallow trench isolation structure 200 is formed in the substrate 200, in which an insulating material (such as an oxide) is filled as electricity. For sexual isolation, the method is to use the traditional shallow trench process, for example. 6 This paper h is applicable to the national standard (CNS) A4 specification (210 father 297 public ^ _) " " ^ 1 .--«II I-! N IIIJ, II--I ^^ 1! IX (谙 Please read the precautions on the back before filling out this page) Central Standards Bureau of the Ministry of Economic Affairs, Central Standards of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 412848 A7 4 1 ^ 5lu ('. (. 1nc / i) 〇X gy V. Description of the Invention (^) Then refer to Figure 3B to form a conductive layer on the oxide layer 204, the material For example, doped polycrystalline silicon, this conductive layer is patterned so as to approximately expose the surface of the shallow trench isolation structure 202 to form a conductive layer 206 as shown in the figure. Then refer to FIG. 3C on the surface of the conductive layer 206 Forming a dielectric layer, the material of which is silicon oxide-silicon nitride-silicon oxide, Silicon silicon or silicon nitride is formed by a low-pressure chemical vapor deposition method. Then, another conductive layer is formed on the entire surface of the substrate 200 structure. The material is, for example, doped polycrystalline silicon, and the conductive layer is formed by a mask. Patterning is used to define the conductive layer 210 as a control gate. While defining the conductive layer 210, continue to define the dielectric layer and the conductive layer 206 with the same mask, so that they form the dielectric layer 208 and The conductive layer 206a. The conductive layer 206a is used as a floating gate. That is, the gate of the flash memory is composed of a stacked structure of a conductive layer (control gate) 2] 0, a dielectric layer 208, and a conductive layer (floating gate) 206a as shown in the figure. Next, referring to FIG. 3D, a gap 212 is formed on the sidewalls of the conductive layer 210, the dielectric layer 208, and the conductive layer 206a. The material is, for example, silicon nitride, and the method is to form a layer of conformal nitrogen on the entire substrate 200 surface. Silicon layer, and then anisotropic etching process. After that, a mask layer 230 is formed on the entire surface of the substrate 200 structure, such as a photoresist. This mask layer exposes the area where the drain is to be formed, and the mask layer, the conductive layer 210, the partition wall 212 and the shallow trench are separated from each other. The structure 202a is an implant mask, and an ion implantation process 1 is performed to form a drain electrode 218 in the substrate 200 below one side of the conductive layer 210. The conductivity type of the implanted ions is preferably N type. The ions that are introduced are, for example, phosphorus ions or arsenic ions. 7 -11-I.-—I-Shi ^ 1_ -I n I xw (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297mm) Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 412848 4μ) Μνν1.ϋικ / < ί〇Κi V. Description of the Invention ()
I 接著請參照第3E圖，將罩幕層230剝除後，繼續於 整個基底200結構表面形成·一層罩幕層232,比如是光阻， 此卓幕層2 3 2暴露出欲形成共用源極線的區域。以罩幕層 232、導電層2 10和間隙壁212爲硬罩幕，進行非等向性 蝕刻製程，將導電層210之另一側下方的淺溝渠隔離結構 202中之氧化物剝除，以於基底200中形成開口 214，而 淺溝渠隔離結構202則轉爲淺溝渠隔離結構202a，在剝除 淺溝渠隔離結構202中之氧化物的同時，亦會有部份氧化 層2〇4被剝除，使氧化層204轉爲氧化層204a。 接著請參照第3F圖，繼續進行一斜角的旋轉離子植 入製程，用以於所暴露的基底200 (包括開口 214所暴露 的基底200 )中形成離子佈植區216,此離子佈植區216 與作爲控制閘的導電層210平行，離子佈植區216爲兩相 鄰之導電層2 1 0所共用，其爲一共用源極線。其中斜角的 旋轉離子植入製程的離子植入角度約爲15度至45度，所 植入的離子之導電型較佳的是N型，所植入的離子比如是 磷離子或砷離子，所植入的劑量約爲1E15至1E16原子/ 平方公分。之後再將罩幕層232予以剝除。 第4圖係繪示第3F圖之未位於淺溝渠隔離結構的橫 向切面圖。第5圖係繪示第3F圖之位於淺溝渠隔離結構 的橫向切面圖。第6圖係繪示第3F圖之共用源極線的縱 向切面圖。 本發明不僅適用於Ν Ο R型陣列的快閃記憶體，亦可適 用於NAND ( Not-AND Gate)型陣列的快閃記億體。 本發明的特徵如下： 8 -I !1 - l^i —i- - -I 1 I 1 (請先閲讀背面之注項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α衫見格（210X297公嫠） 412848 五、發明説明（q ) 1. 本發明係提供一種結合自行對準源極和淺溝渠隔 離結構的製程之快閃記憶體的製造方法。 2. 本發明於控制閘和浮置閘兩側之間隙壁形成後，剝 除共用源極間的淺溝渠隔離結構中的氧化物及剝除共用 源極之基底表面的氧化層，以暴露出基底表面，之後利用 斜角的旋轉離子植入製程，於所暴露出的基底中形成離子 佈植區，以形成平行於控制閘之共用源極線。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 —：--------裝— (請先閱讀背命之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 9 本紙張尺度適用中國围家標準（CNS ) A4祝格（210X297公釐）I Please refer to FIG. 3E. After stripping the mask layer 230, continue to form a layer of mask layer 232 on the entire surface of the substrate 200 structure, such as a photoresist. This curtain layer 2 3 2 is exposed to form a common source. The area of the epipolar line. Using the mask layer 232, the conductive layer 210, and the spacer 212 as hard masks, an anisotropic etching process is performed to remove the oxide in the shallow trench isolation structure 202 below the other side of the conductive layer 210 to An opening 214 is formed in the substrate 200, and the shallow trench isolation structure 202 is converted to a shallow trench isolation structure 202a. When the oxide in the shallow trench isolation structure 202 is stripped, a part of the oxide layer 204 is also stripped. The oxide layer 204 is converted into the oxide layer 204a. Next, referring to FIG. 3F, a beveled rotary ion implantation process is continued to form an ion implantation region 216 in the exposed substrate 200 (including the substrate 200 exposed by the opening 214). This ion implantation region 216 is parallel to the conductive layer 210 as a control gate, and the ion implantation region 216 is shared by two adjacent conductive layers 210, which is a common source line. The angle of the ion implantation process of the beveled rotary ion implantation process is about 15 to 45 degrees. The conductivity type of the implanted ions is preferably N type. The implanted ions are, for example, phosphorus ions or arsenic ions. The implanted dose is approximately 1E15 to 1E16 atoms / cm². The mask layer 232 is then removed. Figure 4 is a cross-sectional view of Figure 3F, which is not located in the shallow trench isolation structure. Figure 5 is a cross-sectional view of the shallow trench isolation structure in Figure 3F. Fig. 6 is a longitudinal sectional view showing the common source line in Fig. 3F. The invention is not only applicable to the flash memory of the ΝΟR type array, but also applicable to the flash memory of the NAND (Not-AND Gate) type array. The features of the present invention are as follows: 8 -I! 1-l ^ i —i---I 1 I 1 (Please read the note on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS) Grid (210X297) 412848 V. Description of the Invention (q) 1. The present invention provides a method for manufacturing a flash memory by combining a self-aligned source and a shallow trench isolation structure. 2. After the gaps on both sides of the control gate and the floating gate are formed in the present invention, the oxide in the shallow trench isolation structure between the common sources is stripped and the oxide layer on the substrate surface of the common source is stripped to expose On the substrate surface, an ion implantation region is formed in the exposed substrate by using a beveled rotary ion implantation process to form a common source line parallel to the control gate. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. — ： -------- Installation— (Please read the precautionary instructions before filling out this page) Printed by the Sheller Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 9 This paper is in accordance with the Chinese Standard for Enclosure (CNS) A4 Zhuge (210X297 mm)