412846 五、發明說明（ο 本發明係有關於一種基底偏壓偵測電路（s u b s t r a t e bias detector)，特別是一種用於CMOS基底之偏壓偵測電 路，可減小VBB隨VCC增加而變動之幅度，降低產生偏壓 (VBB)中主電源（VCC)成分，降低接面反偏壓（junction reverse bias)的程度。 一般M0S製程中常會對基底施以偏壓（VBB)以防止漏電 流（leakage current)發生。偏壓產生器電路大致包括兩 部分：偏壓偵測電路與電荷泵電路。如第1圖所示為基底 偏壓電路之方塊圖。以P-基底為例，當M0S基底10之偏壓 位準VBB因如漏電流等因素而高於偏壓偵測電路丨2中所預 設之範圍時’振盪器驅動電路14會啟動振盪器並發出致動 (enable)信號至電荷泵電路μ，啟動電荷泵電路16將M0S 基底1 0内的電荷打入地線（gr〇und )中。此時M〇s基底^ 〇 之偏壓位準VBB會隨電荷泵電路16所排出之電荷增加而下 降°當偏壓位準位準到達偏壓偵測電路1 2所預定之下 限值時’偏壓偵測電路1 2將停止振盪器驅動電路1 4運作並 關閉電荷泵電路1 6。 第2圖所示為第1圖中基底偏壓器電路運作時偏壓位準 VBB與時間T之關係圖。VH與几分別為預設基底偏壓位準位 ，VBB之上限與下限值’ vA則為理想基底偏壓位準位準之 平均值。在時間T1與T2期間，基底偏壓位準VBB可能因元 ^發生漏電流逐漸升高。當偏壓位準位準VBB到達上限值 $ 振堡器驅動電路1 4開始運作，致動電荷泵電路1 6排 ，于’基底電荷。此時偏壓位準VBB會如時間T2至T3所示一412846 V. Description of the invention (ο The present invention relates to a substrate bias detector circuit, especially a bias detection circuit for a CMOS substrate, which can reduce the amplitude of VBB as VCC increases. In order to reduce the main power supply (VCC) component in the generated bias voltage (VBB), the degree of junction reverse bias is reduced. Generally, the substrate is biased (VBB) during the M0S process to prevent leakage. current). The bias generator circuit roughly includes two parts: the bias detection circuit and the charge pump circuit. The block diagram of the base bias circuit is shown in Figure 1. Taking the P-base as an example, when the M0S base When the bias level VBB of 10 is higher than the range preset in the bias detection circuit due to factors such as leakage current, etc. 2 'the oscillator drive circuit 14 will start the oscillator and send an enable signal to the charge The pump circuit μ starts the charge pump circuit 16 and charges the charge in the M0S substrate 10 into the ground (grund). At this time, the bias level VBB of the M0s substrate ^ 〇 will be discharged with the charge pump circuit 16 The charge increases and decreases ° when the bias level When the predetermined lower limit value of the bias detection circuit 12 is reached, the 'bias detection circuit 12 will stop the oscillator driving circuit 14 and shut down the charge pump circuit 16. Figure 2 shows the figure 1 The relationship between the bias level VBB and the time T when the substrate bias circuit operates. VH and several are the preset substrate bias levels, respectively. The upper and lower limits of VBB 'vA are the ideal substrate bias levels. The average value of the level. During the time T1 and T2, the base bias level VBB may gradually increase due to the leakage current. When the bias level VBB reaches the upper limit value $ Vibrator driver circuit 1 4 Begin operation, actuate the charge pump circuit 16 rows, at the 'base charge. At this time, the bias level VBB will be as shown by time T2 to T3.
第4頁 412846 五、發明說明（2) '--- 般因電荷的排除而逐漸朝下限值V L接近。同樣地，當偏 壓位準VBB到達下限值U後，振篕器驅動電路14與電荷泵 電路16停止運作，偏壓位準VBB將因元件所產生之漏電流 又再度升高。 在習知技術中，偏壓偵測電路丨2所偵測得之偏壓位準-VBB多為電源VCC函數。換言之，偏壓位準VBB之值會隨所 供應電源VCC之變化而改變。 第3A與第3B圖所示分別為高偏壓位準VH與低電壓位準 VL之偏壓谓測電路。其中兩相串聯p型M〇s電晶體ρι與卩2以 及P11與P1 2可分別視為高偏壓位準偵測電路與低偏壓位準 偵測電路之阻抗。端點NA與NB則分別為p型MOS電晶體P1與 P2以及P11與P12之連接點，由端點να與NB所取得之電位分 別經過P型電晶體P3與N型電晶體M3以及P型電晶體P1 3與N 型電晶體N1 3所組成CMOS反閘，以及雙重緩衝反閘〖1與I 2 以及111與11 2後分別輸出偵測位準狀態（d e t e c t e d 1 e v e 1 state)Vl 與V2 。 第3A與3B圖、第4圖、以及第5A與5B圖中各電晶體旁 皆標示出製程電晶體之寬/長比。 比較第3A與第3B圖中可觀察出兩電路中僅電晶體p 2與 P1 2之寬/長比不同，除此之外其他元件之規格與配置皆相 同。事實上，調整電晶體之寬/長比大小可改變其阻抗負 載之大小。以電晶體P2(寬/長比為4u/1 232u)與電晶體 P12(寬/長比為4u/2688u)為例，因電晶體P2之閘道長度小 於電晶體P12，故電晶體P2之阻抗值小於電晶體pi2。此Page 4 412846 V. Description of the invention (2) '-Generally, the lower limit value V L is gradually approached due to the elimination of charge. Similarly, when the bias voltage level VBB reaches the lower limit U, the oscillator driving circuit 14 and the charge pump circuit 16 stop operating, and the bias voltage level VBB will increase again due to the leakage current generated by the component. In the conventional technology, the bias level -VBB detected by the bias detection circuit 2 is mostly a function of the power supply VCC. In other words, the value of the bias level VBB changes with the change of the power supply VCC. Figures 3A and 3B show the bias pre-measurement circuits for the high bias level VH and the low voltage level VL, respectively. The two-phase series p-type MOS transistors ρ and 卩 2 and P11 and P1 2 can be regarded as the impedances of the high-bias level detection circuit and the low-bias level detection circuit, respectively. The terminals NA and NB are the connection points of p-type MOS transistors P1 and P2 and P11 and P12, respectively. The potentials obtained by the terminals να and NB pass through the P-type transistors P3 and N-type transistors M3 and P-type, respectively. Transistor P1 3 and N-type transistor N1 3 are composed of CMOS inverters and double-buffered inverters. [1 and I 2 and 111 and 11 2 respectively detect the output level (detected 1 eve 1 state) Vl and V2 . Figures 3A and 3B, Figure 4, and Figures 5A and 5B show the width / length ratio of the process transistor next to each transistor. Comparing Figures 3A and 3B, it can be observed that only the widths / lengths of the transistors p 2 and P 1 2 are different in the two circuits, and the other components have the same specifications and configurations. In fact, adjusting the width / length ratio of the transistor can change its impedance load. Take transistor P2 (width / length ratio is 4u / 1 232u) and transistor P12 (width / length ratio is 4u / 2688u) as an example. Because the gate length of transistor P2 is shorter than transistor P12, The impedance value is smaller than the transistor pi2. this
412846 五、發明說明（3) 時’由端點NA與NB所取得之分壓亦不相同。由圖中可觀察 出若同時供應相同偏壓位準VBB時，端點NA之分壓將會低 於端點NB之分壓。 因此’高偏壓位準VH與低偏壓位準VL之值可利用不同 的寬/長比之電晶體P 2與P1 2加以預設。 第4圖所示為振盪器驅動電路丨4之結構圖。當第3A與 第3B圖中所示之電路最終輸出偵測位準狀態V1與¥2後，偵 測位準狀態VI輸入圖中端點Ni 1與N12，且偵測位準狀態V2 輸入圖中端點N2 ^經此電路综合兩偵測位準狀態VI與V2後 判定是否致動或關閉電荷泵電路丨6，使基底偏壓位準始終 維持在高偏壓位準V Η與低偏壓位準v L之間。 然而’在前述高偏壓位準VH與低電壓位準VL之偏壓偵 測電路中’分別由端點“與〇所偵測之偏壓位準VBB結果 與電源電壓VCC存在極強之關連性。因為端點να與NB分壓 來源為電源電壓VCC與偏壓位準VBB之綜合電壓，電源電壓 vcc於其中佔有極大成分。換句話說’電源電壓vcc之變動 對端點NA與NB之偏壓偵測結果影響甚巨。此外，若電源電 壓越高’由於對端點NA與NB之偏壓會經由CMOS反開而輸 出’读測位準狀態V1與V2的轉換時機須延遲至偏壓位準 VBB更負時才會發生。此時’第2圖中原先所預定高偏壓位 準VH與低偏壓位準VL會朝更低偏壓位準移動，此舉將使p_ 基底與N型没極以及N型源極間產生更大的接面反向偏壓 (junction reverse bias)，對M0S電晶體操作造成負面的 影響。412846 V. Description of the invention (3) The partial pressure obtained by the endpoints NA and NB is also different. It can be observed from the figure that if the same bias level VBB is supplied at the same time, the divided voltage at the endpoint NA will be lower than the divided voltage at the endpoint NB. Therefore, the values of the 'high bias level VH and the low bias level VL can be preset using transistors P 2 and P 1 2 with different width / length ratios. Figure 4 shows the structure of the oscillator drive circuit. When the circuits shown in Figures 3A and 3B finally output the detection level states V1 and ¥ 2, the detection level state VI enters the endpoints Ni 1 and N12 in the figure, and the detection level state V2 enters the figure. Middle end point N2 ^ This circuit combines the two detection level states VI and V2 to determine whether to activate or close the charge pump circuit 丨 6, so that the base bias level is always maintained at a high bias level V Η and a low bias Pressure level between v L. However, 'in the aforementioned bias detection circuit of the high bias level VH and the low voltage level VL', the bias level VBB detected by the end point and 0 respectively has a strong correlation with the power supply voltage VCC Because the source of the divided voltage να and NB is the combined voltage of the power supply voltage VCC and the bias level VBB, the power supply voltage vcc occupies a very large component. In other words, the change of the power supply voltage vcc affects the endpoints NA and NB. The bias detection result has a huge impact. In addition, if the power supply voltage is higher, 'Because the bias to the terminals NA and NB will be output through CMOS inversely open,' the switching timing of the reading level states V1 and V2 must be delayed to the bias This occurs only when the level VBB is more negative. At this time, 'the original high bias level VH and low bias level VL that were previously scheduled in Figure 2 will move to a lower bias level, which will make the p_ basis and The larger junction reverse bias between the N-type pole and the N-type source causes a negative impact on the operation of the MOS transistor.
412846 發明說明（4) 伯制S，本發明之—目的，在於提供一種⑽S基底偏壓 φ " ，其利用—數個相串聯之負載電晶體連接於電源 =CC與偏壓偵測電路之間，將 得之參考位準中電壓電·c之成分降低^振^ ::電路與電荷栗電路最終達成之偏壓位準不致過低，· 減小接面反向偏壓的程度。 本發明提供一種基底偏壓偵測電路，用以 偏壓，包括一第一备恭·一筮-名并\ 暴底 負載，第一負载，v刀別耦接該第一負 載與該基底偏壓一第一反閘，具一輸入端耦接該 =與該第二負載之耦接處；—第二反閑與一第三反間該 第二反閉與該第三反閘申聯，其中該第二反閘之一 耦接該第一反閘之輸出端；以及一分壓電路，耦於 -負載與該電壓源間’纟中該分壓電路 電4 電壓至該第一負载。 為讓本發明之上述和其他目的、特徵、和 顯易懂，下文特舉一較佳實施例’ i配合所附1月b 細說明如下： 叫八’作坪 圖示之簡單說明： 第1圖係顯示一基底偏壓電路之方塊圖； 電路運作時偏壓位 準VH與低電壓位準 第2圖係顯示為第1圖中基底偏壓器 準VBB與時間T之關係圖； 第3A與3B圖係顯示分別為高偏壓位 VL之偏壓偵測電路； 第4圖係顯示所示為振盪器驅動電路 * <結構圖；以412846 Description of the invention (4) S, the purpose of the present invention is to provide a ⑽S substrate bias φ ", which uses several serial load transistors connected to the power source = CC and the bias detection circuit. In the meantime, the voltage reference · c component in the obtained reference level is reduced ^ Vibration ^ :: The bias level finally achieved by the circuit and the charge pump circuit is not too low, and the degree of reverse bias of the junction is reduced. The present invention provides a substrate bias detection circuit for biasing, including a first standby load, a first load, a first load, a first load, and a v-couple coupled to the first load and the substrate bias. Press a first reverse brake with an input terminal coupled to the coupling point of the = and the second load;-the second reverse idle and a third reverse between the second reverse closing and the third reverse brake, One of the second reverse gate is coupled to the output terminal of the first reverse gate; and a voltage dividing circuit is coupled between the load and the voltage source, and the voltage dividing circuit is electrically connected to the first voltage. load. In order to make the above and other objects, features, and comprehensibility of the present invention, a preferred embodiment is described below with a detailed description of the accompanying January b as follows: Called eight 'as a simple illustration of the ping diagram: Section 1 The figure shows a block diagram of a base bias circuit; the bias level VH and the low voltage level when the circuit is operating. Figure 2 shows the relationship between the base bias voltage VBB and time T in Figure 1; Figures 3A and 3B show the bias detection circuits for the high bias bit VL respectively; Figure 4 shows the oscillator drive circuit * < structure diagram;
412846 五、發明說明（5) 及 第5A與5B圖係分別顯示根據本發明實施例中高偏正 準VH與低電壓位準VL之偏壓偵測電路。 符號說明： - 1 〇〜基底；1 2〜偏壓偵測電路；丨4〜振盪器驅動電. 路’16〜電荷泵電路；VBB〜偏壓位準：VCC〜電壓源電 壓’PI-P14 'N3-N17〜電晶體；11-112〜反閘：以及D1、 D2〜分壓電路。 實施例·· 第5 A與第5 B圖係分別顯示根據本發明一實施例中高偏 壓位準VH與低電壓位準Vl之偏壓偵測電路。 第5A與第5B圖與第3A與3B圖所示之元件與功能相仿。 兩相串聯P型MOS電晶體P1與P2以及P11與P12可分別視為高 偏壓位準偵測電路與低偏壓位準偵測電路之阻抗。端點N A 與NB則分別為p型MOS電晶體P1與P2以及P11與P12之連接 點’由端點NA與NB所取得之電位分別經過p型電晶體P3與n 型電晶體N3以及P型電晶體P13與N型電晶體N13所組成CMOS 反閘’以及雙重緩衝反閘11與I 2以及111與11 2後分別輸出 偵測位準狀態VI與V2。 同樣地，比較第5A與第5B圖中可觀察出兩電路中僅電 晶體P2與P12之寬/長比不同’因在製程時調整電晶體之寬 /長比大小可改變其阻抗負載之大小。故電晶體P2(寬/長 比為4u/l 2 32u)之閘道製程長度小於電晶體P12(寬/長比為 4u/2688u)，電晶體P2之阻抗值小於電晶體P12。此時，由412846 V. Description of the Invention (5) and Figures 5A and 5B show the bias detection circuits of the high bias VH and the low voltage VL according to the embodiment of the present invention, respectively. Explanation of symbols:-1 〇 ~ substrate; 1 2 ~ bias detection circuit; 4 ~ oscillator drive circuit. '16 ~ charge pump circuit; VBB ~ bias level: VCC ~ voltage source voltage 'PI-P14 'N3-N17 ~ transistor; 11-112 ~ reverse brake: and D1, D2 ~ voltage divider circuit. Embodiments · Figures 5A and 5B show the bias detection circuits of the high bias voltage level VH and the low voltage level Vl, respectively, according to an embodiment of the present invention. The components and functions shown in Figures 5A and 5B and Figures 3A and 3B are similar. The two-phase series P-type MOS transistors P1 and P2 and P11 and P12 can be regarded as the impedances of the high bias level detection circuit and the low bias level detection circuit, respectively. Terminals NA and NB are the connection points of p-type MOS transistors P1 and P2 and P11 and P12, respectively. The potentials obtained by terminals NA and NB pass through p-type transistors P3 and n-type transistors N3 and P-type, respectively. The transistor P13 and the N-type transistor N13 are composed of a CMOS inverter and a double-buffered inverter 11 and I 2 and 111 and 11 2 to output detection level states VI and V2, respectively. Similarly, comparing Figures 5A and 5B, it can be observed that only the width / length ratio of the transistors P2 and P12 in the two circuits is different. Because the width / length ratio of the transistor can be adjusted during the process, the impedance load can be changed. . Therefore, the gate process length of transistor P2 (width / length ratio 4u / l 2 32u) is shorter than transistor P12 (width / length ratio 4u / 2688u), and the resistance value of transistor P2 is smaller than transistor P12. At this point, by
第8頁 五'發明說明（6) 端.點NA與NB所取得之分壓亦不相同。由圖中可觀察出若同 時供應相同偏壓位準VBB時，端點NA之分壓將會低於端點 NB之分壓。利用此兩電路之互異處分別構成高偏壓位準VH 與低電壓位準VL之偏壓偵測電路。 為達本發明所揭示之目的，亦即降低高/低偏壓位準 偵測電路所測得之參考位準中電壓電源vcc之成分，如第 5A與5^圖所示’耦接一分壓電路D1與D2於電晶體P1以及電 晶體P11與電源電壓VCC之間，其中此分壓電路供應部分該 電壓源電壓至電晶體P1與電晶體P2。 此分壓電路D1與D2其中任一包括兩類負載，一為電晶 體P4與P14所構成之上偏壓負載，以及電晶體“叫7與 N14-N17所構成之下偏壓負載。此時，原先在第3人與^圖 中端點A與β將不直接供應電壓源電壓vcc，而是經上偏壓 負載與下偏壓負載分化電壓源電壓VCC後之部分電壓。從 圖中可觀察出，電晶體Ρ4與Ρ14(寬/長比為4u/150u)之阻 抗於電晶體Ν4-Ν7與Ν14-Ν17(寬/長比為400u/1.6u)，故電 晶體P4與P14所構成之上偏壓負載阻抗大於電晶體N4_N7與 N14-N17所構成之下負載阻抗。換言之，因為端點a與β所 分得電壓與下負載阻抗成正比，故經由端點A與8供應至高 偏壓位準VH與低電壓位準VL之偏壓读測電路之電壓源電壓 VCC成分可被降低。 在實際運用上，設計者可依實際操作所需求之偏壓位 準幅度而調整下負載阻抗電晶體N4-N7與N14-N17之電晶體 個數。此外’調整下負載阻抗電晶體N4-N7與N14_Nn，以Page 8 Five 'invention description (6) Terminal. The partial pressure obtained by NA and NB is also different. It can be observed from the figure that if the same bias level VBB is supplied at the same time, the divided voltage at the endpoint NA will be lower than the divided voltage at the endpoint NB. The difference between these two circuits is used to form a bias detection circuit with a high bias level VH and a low voltage level VL, respectively. In order to achieve the purpose disclosed in the present invention, that is, to reduce the components of the voltage power supply vcc in the reference level measured by the high / low bias level detection circuit, as shown in Figs. 5A and 5 ^ The voltage circuits D1 and D2 are between the transistor P1 and the transistor P11 and the power voltage VCC. The voltage dividing circuit supplies part of the voltage source voltage to the transistor P1 and the transistor P2. This voltage-dividing circuit D1 and D2 includes two types of loads, one is an upper biased load composed of transistors P4 and P14, and the transistor is called a lower biased load composed of 7 and N14-N17. At the time, the terminals A and β in the third figure and the first figure will not directly supply the voltage source voltage vcc, but the partial voltage after dividing the voltage source voltage VCC by the upper bias load and the lower bias load. From the figure It can be observed that the resistance of transistors P4 and P14 (width / length ratio is 4u / 150u) is compared with that of transistors N4-N7 and N14-N17 (width / length ratio is 400u / 1.6u). The upper bias load impedance is greater than the lower load impedance formed by transistors N4_N7 and N14-N17. In other words, because the voltage divided by terminals a and β is proportional to the lower load impedance, it is supplied to high via terminals A and 8. The voltage source voltage VCC component of the bias reading and measuring circuit of the bias level VH and the low voltage level VL can be reduced. In practical application, the designer can adjust the load according to the bias level required by the actual operation. The number of transistors N4-N7 and N14-N17. In addition, the load impedance transistors N4-N7 and N14_Nn with
412846 五'發明說明（7) 及上負載阻抗電晶體P4與P1 4之寬/長比，亦可達到調整供 應至端點A與B之電壓源電壓VCC之成分比率。 根據本發明所揭示之實施例，利用本發明所提供之如 j 第5A與5B圖所示分壓電路D1與D2，即使電壓源電壓VCC大 | 幅提昇或降低’分別經由高偏壓位準VH與低電壓位準vl之 I 偏壓偵測電路中端點A與端點B所取得之電壓將不會隨電壓 源電壓VCC大幅變化’而基底與源極或汲極間亦減少接面 反相偏壓的程度，避免縮短電晶體使用壽命，並提升可操 作電晶體之電源範圍。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍内’當可作更動與潤飾’因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。412846 Five 'invention description (7) and the width / length ratio of the upper load impedance transistors P4 and P1 4 can also adjust the component ratio of the voltage source voltage VCC supplied to the terminals A and B. According to the embodiment disclosed by the present invention, the voltage dividing circuits D1 and D2 provided by the present invention as shown in FIGS. 5A and 5B are used, even if the voltage source voltage VCC is large | The voltages obtained by the terminal A and terminal B in the I-bias detection circuit of the quasi-VH and low-voltage level vl will not change greatly with the voltage source voltage VCC, and the connection between the substrate and the source or the drain is also reduced. The degree of reverse bias of the surface avoids shortening the service life of the transistor and increases the power range of the transistor. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can change and retouch without departing from the spirit and scope of the present invention'. Therefore, the present invention is protected. The scope shall be determined by the scope of the attached patent application.