TW412674B - Method and system for analyzing test coverage - Google Patents

Abstract

A method for determining test coverage of an original high level language description which represents an electrical circuit by the data of at least one dump file exported by a simulation program, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the data of the dump file consisting of the values of all the variables of the original high level language description between a simulation start time instant and a simulation end time instant the method comprising: a description importing step for importing the original high level language description to form a design database; a dump file importing step for importing the dump file; and a test coverage determining step for determining the test coverage of the original high level language description by the values of the variables at all the time instants from the simulation start time instant to the simulation end time instant.

Description

412674_ V. Description of the invention (1) Background of the invention The present invention relates generally to data processing systems, and particularly to the analysis of test coverage of a circuit when it accepts input data for a given complex array test. Methods and systems. Description of the conventional technique US Patent No. 5,604,895, discloses a method for inserting computer code into a high-level language software model of a circuit, and monitoring software when receiving test input Test coverage of the model. This method has the following disadvantages: it generates an augmented description code of the circuit to determine the test coverage rate, but the expanded description code will occupy more computer storage space; when the augmented description code is simulated by software or hardware tools , Which will generate a few extra files, which will also occupy more computer storage space; determining the test coverage rate in this way will result in the cost of using simulated software or hardware tools; and the use of simulated soft bones or hardware tools to determine the test coverage rate Is time consuming. In order to avoid the shortcomings of the prior art method used to analyze the test coverage of the high-level language model of the circuit when receiving test input, the inventor of the present case considered dumping the dump file generated by the simulation software or hardware tool [dump fi 1 e (s)] Used to analyze the test coverage rate when the software model accepts test inputs. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method and system for analyzing a test coverage rate when a software model accepts a test input, which does not generate any additional augmented description codes of the analysis circuit and does not generate any additional

-442674- Page 6 'Explanation of invention description (2). Another object of the present invention is to provide a method and system for analyzing a test coverage rate when a software model accepts a test input. When analyzing the test coverage rate, it is not necessary to use simulation software or hardware tools. Yet another object of the present invention is to provide a method and system for analyzing the test coverage rate of a software model when receiving test input. The time it takes to analyze the test coverage rate is much less than that consumed by the prior art method. . To achieve the foregoing and other objectives, the present invention provides a method for determining a test coverage rate of an original high-level language description code representing a circuit by using at least one dump file output by an analog program. The high-level description code has At least one executable specified statement is used as a model of the circuit. The left side and the right side of the at least one executable specified statement are separated by a specified operator, the left side is a variable, and the 'right side is an expression, which has at least one variable and at least A logical operator. The expression on the right determines the value of the variable to be assigned to the left when calculating. The data of the dump file contains the values of all variables in the original high-level language description code from the simulation start time to the simulation end time. The method includes: a description code import step to import the original high-level language description code as a database of circuit design; a dump file import step to import the dump file; and a test coverage rate decision Steps: use the values of all variables in the original high-level language description code at the moment between the start of the simulation and the end of the simulation to determine Test coverage of the original high-level language description code. Brief description of the drawings From the detailed description of the following preferred embodiments, and with reference to the following formulas, when the preferred embodiments of the present invention can be fully understood, reference is made to the following drawings in detail,

412674_ V. Description of the invention (3) The foregoing and other objects and effects of the present invention are illustrated: Figure 1 (a) shows a small section of Verilog program; Figure 1 (b) shows a small section of Verilog program shown in Figure 1 (a) Event model diagram; Figure 2 (a) shows a small segment of VHDL program; Figure 2 (b) shows the event model of a small segment of VHDL program shown in Figure 2 (a); Figure 3 (a) shows a small segment of Verilog program; Figure 3 (b) shows a model diagram of the statement tree of the Verilog program shown in Figure 3 (a); Figure 4 shows the tracking of signal changes; Figure 5 shows the procedure for determining executed statements; Figure 6 shows Steps of the preferred embodiment of the method of the present invention; Figure 7 shows the sub-steps of the test coverage determination step shown in Figure 6; Figure 8 (a) shows a finite state machine graph [finite state machine graph]; and 8 (b) shows an event model diagram corresponding to FIG. 8 (a). Label description 6 1 Description code import step 62 Event model map construction step 63 Sentence tree construction step 64 FSM information extraction step. 65 Dump file import step 66 Variable selection step

Page 8 412674 V. Description of the invention (4) 6 7 Test coverage determination step 7 1 Time schedule step 72 Affected conditional labeling step 73 Triggered event picking step 7 4 Sentence tree viewing step details of the preferred embodiment Description In a preferred embodiment of the present invention, both the event model diagram and the sentence tree model diagram are used to describe the original high-level language description code representing a circuit. An event model diagram is basically a directional model diagram [G (V, E)]. In this model, an event is defined as the largest unit that an HDL program will automatically execute during simulation. Each Always statement in a Verilog program or each Process statement in a VHDL program can generate an event model diagram. Each vertex in an event model diagram [vertex] veV represents an event in the HDL design. The executable code of each event is also related to a vertex. Each event can have several child nodes child (v), that is, child (v) is generated by the vertex v. For example, if you insert the code of event j into event i, you can use @, wait, or deferred statements in Verilog design, or use wait on / until / for in VHDL design, or deferred statements [after] The codes in these two events are separated. Regarding the triggering timing of these events, there is a hierarchical relationship between them. Each event model diagram has a candidate event [candidate event], which represents the current point to be triggered. If this event is triggered, the next-level event becomes a new candidate event of the event model diagram. Please refer to FIG. 1 (a) and FIG. 1 (b). According to the foregoing definition, in FIG. 1 (a)

412674 V. The Verilog program shown in the description of the invention (5) can be divided into five events, the relationship of which is established in the event model diagram shown in Figure 1 (b), and its arrow indicates the relationship between events. In the initial state, the trigger point of each event model diagram is on the root event. If the candidate event is triggered, the point to be triggered is moved to the next event. Each vertex of each event model diagram has two fields, where the upper field is the trigger condition of the event, and the lower field is the executable code of the event. In Figure 1 (b), El, E2, and E3 are root events and will be triggered first. El 1 and E21 are generated by E1 and E2, respectively. After E 2 is executed, E 2 1 is executed with a fixed delay time, so its trigger condition can be set to the absolute time it will be executed. This absolute time can be easily calculated from the current time. The same concept can be used to customize the event model diagram of a VHDL program, as shown in Figure 2 = The foregoing programs are quite simple, so the event model diagram can directly display the executable code of each event. In practical cases, the executable code for an event can be quite complex. Therefore, a statement tree can be used to preserve the complex behavior of each event. A sentence tree is a rooted and directional model graph, where the vertex set N has two kinds of vertices. A non-terminal vertex has one or more child vertices child (n) eN. A terminal vertex represents the terminal block in the HDL code and has no child vertices, but has a set of specified sentences recorded in a c t i ο η (η). The entry conditions for each endpoint are recorded in cond (n). Figure 3 (b) illustrates a sentence tree of Verilog code. Each sentence tree has two columns, where the upper block is the entry condition for the vertex cond (), and the lower block is a set of executable code action () for the vertex. From the event model diagram, you can easily know what code will be executed after an event is triggered. For example, in Figure 1 (b), after E 1 is triggered, L 6 will be executed

Page 10 412674_ 5. Explanation of the invention (6) and L7 sentence. In an HDL program, if you know the value of each variable at any time, you can know how many times each event has been triggered, and how many times each statement has been executed. 'Dump files are usually generated in simulation programs to track changes to selected variables in HDL programming. Therefore, if a dump file is read from the beginning, the value of each variable recorded in the dump file at any time can be obtained. This means that by properly selecting the variables, you can know the number of executions of each statement in this dump file. From this statistical data, you can easily calculate the test coverage. The test coverage rate dump analysis method (DUCA) is similar to the simulation method, but its complexity is extremely low. The reasons are as follows: First, the schedule calculation can be omitted in the test coverage ratio dump analysis method. This operation is the most time-consuming step in the simulation method, but it is an unnecessary step in the test coverage ratio dump analysis method. . The dump file clearly records when an event should be triggered, so only by following the order of the codes in the dump file, you can get the correct schedule. Furthermore, in test coverage dump analysis, many sentences can be skipped and only certain events and entry conditions need to be evaluated. Which code is executed is the key, but the value of each variable is irrelevant. Therefore, the result of the operation does not affect which code will be executed, and these operations will be ignored. Even if the calculation result is necessary to determine which codes are executed, the calculation results can be taken from the dump file. Therefore, among the calculations performed by the simulation program that generates dump files, only a few calculations need to be recalculated in the test coverage dump file analysis method, so the complexity of the calculation can be greatly reduced. As stated above, not all code is used to determine which code has been executed.

Page 11_412674_ V. Explanation of the invention (7) All information is necessary, so in order to improve the efficiency of the test coverage rate dump analysis method, it is advisable to analyze and find out the variables that affect the decision, that is, it is necessary to track these variables The change. In fact, these variables are variables that appear in the trigger condition of each vertex of each event model graph, or variables in the entry conditions of each vertex of the statement tree. This variable selection operation also provides the ability to analyze the coverage of some test codes. If the user is only concerned about the test coverage of a part of the entire code, then only the variables needed to track this part of the code need to be selected, which can further reduce the analysis time. If the user is only concerned about whether a certain sentence has been executed, then after a c t i ο η () is executed once, all evaluations of each condition can be ignored. This trick can save a lot of time when dumping out is quite large. After the variable selection step, you can begin to analyze coverage by tracking changes to these variables in the dump file. An example is shown in Figure 4 to illustrate the operation of coverage analysis more clearly. If a signal changes its value in the dump file, first find out the scope of the signal, that is, the range affected by the change, and then mark the relevant positions in the event model diagram and the sentence tree. If the affected code is a triggering condition in the event model diagram, mark it as T (triggered), and if the affected code is an entry condition in the statement tree, mark it as M (changed) These labels can help avoid unnecessary double counting in the following steps. After all signal changes at the same time, the statement tree of the triggered event can be traced to determine which codes have been executed. For each triggered event, the statement tree must be examined to determine which code has been executed, as shown in Figure 5. Looking down at the statement tree

Page 12 412674 V. In the description of the invention (8), if the current vertex has been changed, the entry condition value must be calculated again to decide which path to follow; otherwise, the previous calculation result can be used to avoid unnecessary calculation. It is not necessary to calculate the condition value for each vertex labeled M (changed) but not in the pursuit. The M (changed) mark of these vertices must be kept until it is finally located in Kao Lu Road # 中 A v 'In the above steps, after watching the dumping, ^^ // Which code has been executed and executed Statistics of times. However, there are many different coverage methods that require different coverage reports. Therefore, post-procedure steps can be added to generate the coverage test method selected by the user. 'Please refer to FIG. 6, which shows a method according to a preferred embodiment of the present invention. This method includes a description code import step 6 1 for importing the original high-level language = description code to form a circuit design database; Event model diagram building step 2 is used to view the circuit design database and find out the basic event units, 2 to build each event model diagram; a sentence tree building step 63 is used to build a sentence tree for each event unit; —FSM information extraction step 64, used to extract FSM information [including transfer and status information] from the 1-way design database, and send the transfer and status information to the statement tree; In and out files; a variable selection step 66 for selecting at least one event unit or all variables appearing in a sentence tree from all variables; and a test coverage determination step 67. As shown in FIG. 7, the coverage test determining step 67 includes a time scheduling step Ή, a sentence recognition step 72, a triggered event retrieval step 73, and a ^ tree inspection step 74. The time scheduling step 71 is used to monitor the time from the simulation start time to the simulation end time according to a predetermined time.

412674 V. Description of the invention (9) And for each of these moments, an iterative cycle is generated. Affected conditional labeling-showing step 72 is used to mark the conditional expression in each statement tree affected by the variable selected in the variable selection step 66. This effect is therefore to wait for the selected variable to Caused by a change in the value of the previous moment. The triggered event picking step 73 is used to pick up each event unit triggered by the selected variable in the variable selection step 66, and its trigger is therefore to wait for the selected variable at the time corresponding to the current iteration cycle and its previous time. Caused by change. The statement tree viewing step 74 is used to view the statement tree of a basic event unit to determine which condition or statement has been executed. Therefore, test coverage data can be obtained and written into a test coverage database. In other words, after analyzing the original high-level language description code with at least one executable specified sentence, an event model diagram and a sentence tree model diagram of the description code can be obtained. The variables to be tracked and their values are determined in the variable selection step. After completing all the preparations, you can start to look at the dump file to get the execution statistics. Once the time change is read out from the dump file, the statement tree of each triggered event is viewed in the correct execution order, and which statements are executed. In this way, it is possible to find out the code that has been executed between the last time change and the moment just after. The execution statistics will be kept in a code, such as Execution_Stats. After looking at each sentence tree, start to dump out files and read the signals that will change in the next period. Each signal change will update each event model diagram and the related mark of the statement tree t, so that the next time the change is made, the executed code can be correctly determined. Finally, a post processing subroutine is used to process the statistical results to generate the test coverage selected by the user.

Page 14 412674 V. Description of the invention (ίο) Rate report. The finite state machine test coverage rate (ie, the state and state transition test coverage rate) is an important test coverage test method to confirm the finite state machine. In fact, the event model diagram can be used as a model for a finite state machine. For example, the finite state machine shown in FIG. 8 (a) has three states and five state transition conditions, which can be represented by the event model diagram shown in FIG. 8 (b), which has three events, and each state Transition conditions are also associated with corresponding events. The test coverage rate dump analysis method can also be used to obtain such test coverage statistics. The slight difference is that for each event, it is necessary to evaluate which condition is true or false to determine which state transition condition has been executed when this event has been triggered. For FSM test coverage analysis, the variables to be tracked in the dump file need to be selected. If a finite state machine model has been ordered, a test coverage analysis procedure can be used to obtain the statistical results of the finite state machine test coverage. With the present invention, various test coverage rates can be obtained, such as: • Statement coverage rate: Reports whether each statement has been executed. • Fork coverage rate: Reports whether each tested Bollinger expression in the control structure has ever been counted as "true j" or "false". • Condition coverage rate: Report the true and false results of each Brinzi expression. When these results occur, they are separated by "logical AND" and "logical OR". • Multi-condition coverage: Reports whether each possible combination of each Bollinger expression occurs. • Path Coverage: Reports that every possible path in each function used to be an execution path.

Page 15 41267: _ V. Description of the invention (11) • Conversion coverage: Reports the logical bits that have been converted during the simulation. • Finite state machine coverage: as described in the previous paragraph. From the above description, a person of ordinary skill in the art can easily understand that the preferred embodiments of the present invention can achieve the various objects of the invention. The detailed description of the above preferred embodiments is only used to explain the technical content of the present invention, and the spirit and scope of the present invention should not be limited by it. Any changes made in accordance with the present invention are within the spirit and scope of the present invention patent application.

Page 16

Claims (1)

412674 6. Scope of patent application 1. — A method to determine the coverage rate of the original high-level language description code test by at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one The executable specified statement is used as a model of the circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. This expression has At least one variable consists of a group of variables and at least one logical operator. When calculating the expression on the right, a value will be determined to assign to the variable on the left. The data of the dump file is from the original higher order All variables in the language description code are composed of variable values between a simulation start time and a simulation end time. The method includes: a description code import step for importing the original high-level language description code to form a design Tribute storehouse, a dump file import step to import the dump file; and a test coverage determination step to borrow these variables to open the simulation The variable value between the start time and the end time of the simulation determines the test coverage rate of the original high-level language description code. 2. A method that determines the coverage rate of the original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group of variables composed of at least one variable. And at least one logical operator, when calculating the expression on the right side, a value will be determined to assign the variable on the left side, the data of the dump file is from the original height Page 17 412674 VI. All the variables in the patent description range language description code are composed of various variable values between a simulation start time and a simulation end time. The method includes: a description code import step for importing the The original high-level language description code to form a design database; an event model map building step to look at the design database and find out the basic event units to build one or more event model maps; A file import step for importing the dump file; and a test coverage determination step including monitoring each time that changes in a predetermined time increment from the simulation start time to the simulation end time; for each At these moments, an iterative cycle is generated; and by using the one or more event model diagrams, the sentences affected by the variables whose value has changed between the moment corresponding to the cycle and the previous moment are determined. 3. — A method to determine the coverage rate of the original high-level language description code test by using at least one dump file data output by a simulation program. This original high-level language description code represents a circuit and has at least one executable specified statement as The model of the circuit. The at least one executable specified sentence is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a first order consisting of at least one variable. Variables and at least one logical operator. When calculating the expression on the right, a value will be determined to be assigned to the variable on the left. The data of the dump file is determined by all the variables in the original high-level language description code. A simulation start time and a simulation end time are composed of variable values, and the method includes: a description code import step for importing the original high-level language description mark to form a design database; Page 18 412674 VI. Patent application scope-An event model diagram construction step is used to look at the design database and find out the basic event units to build one or more event model diagrams. A sentence tree construction step uses To build one or more statement trees of these basic event units; a dump file import step to import the dump file; and a test coverage determination step including monitoring from the moment the simulation is started to the At the end of the simulation, the moments that change by a predetermined time increment; for each such moment, an iterative cycle is generated; and the one or more event model diagrams or the one or more statement trees are used to determine Between the time corresponding to the cycle and its previous time, each sentence affected by each variable whose value has changed. 4. A method that determines the coverage rate of the original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has one of at least one variable. A set of variables and at least one logical operator. When calculating the expression on the right, a value will be determined to assign to the variable on the left. The data of the dump file is all in the original high-level language description code. The variables are composed of various variable values between a simulation start time and a simulation end time. The method includes:-a description of the importing step for importing the original high-level language description code to form a design database; an event; Model diagram building steps to view the design database, and Page 19 412674 6. Application scope: Find out the basic event units to build one or more event model diagrams;-sentence tree construction step to build one or more sentence trees of these basic event units; A dump file import step for importing the dump file; a variable selection step for selecting from all of these variables at least one event unit that will trigger the event units, or appear in the statements Each variable in at least one sentence tree in the tree; and a test coverage determination step including monitoring each time that changes in a predetermined time increment from the simulation start time to the simulation end time; for each such Time, an iterative loop is generated; and by the one or more event model diagrams or the one or more statement trees, it is determined that between the time corresponding to the loop and the previous time, it is selected by the variable selection step Each of the sentences whose variable value has changed has been affected. 5. — A method to determine the coverage rate of the original high-level language description code test by using at least one dump slot data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as The model of the circuit. The at least one executable designation statement is divided into a left side and a right side by a designation operator. The left side is a variable and the right side is an expression. The expression has at least one variable. A set of variables and at least one logical operator. When calculating the expression on the right side, a value is determined to be assigned to the variable on the left side. The data of the dump file is all in the original high-level language description code. The variable is composed of various variable values between a simulation start time and a simulation end time. The method includes: a description code import step for importing the original high-level language description Page 20 412674 VI. Patent application scope code to form a design database; an event model diagram construction step to look at the design database and find out the basic event units to build one or more event models Figure; a sentence tree construction step to construct one or more sentence trees of these basic event units; a FSM information extraction step to extract FSM information including transition and status information from the design database, and Transition and status information is attached to the one or more statement trees; a dump slot import step to import the dump gift; and a test coverage determination step, including monitoring from the moment the simulation starts to the time At the end of the simulation, the moments that change by a predetermined time increment; for each such moment, an iterative cycle is generated; and by the one or more event models or the one or more statement trees, the decision is made Between the time corresponding to the cycle and its previous time, the sentences and FSM coverage rates affected by the variables whose variable values have changed. 6. A method that determines the coverage rate of the original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group consisting of at least one variable. Variables and at least one logical operator. When calculating the expression on the right, a value will be determined to assign to the variable on the left. The data of the dump file is all in the original high-level language description code. Variables at the beginning of a simulation and the end of a simulation Page 21 412674 6. The value of each variable in the patent application range at the time, the method includes: a description code import step for importing the original high-level language description code to form a design database; an event model A graph construction step for viewing the design database and identifying each basic event unit to construct one or more event model diagrams; a statement tree construction step for constructing one or more of these basic event units A statement tree; a FSM information extraction step for extracting FSM information including transition and status information from the design database, and attaching the transition and status information to the one or more statement trees; a dump file An import step for importing the dump file; a variable selection step for selecting at least one event unit from all of the variables that will trigger the event unit t, or at least one appearing in the statement tree Each variable in a sentence tree; and a test coverage determination step, including monitoring from the simulation start time to the simulation end time, according to a predetermined time Each time of the quantity change; for each such time, an iterative cycle is generated; and the one or more event model diagrams or the one or more statement trees are used to determine the time corresponding to the cycle and the previous one At the moment, each sentence and FSM coverage rate affected by those whose variable values have changed among the variables selected in the variable selection step. 7. A system that uses the data of at least one dump file output by a simulation program to determine the coverage rate of the original high-level language description code test. This original high-level language description code represents a circuit and has at least one executable specified statement. Page 22 412674 6. The scope of the patent application is used as a model of the circuit. This at least one executable designation statement is divided into a left side and a right side by a designated operator. The formula has a set of variables consisting of at least one variable and at least one logical operator. When calculating the expression on the right side, a value will be determined to assign to the variable on the left side. The data of the dump file is determined by All variables in the original high-level language description code are composed of variable values between a simulation start time and a simulation end time. The system includes: a description code import device for importing the original high-level language description code, and Forming a design database; a dump file import device for importing the dump file; and a test coverage determination device for borrowing variables from each of the simulation start time and the simulation end time The variable value determines the test coverage of the original high-level language description code. 8. A system that determines the coverage rate of an original high-level language description code test by at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group consisting of at least one variable. Variables and at least one logical operator. When calculating the expression on the right side, a value will be determined to assign to the variable on the left side. The data of the dump file is all the variables in the original high-level language description code. The system consists of variable values between a simulation start time and a simulation end time. The system includes: a description code import device for importing the original high-level language description Page 23 412674 6. Apply for a patent scope code to form a design database; An event model diagram construction device is used to view the design database and find out the basic event units to build one or more event models Figure; a dump file import device for importing the dump file: and a test coverage rate determination device, whose role includes monitoring the change from the start time of the simulation to the end time of the simulation by a predetermined time increment Each time; for each such time, an iterative cycle is generated; and using the one or more event model diagrams to determine the variables whose variable values have changed between the time corresponding to the cycle and the previous time The sentences affected. 9. A system that determines the coverage rate of an original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a set of variables consisting of at least one variable and At least one logical operator, when calculating the expression on the right side, will determine a value to be assigned to the variable on the left side, and the data of the dump file is composed of all the variables in the original high-level language description code. The system includes: a description code import device for importing the original high-level language description code to form a design database; and an event model diagram construction. A device for viewing the design database and finding each basic event unit to construct one or more event model diagrams; a sentence tree construction Device to build one of these basic event units 412674 VI. Patent application scope of one or more sentence trees;-a dump file import device for importing the dump file; and a test coverage determination device, whose role includes monitoring from the moment the simulation starts to At the end of the simulation, the moments that change by a predetermined time increment; for each such moment, an iterative cycle is generated; and by borrowing the one or more event model diagrams or the one or more statement trees, Decide between the time corresponding to the cycle and the previous time, the sentences affected by the variables whose values have changed-variables. ίο. —A system that determines the coverage rate of the original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified sentence as The model of the circuit. The at least one executable designation statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group consisting of at least one variable. Variables and at least one logical operator. When calculating the expression on the right, a value will be determined to be assigned to the variable on the left. The data of the dump file is determined by all the variables in the original high-level language description code. A simulation start time and a simulation end time are composed of various variable values, the system includes:-description code import device, used to import the original high-level language description Ma to form a design database; an event model diagram A construction device for inspecting the design database and identifying basic event units to construct one or more event model diagrams; a sentence tree structure Building means for building one or more sentence trees of these basic event units; Page 25 412674 VI. Patent application scope-a dump file import device for importing the dump file; a variable selection device for selecting from all these variables which will trigger at least one of the event units Event units, or variables that appear in at least one of the sentence trees in the sentence trees; and-the test coverage determination device, whose role includes monitoring from the simulation start time to the simulation end time, increasing by a predetermined time The time of the quantity change; for each such time, an iterative cycle is generated; and by the one or more event model diagrams or the one or more statement trees, the time corresponding to the cycle is decided with the previous one In time, each sentence affected by the variable whose value has been changed among the variables selected in the variable selection device. π. A system that uses at least one dump file data output by a simulation program to determine the coverage rate of the original high-level language description code test. This original high-level language description code represents a circuit and has at least one executable specified statement as The model of the circuit. The at least one executable designation statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group consisting of at least one variable. Variables and at least one logical operator. When calculating the expression on the right side, a value will be determined to assign to the variable on the left side. The data of the dump file is all the variables in the original high-level language description code. The system consists of variable values between a simulation start time and a simulation end time. The system includes: a description code importing device for importing the original high-level language description code to form a design database; an event model A graph constructing device for viewing the design database and finding each basic event unit to construct one or more event model diagrams; Page 26 412674 VI. Patent application scope-a sentence tree construction device for constructing one or more sentence trees of these basic event units; a FSM information extraction device for extracting from the design database including transitions and states FSM information, and transfer and status information to the one or more statement trees; a dump file import device for importing the dump file; and a test coverage determination device, its role Including monitoring the moments that change by a predetermined time increment from the simulation start time to the simulation end time; for each such time, an iterative cycle is generated; and borrowing the one or more event model diagrams or the One or more statement trees that determine the coverage of each statement and FSM affected by each variable whose value has changed between the time corresponding to the cycle and its previous time. 12. A system that determines the coverage rate of an original high-level language description code test by using at least one dump file data output by a simulation program. The original high-level language description code represents a circuit and has at least one executable specified statement as the A model of a circuit. The at least one executable specified statement is divided into a left side and a right side by a specified operator. The left side is a variable and the right side is an expression. The expression has a group of variables composed of at least one variable. And at least one logical operator, when calculating the expression on the right, a value will be determined to assign to the variable on the left. The data of the dump file is determined by all the variables in the original high-level language description code. A simulation start time and a simulation end time are composed of variable values. The system includes: a description code importing device for importing the original high-level language description code to form a design database; Page 27 6'Applied patent-an event model diagram constructing device to view the design database and find out the basic event units to construct one or more event model diagrams; a sentence tree constructing device to construct One or more statement trees of the basic event units; an FSM information extraction device for extracting FSM information including transition and status information from the design database, and attaching the transition and status information to the one or more A statement tree; a dump file import device to import the dump file; a variable selection device to select from all of these variables at least one event unit that will trigger the event units, or Variables that appear in at least one of the sentence trees in the sentence trees; and a test coverage determination device, whose role includes monitoring each of the changes in a predetermined time increment from the simulation start time to the simulation end time Moments; for each such moment, an iterative loop is generated; and borrowing the one or more event model diagrams or the one or more statement trees, decide on Corresponding to the cycle time between the moment of its front, by the impact of each sentence in each of the selected variable means whose variable values have been changed by the F S Μ coverage for this variable selection. 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