B7 41159 使 —I ,, _· 五、發明說明（丨) 本發明是有關於一種分離式閘極快閃記憶體之結構及 其製造方法，且特別是有關於一種低抹除電壓、高抹除速 度之分離式閘極快閃記憶體。 習知的可抹除可程式唯讀記憶體（Erasable Programmable Read-Only Memory ; EPROM)，其結構大致 上與N型的金氧半電晶體（Metal-Oxide-Semiconductor; MOS)相似。其中，閘極的結構爲堆疊閘極（stacked gate)的 型式，分爲以多晶矽（poly-silicon)所製作用來儲存電荷的 浮置閘（floating gate)，以及用來控制資料存取的控制閘 (control gate)。因此，一般EPROM單元都有兩個閘極， 浮置閘位於控制閘下方，其中，控制閘與字元線(worcHine) 相接，而浮置閘則處於”浮置”的狀態，沒有和任何線路相 連接。而目前流行一種由Intel公司所發展的”快閃記憶 體”，其可以進行”一塊一塊”(bl〇ck by block)方式的記憶淸 除(erase)工作，其速度非常的快，約1到2秒之間即可完 成記憶淸除工作，大量節省時間與製造上的成本。 請參照第1圖，其所繪示的是習知一種快閃記憶體之 電路佈局不意圖。快閑記憶體陣列（memory array)的局部 結構，其中’每一列的每個快閃記憶體之控制閘均電性連 接至同一條字元線，例如快閃記憶體10的控制閘G連接 到字元線WL2，而字元線WL1則串連另一列快閃記憶體 之控制閘。至於每一行的每個快閃記憶體，其源極會電性 連接至同一條位元線，例如，快閃記憶體1〇的源極S電 性連接至一位元線BL1。同樣的，每個快閃記憶體之汲極 3 ------------ IE------】--訂----------線 ' '1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS>A4規格（2〗〇χ 297公楚） 經濟部智慧財產局員工消費合作社印製 _pinw_π：_ 五、發明說明（、） 亦電性連接至另一條位元線，例如快閃記憶體10的汲極 D會連接至另一位元線BL2，此處源極與汲極所連接的位 元線不同。通常位元線BL1、位元線BL2與位元線BL3 會平行分佈’與字元線WL1與WL2等垂直分佈，共同組 成一快閃記憶體陣列。 接著，請參照第2圖，其所繪示的是習知一種快閃記 億體之剖面示意圖。其中，在半導體基底20上，設有薄 的穿隧氧化層22(tunneling oxide)。在穿隧氧化層22上有 浮置閘24，其材料例如爲多晶矽。在浮置閘24上有介電 層26 ’其材料例如爲氧化層/氮化矽層/氧化層 (Oxide/Nitride/Oxide ; 0N0)。以及在介電層26上有控制 閘28 ’其外接閘極電源G，控制閘28的材料例如爲多晶 石夕。此外’在控制鬧28與浮置閘24兩側的半導體基底2〇 中，還有摻雜區的結構，包括源極30b與汲極30a，源極 30b外接源極電壓S，而汲極30a外接汲極電壓d。其中， 在汲極30a與浮置聞24之間有一間隔距離，也就是說， 在源極3〇b與汲極30a之間的通道區域32(channel)，有部 分的通道區域32上方未覆蓋有浮置閘24，而是覆蓋控制 閘2S，此種控制閘28與浮置閘24分置在通道區域32上 方的結構’稱爲分離閘極（split gate)的結構^此種分離閘 極結構可以更加強快閃記憶體的操作速度。 習知分離式閘極快閃記憶體操作時，當進行編程動作 (program) ’係將源極電壓S給予高電位，鬧極電壓g亦 爲高電位，而汲極電壓D處於低電位，利用通道熱載子射 4 (請先閱讀背面之注意事項再填冩本頁) 裝------^--訂--------線. 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（A ) 入原理（Channel Hot Electron Injection, CHEI) ’ 使得汲極 3〇a之熱電子射入浮置閘24中。而當進行抹除動作(erase) 時，則是讓隧穿效應(tunneling effect)發生於浮置閘24與 控制閘28間，讓浮置閘24之電子射入控制閘28中。將 閘極電壓給予高電位，而源極電壓S與汲極電壓D均爲〇， 利用富勒-諾得海隧穿效應(Fowler-Nordheim Effect) ’使陷 於浮置閘24之電子射入控制閘28中。爲了降低抹除電壓 及提高抹除速度，一般會在浮置閘24形成尖端34(tip)。 習知形成尖端34的方法係利用區域氧化法（Local Oxidation, LOCOS)，在浮置閘34上形成一氧化層36，由於鳥嘴現象 (bird’s beak)，而形成尖端 34。 縱然在浮置閘形成尖端可以改善抹除電壓及抹除速 度，然而因爲習知係採用區域氧化法，又因爲濕式氧化法 的特性，若製程線寬需縮減以提高積集度時，則此層氧化 層之形成將限制產品線寬的縮減量。而利闬濕式氧化法所 形成之尖端，其尖銳度有限，可改善抹除電壓及抹除速度 之程度有限。此外，區域氧化法中的熱製程會使得後續製 程之熱預算降低，因而縮小製程裕度(process window)。 因此本發明的觀點之一就是在提供另一種分離式閘極 快閃記憶體，可使其浮置閘具有更尖銳之尖端，進而降低 抹除電壓，及提高抹除速度6 本發明的另一觀點在於提出一種形成上述分離式閘極 快閃記憶體的製造方法’利用間隙壁及平坦化的方法形成 浮置閘的尖端，利於縮減線寬，並增加熱預算。 5 -------------^--------J^T--------- (請先閱讀背面之注意事項再填冩本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4694twf.doc/008 _4iiaaa_si_ 五、發明說明（a) 本發明的再一觀點在於提出一種分離式閘極快閃記憶 體的製造方法，利用具有斜度之間隙壁使得浮置閘下方基 底中，形成一倒三角形的摻雜區域（delta doping)，可以使 位元線電容値降低，並可以有效阻止編程動作時，因源極 之高電壓而導致源極與汲極間產生擊穿現象(pimchthrough) 而無法編程。 爲達成本發明之上述和其他觀點，提出一種分離式閘 極快閃記憶體的製造方法，包括：首先在一半導體基底上 形成一第一絕緣區塊及一第二絕緣區塊。接著，在第一絕 緣區塊與第二絕緣區塊鄰近的側面形成一間隙壁。進行一 第一摻雜步驟，在第一絕緣區塊與第二絕緣區塊之間的半 導體基底中形成一倒三角形摻雜區域然後，形成一穿隧 氧化層，於第一絕緣區塊與第二絕緣區塊間的基底表面。 形成一第一多晶矽層於半導體基底上；並去除部分第一多 晶矽層，暴露出第一絕緣區塊及第二絕緣區塊，以形成一 浮置閘於第一絕緣區塊與第二絕緣區塊之間。其中浮置閘 呈一漏斗型，其具有一下表面與一上表面，而上表面之截 面積大於下表面之截面積，且上表面之周緣呈一環狀尖 端。去除第一絕緣區塊及第一絕緣區塊側面之間隙壁，至 少暴露出浮置閘之部分側面及部分半導體基底。接著， 形成一共形之氧化層，至少覆蓋浮置閘之上表面及其暴露 出之部分側面，以及暴露之半導體基底表面。形成一第二 多晶矽層於氧化層上，定義第二多晶矽層及氧化層，以形 成一控制閘，其中控制閘至少覆蓋浮置閘之部分上表面和 6 (請先閱讀背面之泛意事項再填寫本頁) 裝--------訂---------線t 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（女） 部分側面，以及浮置閘鄰近之半導體基底表面。去除第二 絕緣區塊；並進行一第二摻雜步驟，形成二源極/汲極區 域於半導體基底中，源極/汲極區域其中之一位於浮置閘 遠離控制閘之一側，另一源極/汲極區域則位於控制閘遠 離浮置閘之一側。 藉由上述之製造方法，本發明亦提出一種分離式閘極 快閃記憶體，建構於一半導體基底上，至少包括：一通道 區域、一浮置閘、一控制閘，一介電層及二源極/汲極區 域。其中，通道區域係位於半導體基底表面。浮置閘配置 於部分通道區域上，且浮置閘與半導體基底之間具有一穿 隧氧化層。浮置閘呈一漏斗型，浮置閘具有鄰近半導體基 底之一下表面與遠離半導體基底之一上表面，其中上表面 之截面積大於下表面之截面積，且上表面之周緣呈一環狀 尖端。介電層配置於浮置閘的部分上表面與側面，以及未 被浮置閘覆蓋之通道區域表面。控制閘配置於介電層上， 包括浮置閘的部分上表面與側面，以及未被浮置閘覆蓋之 通道區域表面。二源極/汲極區域則分別配置於通道區域 之二側。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖所繪示的是習知一種快閃記憶體之電路佈局示 意圖。 7 --------I---褒·--------訂·--------' ί (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇χ297公釐） 經濟部智慧財產局員工消費合作社印製 j|^S3〇c/〇08 Λ/ ^ _Β7_ 五、發明說明（匕） 第2圖所繪不的是習知一種快閃記憶體之剖面示意 圖。 第3Α圖至第Ή圖繪示依照本發明一較佳實施例的一 種分離式閘極快閃記憶體製程的流程剖面示意圖。 圖式之標示說明： 10 :快閃記憶體 WL1 ' WL2 :字元線 BL1、BL2、BL3 :位元線 G :控制閘 S :源極(源極電壓） D :汲極（汲極電壓） 20、50 :半導體基底 22 :穿隧氧化層 24、64a :浮置閘 26 :介電層 28、74a :控制閘 3〇a :汲極 30b :源極 32 :通道區域 34 :尖端 36 :氧化層 ------------襄--------訂·-------線 1 (請先閱讀背面之注意事項再填寫本頁) 本紙張&度適用中國國家標準（CNS)A4規格（210x 297公釐） 經濟郎智慧財產局員工消費合作社印製 抑 B "_B7_ 五、發明說明（")） 52、54 :絕緣層 56a :第一絕緣區塊 56b :第二絕緣區塊 58 :間隙壁 60 :摻雜區 62 :穿隧氧化層 64 :第一多晶砂層 66a ：下表面 66b :上表面 66c :側面 68 :環狀尖端 70 :光阻層 72、72a :介電層 74 :第二多晶矽層 76 ' 78 :源極/汲極區域 76a、76b、78a ' 78b :摻雜輪廓 80 :通道區域 實施例 請參照第3A圖至第31圖，其繪示依照本發明一較佳 實施例的一種分離式閘極快閃記憶體製程的流程剖面示意 圖。首先請參照第3A圖，在一半導體基底50上形成第一 絕緣區塊56a與第二絕緣區塊56b，其中第一絕緣區瑰56a 及第二絕緣區塊56b係由二絕緣層52、54所組成。絕緣 層52之材質比如是氮化矽，而絕緣層54之材質比如是氧 9 (請先閱讀背面之注意事項再填寫本頁) 哀.-----^--訂.---- 線 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 411鶴B7 41159 ——I ,, _ · V. Description of the Invention (丨) The present invention relates to a structure of a separate gate flash memory and a method for manufacturing the same, and particularly to a low erasing voltage and high erasing voltage. In addition to speed, separate gate flash memory. The conventional Erasable Programmable Read-Only Memory (EPROM) has a structure similar to that of an N-type Metal-Oxide-Semiconductor (MOS). Among them, the structure of the gate is a type of stacked gate, which is divided into a floating gate made of poly-silicon to store charge and a control for controlling data access Gate (control gate). Therefore, general EPROM units have two gates. The floating gate is located below the control gate. Among them, the control gate is connected to the word line (worcHine), and the floating gate is in a "floating" state. The lines are connected. At present, a kind of "flash memory" developed by Intel is popular, which can perform a memory erasure work in a "bloc by block" manner. Its speed is very fast, about 1 to Memory erasure can be completed in 2 seconds, saving a lot of time and manufacturing costs. Please refer to FIG. 1, which shows a circuit layout of a conventional flash memory. A local structure of a fast memory array, in which the control gates of each flash memory in each column are electrically connected to the same word line, for example, the control gate G of the flash memory 10 is connected to The character line WL2 and the character line WL1 are connected to the control gates of another flash memory in series. As for each flash memory in each row, its source is electrically connected to the same bit line, for example, the source S of the flash memory 10 is electrically connected to a bit line BL1. Similarly, the drain of each flash memory 3 ------------ IE ------]-Order ---------- line '' 1 (Please read the precautions on the back before filling out this page) The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese national standards (CNS > A4 specifications (2) 0 × 297). Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative _pinw_π: _ V. Description of the invention (,) is also electrically connected to another bit line, for example, the drain D of the flash memory 10 is connected to another bit line BL2, where the source It is different from the bit line connected to the drain. Usually, the bit line BL1, the bit line BL2 and the bit line BL3 are distributed in parallel with the word lines WL1 and WL2, and form a flash memory array. Next, please refer to FIG. 2, which shows a schematic cross-sectional view of a conventional flash memory 100 million body. Among them, a thin tunneling oxide layer 22 (tunneling oxide) is provided on the semiconductor substrate 20. A floating gate 24 is formed on the oxide layer 22, and the material is, for example, polycrystalline silicon. A dielectric layer 26 'is formed on the floating gate 24, and the material is, for example, an oxide layer / nitride. Layer / oxide layer (Oxide / Nitride / Oxide; 0N0). And on the dielectric layer 26 is a control gate 28 'its external gate power source G, and the material of the control gate 28 is, for example, polycrystalline silicon. In addition, The semiconductor substrate 20 on both sides of the 28 and the floating gate 24 also has a structure of a doped region, including a source 30b and a drain 30a, the source 30b is connected to the source voltage S, and the drain 30a is connected to the drain voltage d There is a separation distance between the drain electrode 30a and the floating electrode 24, that is, in the channel region 32 (channel) between the source electrode 30b and the drain electrode 30a, a part of the channel region 32 is not above the channel region 32. Covered with the floating gate 24, but covering the control gate 2S. The structure where the control gate 28 and the floating gate 24 are separated above the channel area 32 is called a structure of a split gate. The pole structure can further enhance the operating speed of the flash memory. When the discrete gate flash memory is operated, when the program action (program) is performed, the source voltage S is given a high potential, and the alarm voltage g is also High potential and drain voltage D at low potential, shoot 4 with channel hot carrier (please read the back first Note for refilling this page) Install ------ ^-Order -------- line. This paper size applies to China National Standard (CNS) A4 (210x297 mm) Intellectual Property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau A7 B7 V. Description of the Invention (A) Channel Hot Electron Injection (CHEI) 'Thermal electrons of the drain electrode 30a are injected into the floating gate 24. When erasing, the tunneling effect occurs between the floating gate 24 and the control gate 28, and the electrons of the floating gate 24 are injected into the control gate 28. The gate voltage is given a high potential, and the source voltage S and the drain voltage D are both 0. The Fowler-Nordheim Effect is used to control the electron injection trapped in the floating gate 24 Gate 28. In order to reduce the erasing voltage and increase the erasing speed, a tip 34 is generally formed in the floating gate 24. A conventional method for forming the tip 34 is to use a local oxidation (LOCOS) method to form an oxide layer 36 on the floating gate 34. The tip 34 is formed due to a bird's beak. Although the formation of the tip at the floating gate can improve the erasing voltage and erasing speed, because the conventional system adopts the area oxidation method and the characteristics of the wet oxidation method, if the process line width needs to be reduced to increase the accumulation degree, The formation of this oxide layer will limit the reduction in product line width. However, the sharpness of the tip formed by the wet oxidation method is limited, and the extent of improving the erasing voltage and erasing speed is limited. In addition, the thermal process in the area oxidation method will reduce the thermal budget of subsequent processes, thereby reducing the process window. Therefore, one of the viewpoints of the present invention is to provide another kind of separate gate flash memory, which can make the floating gate have a sharper tip, thereby reducing the erasing voltage and increasing the erasing speed. The idea is to propose a manufacturing method for forming the above-mentioned separated gate flash memory, which uses a partition wall and a flattening method to form the tip of the floating gate, which is beneficial to reduce the line width and increase the thermal budget. 5 ------------- ^ -------- J ^ T --------- (Please read the notes on the back before filling out this page) The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4694twf.doc / 008 _4iiaaa_si_ 5. Description of the invention The manufacturing method of a separate gate flash memory uses an inclined gap wall to form an inverted triangle doped region (delta doping) in the substrate below the floating gate, which can reduce the bit line capacitance 値, and When the programming operation can be effectively prevented, the source and the drain have a pimchthrough caused by the high voltage of the source, which prevents programming. In order to achieve the above and other aspects of the present invention, a method for manufacturing a separate gate flash memory is provided, which includes: first forming a first insulating block and a second insulating block on a semiconductor substrate. Then, a gap wall is formed on the side adjacent to the first insulating block and the second insulating block. A first doping step is performed to form an inverted triangular doped region in the semiconductor substrate between the first insulating block and the second insulating block. Then, a tunnel oxide layer is formed between the first insulating block and the first insulating block. The surface of the substrate between two insulating blocks. Forming a first polycrystalline silicon layer on a semiconductor substrate; and removing a portion of the first polycrystalline silicon layer, exposing the first insulating block and the second insulating block to form a floating gate on the first insulating block and Between the second insulation blocks. The floating gate has a funnel shape, which has a lower surface and an upper surface, and the cross-sectional area of the upper surface is larger than the cross-sectional area of the lower surface, and the peripheral edge of the upper surface has an annular pointed end. The gap between the first insulating block and the side of the first insulating block is removed, at least part of the side of the floating gate and part of the semiconductor substrate are exposed. Next, a conformal oxide layer is formed, covering at least the upper surface of the floating gate and its exposed side surfaces, and the exposed semiconductor substrate surface. Form a second polycrystalline silicon layer on the oxide layer, define the second polycrystalline silicon layer and the oxide layer to form a control gate, where the control gate covers at least part of the upper surface of the floating gate and 6 (please read the back Please fill in this page for general Italian matters) Loading -------- Order --------- line t This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (female) part of the side, and the surface of the semiconductor substrate adjacent to the floating gate. Removing the second insulating block; and performing a second doping step to form two source / drain regions in the semiconductor substrate, one of the source / drain regions is located on one side of the floating gate away from the control gate, and the other A source / drain region is located on one side of the control gate away from the floating gate. By the above manufacturing method, the present invention also proposes a separate gate flash memory, which is constructed on a semiconductor substrate and includes at least: a channel region, a floating gate, a control gate, a dielectric layer and two Source / drain region. The channel region is located on the surface of the semiconductor substrate. The floating gate is disposed on a part of the channel region, and a tunnel oxide layer is provided between the floating gate and the semiconductor substrate. The floating gate has a funnel shape. The floating gate has a lower surface adjacent to a semiconductor substrate and an upper surface remote from the semiconductor substrate. A cross-sectional area of the upper surface is larger than a cross-sectional area of the lower surface. . The dielectric layer is disposed on the upper surface and sides of the floating gate, and on the surface of the channel region not covered by the floating gate. The control gate is disposed on the dielectric layer, and includes a part of the upper surface and sides of the floating gate, and the surface of the channel area not covered by the floating gate. The two source / drain regions are respectively disposed on two sides of the channel region. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 What is shown is a schematic circuit layout of a conventional flash memory. 7 -------- I --- 褒 · -------- Order · -------- 'ί (Please read the notes on the back before filling this page) This paper Standards are applicable to China National Standard (CNS) A4 specifications (2〗 〇χ297mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs j | ^ S3〇c / 〇08 Λ / ^ B7_ V. Description of the Invention (Dagger) 2 What is not shown in the figure is a schematic cross-sectional view of a conventional flash memory. 3A to 3D are schematic flow cross-sectional views of a separate gate flash memory system process according to a preferred embodiment of the present invention. Description of the diagram: 10: Flash memory WL1 'WL2: Word line BL1, BL2, BL3: Bit line G: Control gate S: Source (source voltage) D: Drain (source voltage) 20, 50: Semiconductor substrate 22: Tunneling oxide layer 24, 64a: Floating gate 26: Dielectric layer 28, 74a: Control gate 30a: Drain 30b: Source 32: Channel region 34: Tip 36: Oxidation Layer ------------ Xiang -------- Order · ------- Line 1 (Please read the notes on the back before filling this page) This paper & Applicable to China National Standard (CNS) A4 specification (210x 297 mm) Printed by Economic Consumer Intellectual Property Bureau Employee Consumer Cooperative Co., Ltd. B " _B7_ V. Invention Description 52, 54: Insulation layer 56a: First Insulation block 56b: Second insulation block 58: Spacer wall 60: Doped region 62: Tunneling oxide layer 64: First polycrystalline sand layer 66a: Lower surface 66b: Upper surface 66c: Side surface 68: Ring-shaped tip 70: Photoresist layers 72, 72a: dielectric layer 74: second polycrystalline silicon layer 76 '78: source / drain regions 76a, 76b, 78a' 78b: doped profile 80: channel region For an embodiment, please refer to FIG. 3A To Figure 31, which illustrates the present invention A schematic sectional view of the flow of a separate gate flash memory system process in a preferred embodiment. First, referring to FIG. 3A, a first insulating block 56a and a second insulating block 56b are formed on a semiconductor substrate 50. The first insulating block 56a and the second insulating block 56b are formed by two insulating layers 52, 54. Composed of. The material of the insulating layer 52 is, for example, silicon nitride, and the material of the insulating layer 54 is, for example, oxygen 9 (please read the precautions on the back before filling this page). The paper size of the paper is applicable to China National Standard (CNS) A4 (210x297 mm) 411 cranes
f；doc/OOS Λ7 B7 五 發明說明（） 化矽；此二絕緣層52 ' 54係利用化學氣相沈積法所形成’ 而後經過微影蝕刻的步驟，定義出第一絕緣區塊56a與第 二絕緣區塊56b。第一絕緣區塊56a與第二絕緣區塊56b 係彼此交替排列，也就是第一絕緣區塊56a與第二絕緣區 塊56b彼此相鄰，然而二個第一絕緣區塊56a之間並不相 鄰，且二個第二絕緣區塊56b間亦不相鄰’如圖所示° 請參照第3B圖，接著在第一絕緣區塊56a與第二絕 緣區塊56b之周緣形成間隙壁58(spacei·)，尤其是在第一 絕緣區塊56a與第二絕緣區塊56b相鄰的側面形成°間隙 壁58的材質比如爲氮化矽，其形成方法比如是先以化學 氣相沈積法沈積一氮化矽層，再經過非等向性蝕刻’去除 絕緣層54上及半導體基底50表面之氮化矽層，即可形成 間隙壁58。當然，絕緣層52、54及間隙壁58之材質亦可 以有其他之選擇，比如絕緣層52爲氧化矽，絕緣層54爲 氮化砂，間隙壁5 8爲氧化砂。 請參照第3C圖，進行第一次摻雜步驟，比如以離子 植入的方法形成摻雜區60。由於第一絕緣區塊56a、第二 絕緣區塊56b以及間隙壁58之阻隔，因此離子植入所形 成之摻雜區60呈一倒三角形（delta doping)。此摻雜區60 係作爲抗擊穿效應之用（anti-punchthrough)，由於其異於習 知帶狀的抗擊穿摻雜區，而呈一倒三角形，因此可以更有 效防止擊穿效應，並降低位元線（源極線）的電容。尤其在 編程操作時，藉由此倒三角形的抗擊穿摻雜區，可以有效 阻止因源極之高電壓而導致源極與汲極間產生擊穿現象而 10 ------------ 1衣·-----.--訂 /--------. - (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Λ7 08 Λ7 08 經濟部智慧財產局員工消費合作社印製 五、發明說明（ΐ ) 無法編程。此步驟中亦可以同時進行臨界電壓（threshold voltage)的調整。 請參照第3D圖，接著在暴露出的半導體基底50表面’ 形成穿隧氧化層“(tunneling oxide)。比如是利用熱氧化 法(thermal oxidation)，其製程溫度約爲800〜900°C，其厚 度約爲75-95A。然而除了熱氧化法之外’亦可以低壓化 學氣相沈積法（Low Pressure Chemical Vapor Deposition, LPCVD)來製造此穿隧氧化層62。然後在整個半導體基底 50上形成一第一多晶矽層64，其形成方法比如是低壓化 學氣相沈積法，而其厚度約爲U〇〇〜1300A。 請參照第3E圖，去除部分第一多晶矽層(第3D圖之 64)，直到暴露出絕緣層54，而形成浮置閘64a。此時去除 第一多晶矽層的方法包括回蝕刻（etching back)或者化學機 械硏磨法（Chemical Mechanical Polishing，CMP)，而均以 絕緣層54爲終止層。由於間隙壁58的關係，此時浮置閘 64a呈一漏斗型，亦即浮置閘64a上表面66b之截面積大 於該下表面66a之截面積，且上表面60b之周緣具有一非 常尖銳之環狀尖端68。由於間隙壁58之形狀特性，本發 明所形成之浮置閘64a環形尖端68，較習知區域氧化法所 形成之尖端來得更尖銳。接著進行微影步驟，形成一光阻 層70，經過曝光顯影等步驟，使得光阻層70僅覆蓋第二 絕緣區塊56b，而暴露出第一絕緣區塊56a及部分浮置閘 64a上表面66b。 請參照第3F圖，進行一蝕刻步驟，去除第一絕緣區塊 (請先閱讀背面之注意事項再填寫本頁) 一衣------1 ^--訂·--------線- 本紙張尺度適闬中國國家標準（CNSM4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 A7 H7 五、發明說明（p) (第3E圖中之56a)，以及第一絕緣區塊周緣之間隙壁％， 並剝除光阻餍（第3E圖中之70)。其中去除氮化矽(包括絕 緣層52及間隙壁58)的方法比如是以濕式蝕刻法，用熱磷 酸去除之：而去除氧化矽(絕緣層54)的方法則是以氫氟酸 進行濕式蝕刻。此時將暴露出浮置閘6如之部分側面66c 及部分半導體基底50表面。 請參照第3G圖，依序形成一共形之介電層72，以及 第二多晶砂層74於整個半導體基底50表面。介電層72 之材質包括高溫氧化層（Hot Temperature Oxide, HTO)，其 形成方法包括高溫低壓化學氣相沈積法，溫度約爲 900〜1000 由於高溫氧化層具有較佳之階梯覆蓋能力， 因此可以覆蓋浮置閘64a之上表面66b及其暴露出之部分 側面66c ’以及暴露之半導體基底5〇表面。然而介電層72 亦可以形成類似氧化層/氮化矽層/氧化層的結構(ΟΝΟ)， 可以藉由將氧化矽層暴露於氮氣（Ν2)及氨氣（ΝΗ3)的環境 中’溫度約85〇〜900 °C，使氧化矽層部分氮化 (nitridization)。 請參照第3H圖，接著定義第二多晶矽層(第2G圖之74) 及介電層(第3G圖之72)，以形成控制閘74a。比如利用 微影蝕刻的方法，去除部分第二多晶矽層及介電層，而僅 留部分介電層72a及部分第二多晶矽層74a(控制閘）。其 中控制閘7如至少覆蓋浮置閘64a之部分上表面66b和部 分側面66c，以及浮置閘64a鄰近之半導體基底50表面。 請參照第31圖，浮置閘64a與控制閘74a爲蝕刻罩幕， (請先閱讀背面之注意事項再填寫本頁> '衣--------訂---------線- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 '4 秦a7 -_'__B7___ 五、發明說明（U) 進行乾式非等向性蝕刻（anisotropic dry etching)，去除第 二絕緣區塊(第3G圖之56b)，以暴露出半導體基底50表 面。同時進行第二次摻雜步驟，以形成源極/汲極區域76、 78,比如以離子植入法在半導體基底50中形成摻雜區 76a、7Sa，在藉由回火（annea丨)形成輪廓爲76b、78b之源 極/汲極區域76、78。其中源極/汲極區域76位於浮置閘64a 遠離控制閘74a之一側；源極/汲極區域78則位於控制閘 74a遠離浮置閘64a之一側。通道區域80則介於二源極/ 汲極區域76、78之間，分別爲浮置閘64a與控制閘74a 所覆蓋，形成分離式閘極之快閃記憶體。 請參照第31圖，藉由上述之製程可知，本發明所提出 之分離式閘極快閃記億體之結構係建構於半導體基底50 上，由通道區域80、穿隧氧化層62、浮置閘64a、控制閘 74a ’介電層72a及源極/汲極區域76、78所組成。通道區 域80係位於半導體基底5〇表面；浮置閘6如則覆蓋於部 分通道區域80上’且浮置閘6如與半導體基底50之間具 有穿隧氧化層62。而本發明的特徵在於浮置閘64a呈—漏 斗型’亦即浮置閘Ma上表面66b之截面積大於下表面66a 之截面積’且上表面66b之周緣具有一尖銳之環狀尖端 68。介電層72a則配置於浮置閘64a的部分上表面66b與 側面66c ’以及未被浮置閘64a覆蓋之通道區域8〇表面。‘ 控制閘74a配置於介電層72a上，其範圍包括浮置閘64a 的部分上表面66b與側面60c，以及未被浮置閘6妯覆蓋 之通道區域88表面。至於源極/汲極區域76、78，分別配 本紙張尺度適用中國國豕標準（CNS)A4規格（2】〇 κ 297公爱） - -----------^•——— — —'—訂-· —------I , (請先閱讀背面之注意事項再填寫本頁) 41錄利 oc/ΟΟδ 41錄利 oc/ΟΟδ 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（ 置於通道區域80之二側。 綜上所述’本發明至少具有下列優點： 1·本發明之分離式閘極快閃記憶體，係利用間隙壁幾 何形狀之特性’以形成浮置閘之環形尖端。由於間隙壁頂 端之斜率特性’使得本發明彤成之環形尖端，比習知區域 氧化法所形成者更加尖銳。 2_本發明之分離式閘極快閃記憶體，其浮置閘呈一漏 斗狀，且鄰近控制閘的部分具有環狀尖端，可以降低抹除 電壓’及提高抹除速度。更由於本發明之環形尖端較習知 尖銳’因此降低抹除電壓與提高抹除速度之效果更好。 3 本發明所提出之分離式閘極快閃記憶體的製造方 法’係利用間隙壁及平坦化的方法（包括回蝕刻或化學機 械硏磨）形成浮置閘的環狀尖端，利於縮減線寬，並增加 熱預算。 4.本發明所提出之分離式閘極快閃記憶體的製造方 法’利用間隙壁阻隔部分離子植入，使得浮置閘下方基底 中’形成一倒三角形的摻雜區域，以作爲反擊穿摻雜區， 提高反擊穿效果。尤其在編程操作時，藉由此倒三角形的 抗擊穿摻雜區’可以有效阻止因源極之高電壓而導致源極 與汲極間產生擊穿現象而無法編程。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------------ 卜衣--------訂---I-----線* (請先閱讀背面之注意事項再填寫本頁)f; doc / OOS Λ7 B7 5. Description of the invention () Siliconized silicon; The two insulating layers 52 '54 are formed by chemical vapor deposition', and then undergo a lithographic etching step to define the first insulating block 56 a and the first insulating block 56 a. Two insulating blocks 56b. The first insulating block 56a and the second insulating block 56b are alternately arranged with each other, that is, the first insulating block 56a and the second insulating block 56b are adjacent to each other, but the two first insulating blocks 56a are not Adjacent, and the two second insulating blocks 56b are not adjacent, as shown in the figure. Please refer to FIG. 3B, and then form a partition wall 58 on the periphery of the first insulating block 56a and the second insulating block 56b. (spacei ·), in particular, the material for forming the gap wall 58 on the side adjacent to the first insulating block 56a and the second insulating block 56b is, for example, silicon nitride, and the forming method thereof is, for example, chemical vapor deposition A silicon nitride layer is deposited and then anisotropic etching is used to remove the silicon nitride layer on the insulating layer 54 and the surface of the semiconductor substrate 50 to form a spacer 58. Of course, the materials of the insulating layers 52 and 54 and the partition wall 58 can also be selected from other materials. For example, the insulating layer 52 is silicon oxide, the insulating layer 54 is nitrided sand, and the partition wall 58 is oxide sand. Referring to FIG. 3C, a first doping step is performed, such as forming a doped region 60 by an ion implantation method. Due to the blocking of the first insulating block 56a, the second insulating block 56b, and the spacer 58, the doped region 60 formed by the ion implantation has a delta doping. This doped region 60 is used as an anti-punchthrough effect. Since it is different from the conventional band-shaped anti-punchthrough doped region, it has an inverted triangle shape, so it can more effectively prevent the breakdown effect and reduce The capacitance of the bit line (source line). Especially during the programming operation, the anti-breakdown doped region of the inverted triangle can effectively prevent the breakdown between the source and the drain caused by the high voltage of the source. 10 --------- --- 1 clothes · -----.-- Order / --------.-(Please read the phonetic on the back? Matters before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Λ7 08 Λ7 08 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (发明) cannot be programmed. In this step, the threshold voltage can also be adjusted at the same time. Referring to FIG. 3D, a tunneling oxide layer is formed on the exposed surface of the semiconductor substrate 50. For example, thermal oxidation is used, and the process temperature is about 800 ~ 900 ° C. The thickness is about 75-95A. However, in addition to the thermal oxidation method, the Low Pressure Chemical Vapor Deposition (LPCVD) method can also be used to fabricate the tunnel oxide layer 62. Then, a semiconductor oxide layer 50 is formed on the entire semiconductor substrate 50. The method of forming the first polycrystalline silicon layer 64 is, for example, a low pressure chemical vapor deposition method, and its thickness is about OO˜1300A. Please refer to FIG. 3E to remove a portion of the first polycrystalline silicon layer (see FIG. 3D). 64) until the insulating layer 54 is exposed to form a floating gate 64a. At this time, the method for removing the first polycrystalline silicon layer includes etching back or chemical mechanical polishing (CMP), and The insulation layer 54 is used as the termination layer. Due to the relationship of the partition wall 58, the floating gate 64a is a funnel shape, that is, the cross-sectional area of the upper surface 66b of the floating gate 64a is greater than the cross-sectional area of the lower surface 66a, and Surface 60b week It has a very sharp ring-shaped tip 68. Due to the shape characteristics of the gap wall 58, the ring-shaped tip 68 of the floating gate 64a formed by the present invention is sharper than the tip formed by the conventional area oxidation method. Next, a lithography step is performed. A photoresist layer 70 is formed, and after exposure and development, the photoresist layer 70 covers only the second insulating block 56b, and exposes the first insulating block 56a and a portion of the upper surface 66b of the floating gate 64a. Figure 3F, an etching step is performed to remove the first insulating block (please read the precautions on the back before filling this page) Yiyi ----- 1 ^-Order · -------- line -The size of this paper conforms to the Chinese national standard (CNSM4 specification (210x297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7 H7. 5. Description of the invention (p) (56a in Figure 3E), and the first insulation zone. And the photoresist (70 in Fig. 3E). The method of removing silicon nitride (including the insulating layer 52 and the spacer 58) is, for example, wet etching and hot phosphoric acid. Removal: The method for removing silicon oxide (insulating layer 54) is hydrofluoric acid. Wet etching. At this time, part of the side surface 66c of the floating gate 6 and part of the surface of the semiconductor substrate 50 will be exposed. Referring to FIG. 3G, a conformal dielectric layer 72 and a second polycrystalline sand layer 74 are sequentially formed. The entire surface of the semiconductor substrate 50. The material of the dielectric layer 72 includes a high temperature oxide layer (HTO), and the formation method includes a high temperature and low pressure chemical vapor deposition method, and the temperature is about 900 to 1000. Because the high temperature oxide layer has a better step The covering ability can therefore cover the upper surface 66b of the floating gate 64a and the exposed side surface 66c 'and the exposed surface of the semiconductor substrate 50. However, the dielectric layer 72 can also form a structure similar to the oxide layer / silicon nitride layer / oxide layer (NO). The silicon oxide layer can be exposed to the environment of nitrogen (N2) and ammonia (NΗ3). 85 ~ 900 ° C, nitriding the silicon oxide layer. Please refer to FIG. 3H, and then define a second polycrystalline silicon layer (74 in FIG. 2G) and a dielectric layer (72 in FIG. 3G) to form the control gate 74a. For example, using a lithographic etching method, part of the second polycrystalline silicon layer and the dielectric layer are removed, and only part of the dielectric layer 72a and part of the second polycrystalline silicon layer 74a (control gate) are left. The control gate 7 covers at least part of the upper surface 66b and part of the side surface 66c of the floating gate 64a, and the surface of the semiconductor substrate 50 adjacent to the floating gate 64a. Please refer to Figure 31, the floating gate 64a and the control gate 74a are etched screens. (Please read the precautions on the back before filling in this page > '衣 -------- Order ------ --- Line-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' 4 秦 a7 -_'__ B7___ V. Description of Invention (U) Anisotropic dry etching is performed to remove the second insulating block (56B of FIG. 3G) to expose the surface of the semiconductor substrate 50. At the same time, a second doping step is performed to form a source / drain Electrode regions 76, 78, for example, doped regions 76a, 7Sa are formed in the semiconductor substrate 50 by ion implantation, and source / drain regions 76, 78 with contours 76b, 78b are formed by annealing (annea 丨). The source / drain region 76 is located on one side of the floating gate 64a away from the control gate 74a; the source / drain region 78 is located on one side of the control gate 74a away from the floating gate 64a. The channel region 80 is between two The source / drain regions 76 and 78 are respectively covered by the floating gate 64a and the control gate 74a to form a flash memory of a separate gate. Referring to FIG. 31, it can be known from the above process that the structure of the split gate flash memory structure proposed by the present invention is constructed on the semiconductor substrate 50, and includes a channel region 80, a tunnel oxide layer 62, and a floating gate 64a. The control gate 74a is composed of a dielectric layer 72a and source / drain regions 76 and 78. The channel region 80 is located on the surface of the semiconductor substrate 50; the floating gate 6 covers a portion of the channel region 80 'and floats. The gate 6 has a tunneling oxide layer 62 between it and the semiconductor substrate 50. The present invention is characterized in that the floating gate 64a has a funnel shape, that is, the cross-sectional area of the upper surface 66b of the floating gate Ma is greater than the cross-sectional area of the lower surface 66a. 'And the peripheral edge of the upper surface 66b has a sharp ring-shaped tip 68. The dielectric layer 72a is disposed on the upper surface 66b and the side surface 66c of the floating gate 64a and the surface of the channel area 80 which is not covered by the floating gate 64a. The control gate 74a is disposed on the dielectric layer 72a, and its range includes a part of the upper surface 66b and the side surface 60c of the floating gate 64a, and the surface of the channel region 88 not covered by the floating gate 6a. As for the source / drain Areas 76 and 78, respectively with the paper size applicable China National Standard (CNS) A4 Specification (2) 〇κ 297 Public Love----------- ^ • ———— — —'— Order- · —------ I , (Please read the notes on the back before filling out this page) 41 Luli oc / ΟΟδ 41 Luli oc / ΟΟδ Printed by B7 of the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 5. Description of the invention (located on the 80th side of the aisle area) . In summary, the present invention has at least the following advantages: 1. The split gate flash memory of the present invention uses the characteristics of the geometry of the partition wall to form the annular tip of the floating gate. Because of the slope characteristic of the top end of the gap wall, the annular tip formed by the present invention is sharper than that formed by the conventional area oxidation method. 2_ In the split gate flash memory of the present invention, the floating gate has a funnel shape, and the portion adjacent to the control gate has a ring-shaped tip, which can reduce the erasing voltage and increase the erasing speed. Furthermore, since the annular tip of the present invention is sharper than the conventional one, the effect of reducing the erasing voltage and increasing the erasing speed is better. 3 The manufacturing method of the separated gate flash memory proposed by the present invention is to form a ring-shaped tip of the floating gate by using a spacer and a planarization method (including etch-back or chemical mechanical honing), which is beneficial to reducing the line width And increase the thermal budget. 4. The manufacturing method of the separated gate flash memory proposed by the present invention 'uses a partition wall to block part of the ion implantation, so that an inverted triangular doped region is formed in the substrate below the floating gate as a reverse breakdown doping Miscellaneous area to improve the counter-breakdown effect. Especially during the programming operation, the inverted triangular anti-breakdown doped region 'can effectively prevent a breakdown phenomenon between the source and the drain caused by the high voltage of the source, which prevents programming. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 14 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) ------------ Pu Yi -------- Order --- I --- --Line * (Please read the notes on the back before filling this page)