4 2 5 41 \v f. d 〇 c / 0 0 8 409427 A7 B7 經濟部中央樣準局員工消費合作社印製 五、發明説明（ί ) 本發明是有關於一種薄膜電晶體（Thin-Film Transistor ’ TFT) ’且特別是有關於一種具有偏移層（Offset layer)結構的薄膜電晶體。 近年來薄膜電晶體在液晶顯示器（Liquid Crystal Display，LCD)的應用日趨廣泛，且相關的產品也在陸續 量產中。我們所熟知的薄膜電晶體大致上可分爲兩類：一 種爲非晶矽薄膜電晶體，另一種爲複晶矽薄膜電晶體。〜 般來說’非晶矽薄膜電晶體雖有較低的漏電流（Leakage current) ’ 但因爲場效移動率（field effect mobility)過低， 以致導通電流偏低爲其致命傷。而複晶矽薄膜電晶體雖然 具有較高的場效移動率，使得其導通電流有所改善，可是 卻一直無法有效地降低其漏電流，提昇電流開關比 (UU ’使得複晶矽薄膜電晶體無法應用在大面積的液晶 顯示器上。因此，要如何提高薄膜電晶體的場效移動率、 降低漏電流以及提昇電流開關比等，一直是我們所硏究的 課題。 傳統已知的技術中，可利用輕摻雜汲極（LDD)的結構 來降低漏電流。但是，LDD的結構雖可降低漏電流，其製 程卻較爲複雜。另外，在1997年的SSDM中，K. Y. Choi et al.及L H. Jeon et a丨.發表了以非晶砍（a-Si)來做爲偏移層 (offset)的結構，亦可以有效地降低漏電流，但其原件的製 程也相當複雜。 在此，我們提出一種薄膜電晶體之結構與其製造方法’ 以非晶矽做爲偏移層，並以雷射再結晶的方法製作源極和 3 本紙張尺度適用令國國家標準（CNS ) A4规格（210X297公釐） -----r-----裝------訂 f請先閱讀背面之注意事項再填寫本頁} 經濟部中央標準局貝工消費合作社印裝 4 2 54tw l'.doc/0 0 8 409427 A7 B7 五、發明説明（> ) 汲極，製程簡單，且可行性極高，不僅可降低漏電流，更 可簡化元件的製程，增加其實用性。 因此，本發明提出一種薄膜電晶體之製造方法，包括 提供一絕緣基板，於絕緣基板上，依序形成一非晶矽層與 一第一複晶矽層，接著將第一複晶矽層與非晶矽層定義出 一主動區域，主動區域包括一閘極區域與一源極/汲極區 域，然後依序形成一氧化層與一第二複晶矽層覆蓋整個絕 緣基板，之後將第二複晶矽層、氧化層、第一複晶矽層與 非晶矽層定義出閘極區域與源極/汲極區域，並依序去除 源極/汲極區域之第二複晶矽層、氧化層和第一複晶矽層， 以及去除一厚度之源極/汲極區域的非晶矽層，然後對閘 極區域之第二複晶矽層與源極/汲極區域之非晶矽層進行 摻雜，以及使源極/汲極區域之非晶矽層轉爲複晶矽層。 依照本發明一較佳實施例之薄膜電晶體之製造方法， 可有效地減少在靠近汲極端的漏電流，且可提昇元件之導 通電流、場效移動率、以及其他特性。加上以雷射再結晶 的方法進行再結晶，可產生較大的晶粒而降低源極和汲極 的阻値，提高導通電流，並且此結構具有自我對準的特性， 明顯的簡化了製程的複雜度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如T: 圖式之簡單說明： 第1A圖至第1E圖是繪示依照本發明一較佳實施例之 4 -I. ^^^1 mm n^l - E^i rr^^i ^^^1 一OJ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX29?公釐） 409427 A 74 2 5 41 \ v f. D oc / 0 0 8 409427 A7 B7 Printed by the Consumer Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs. 5. Description of the invention (ί) The present invention relates to a thin-film transistor 'TFT)' and, in particular, it relates to a thin film transistor having an offset layer structure. In recent years, the application of thin film transistors in liquid crystal displays (Liquid Crystal Display, LCD) has become increasingly widespread, and related products are also being mass-produced. The thin-film transistors we are familiar with can be roughly divided into two categories: one is an amorphous silicon thin-film transistor, and the other is a multi-crystalline silicon thin-film transistor. ~ Generally speaking, ‘amorphous silicon thin film transistors have a low leakage current’, but because the field effect mobility is too low, the on-state current is too low for their fatal injuries. Although the polycrystalline silicon thin film transistor has a higher field effect mobility, which improves its on-current, it has not been able to effectively reduce its leakage current and improve the current switching ratio (UU 'makes the polycrystalline silicon thin film transistor It cannot be applied to large-area liquid crystal displays. Therefore, how to improve the field-effect mobility of thin-film transistors, reduce leakage current, and increase the current-switching ratio, etc., have been our research topics. Traditionally known technologies, The structure of lightly doped drain (LDD) can be used to reduce leakage current. However, although the structure of LDD can reduce leakage current, its process is more complicated. In addition, in 1997 SSDM, KY Choi et al. And L H. Jeon et a 丨. Published the structure that uses amorphous chute (a-Si) as an offset layer, which can also effectively reduce the leakage current, but its original process is also quite complicated. We propose a thin-film transistor structure and its manufacturing method. 'Amorphous silicon is used as the offset layer, and the source is made by laser recrystallization. 3 paper sizes are applicable to national standards (CNS) A4 specifications ( 210 X297mm) ----- r ----- installation ------ order f, please read the notes on the back before filling out this page} Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 2 54tw l'.doc / 0 0 8 409427 A7 B7 Fifth, the invention description (>) Drain, the process is simple, and the feasibility is very high, not only can reduce leakage current, but also simplify the process of components, increase its practicality. Therefore The present invention provides a method for manufacturing a thin film transistor, which includes providing an insulating substrate, and sequentially forming an amorphous silicon layer and a first polycrystalline silicon layer on the insulating substrate, and then combining the first polycrystalline silicon layer with a non-crystalline silicon layer. The crystalline silicon layer defines an active region. The active region includes a gate region and a source / drain region, and then an oxide layer and a second polycrystalline silicon layer are sequentially formed to cover the entire insulating substrate. The crystalline silicon layer, the oxide layer, the first polycrystalline silicon layer, and the amorphous silicon layer define the gate region and the source / drain region, and sequentially remove the second polycrystalline silicon layer and the oxide in the source / drain region. Layer and the first polycrystalline silicon layer, and an amorphous silicon layer with a thickness of the source / drain region removed, and then The second polycrystalline silicon layer in the electrode region is doped with the amorphous silicon layer in the source / drain region, and the amorphous silicon layer in the source / drain region is converted into a polycrystalline silicon layer. The manufacturing method of the thin film transistor of the preferred embodiment can effectively reduce the leakage current near the drain terminal, and can improve the on-current, field effect mobility, and other characteristics of the device. In addition, it is performed by laser recrystallization. Recrystallization can generate larger crystal grains, reduce the resistance of the source and the drain, increase the on-current, and the structure has the characteristics of self-alignment, which significantly simplifies the complexity of the process. And other purposes, features, and advantages can be more clearly understood. The following is a detailed description of a preferred embodiment and the accompanying drawings, such as T: A brief description of the drawings: Figures 1A to 1E are 4 -I. ^^^ 1 mm n ^ l-E ^ i rr ^^ i ^^^ 1 OJ according to a preferred embodiment of the present invention (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 OX29? Mm) 409427 A 7
4254t\v I'.doc/OOS B7 五、發明説明（3 ) 製造流程剖面示意圖；以及 第2圖是繪示依照本發明一較佳實施例之薄膜電晶體 中導通電流之流動方向示意圖。 圖式之標記說明： 100 :絕緣基板 102 :非晶矽層 102a :非晶矽偏移層 104 :複晶矽層 106 :氧化層 108 :複晶砂層 1 10 :汲極複晶砂層 1 12 :源極複晶矽層 d :偏移層厚度 I :導通電流 較佳實施例 第1A圖至第1E圖是繪示依照本發明一較佳實施例之 製造流程剖面示意圖。 經濟部中央橾準局貝工消费合作社印袈 —II ^^^1 mj ml .^1^1 ^^^1 ^ϋ< ^ϋι 一eJ (請先閱讀背面之注意事項再填寫本頁) 請參照第1 A圖，提供一絕緣基板1 00，在絕緣基板100 上依序形成一非晶砂層102和一通道複晶砂層104，其形 成的方法比如是以化學氣相沉積法（CVD)沉積而成，所形 成之非晶矽層102的厚度約500至2500埃左右，複晶矽 層104的厚度約500至1000埃左右。由於沉積複晶矽層104 的時間並不長，所以在沉積的過程並不足以使底下的非晶 砂層1 0 2產生再結晶的現象。 5 本紙張尺度逋用中國國家標隼（CNS了A4規格（210X297公釐〆 A254i\\i doc/008 409427 A7 B7 經濟部中央梯準局貝工消费合作社印装 五、發明説明（4 ) 請參照第1B圖，接著將複晶矽層104與非晶矽層102 定義出主動區域(active region)，此主動區域包括一閘極區 域與一源極/汲極區，比如以微影和蝕刻的方式進行。然 後形成隔絕元件的絕緣層（未顯示），比如以高原（mesa)的 形式形成。 請參照第1C圖，於複晶矽層104與絕緣基板100上 依序形成一閘極氧化層106和一複晶矽層108，其形成的 方法比如是以化學氣相沉積法（CVD)沉積而成，所形成之 氧化層106的厚度約300至1000埃左右，複晶矽層108 的厚度約3000埃左右。 請參照第1D圖，將複晶矽層108、氧化層1〇6、複晶 矽層104與非晶矽層102定義出閘極區域與源極/汲極區 域，並依序去除源極/汲極區之複晶矽層1〇8、氧化層106、 複晶矽層104、以及去除一厚度d之源極/汲極區域的非晶 矽層102，使得非晶矽層102與複晶矽層104之接面，與 非晶砍層102之源極/汲極區表面相隔一距離，此一厚度d 之非晶矽層即爲非晶矽偏移層(〇ffset)102a，如圖中虛線內 所示，以上定義和去除的方式比如是以微影和蝕刻的方式 進行。其中，非晶矽層102因爲具有較高之能隙，使得在 非晶砂層102與複晶砂層104通道中的載子（carriers)易被 趨向能隙較低之複晶矽通道層104中，而提昇元件之導通 電流、場效移動率、以及其他特性，並且由於非晶矽層102 可有效地降低在汲極附近空乏區（Depletion Region)的電 場，故可減少靠近汲極端的漏電流。 6 (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 本紙張尺度適用中國國家梯準（CNS > A4規格（2丨0X297公釐> 42?4i\v f.doc/008 409427 A7 B7 經濟部中央標準局員工消費合作社印策 五、發明説明（g ) 請參照第1E圖，接著對閘極區域之複晶矽層108以 及源極/汲極區域之非晶矽層102進行摻雜，以增進其導 電性，其摻雜的方法比如是以離子植入（Ion Implantation) 的方式進行。然後再對源極/汲極區之非晶矽層102進行 再結晶，使其成複晶矽層，如複晶矽源極Π2和複晶矽汲 極Π0。而進行再結晶的方法比如是以雷射再結晶（laser recrystallization)的技術，配合以複晶砍層108爲罩幕，如 使用準分子雷射（excimer丨aser)，使用能量約100-300毫焦 耳/平方公分左右，脈衝（pluse)約50-200次/分鐘左右，如 此，即完成複晶矽薄膜電晶體的製作。其中，由於複晶矽 層108、源極112與汲極Π0皆要形成複晶矽層，因此不 必額外使用其他光罩，故使用雷射再結晶具有自我對準 (self-aligned)的特點，可簡化製程的複雜性。 接著請參照第2圖，其繪示依照本發明一較佳實施例 之薄膜電晶體中導通電流之流動方向示意圖。當在此薄膜 電晶體的閘極1〇8、源極112、和汲極110加上適當的工 作偏壓後，其汲極導通電流⑴的流動方向爲圖中之窬頭所 示，電流⑴由汲極】】〇通過非晶矽偏移層丨〇2a後傳至複 晶矽通道層104，在複晶矽通道層104流通後，再由複晶 矽通道層104通過非晶矽偏移層102a後傳至源極112。其 中，可利用調整能隙大小以及偏移層l〇2a的厚度d來控 制元件的各項特性，如導通電流⑴的大小等。在進行雷射 再結晶，調整源極Π2和汲極〗10的結晶程度時，可間接 調整汲極Π0和非晶矽層102接面附近的結晶程度，以及 7 本紙張尺度適用中國標準("CNS ) Α4ϋ格（2丨0X297公釐) ^^1· ^^^1 m ϋ^—. I— I - --- - In m ^^^1 ^ij i (請先閱讀背面之注意事項再填寫本頁) A7 B7 409427 4254t\v1-.(|〇c/00S ~~ — _ 五、發明説明（厶） 源極Π2和非晶矽層102接面附近的結晶程度亦然，藉以 調整能隙大小。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 1. 非晶矽偏移層因爲具有較高之能隙，將會使得通道 中的載子易被趨向能隙較低之複晶矽通道層中，而提昇元 件之導通電流、場效移動率、以及其他特性。 2. 可有效地減少在靠近汲極端的漏電流。 3. 以雷射再結晶的方法，可產生較大的晶粒而降低源 極和汲極的阻値5提闻導通電流。 4. 此結構具有自我對準的特性，明顯的簡化了製程的 複雜度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 .^1- ^1.^1 ^^^1 —^^1 Hal ϋϋ 1^1 m^i 1 C請先閱讀背面之注^^項存填寫本X ) 經濟部中央橾率局貝Η消費合作社印製 8 本紙張尺度適用中國國家榡丰（CNS > A4規格（210X297公釐）4254t \ v I'.doc / OOS B7 V. Description of the invention (3) Schematic cross-sectional view of the manufacturing process; and Figure 2 is a schematic diagram showing the flow direction of the conduction current in the thin film transistor according to a preferred embodiment of the present invention. Description of the symbols of the drawings: 100: insulating substrate 102: amorphous silicon layer 102a: amorphous silicon offset layer 104: polycrystalline silicon layer 106: oxide layer 108: polycrystalline sand layer 1 10: drain polycrystalline sand layer 1 12: Source polycrystalline silicon layer d: Offset layer thickness I: On-state current. FIGS. 1A to 1E are schematic cross-sectional views illustrating a manufacturing process according to a preferred embodiment of the present invention. Seal of the Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs—II ^^^ 1 mj ml. ^ 1 ^ 1 ^^^ 1 ^ ϋ < ^ ϋι eJ (Please read the notes on the back before filling this page) Please Referring to FIG. 1A, an insulating substrate 100 is provided, and an amorphous sand layer 102 and a channel polycrystalline sand layer 104 are sequentially formed on the insulating substrate 100. The formation method is, for example, chemical vapor deposition (CVD) deposition. The thickness of the formed amorphous silicon layer 102 is about 500 to 2500 angstroms, and the thickness of the polycrystalline silicon layer 104 is about 500 to 1000 angstroms. Since the time for depositing the polycrystalline silicon layer 104 is not long, the deposition process is not enough to cause the underlying amorphous sand layer 102 to recrystallize. 5 This paper uses Chinese national standard (CNS A4 size (210X297 mm) A254i \\ i doc / 008 409427 A7 B7. Printed by the Shell Industry Consumer Cooperative of the Central Ladder Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) Referring to FIG. 1B, an active region is defined for the polycrystalline silicon layer 104 and the amorphous silicon layer 102. The active region includes a gate region and a source / drain region, such as lithography and etching. Then, an insulating layer (not shown) of the isolation element is formed, for example, in the form of a mesa. Referring to FIG. 1C, a gate oxide is sequentially formed on the polycrystalline silicon layer 104 and the insulating substrate 100. The layer 106 and a polycrystalline silicon layer 108 are formed by, for example, chemical vapor deposition (CVD). The thickness of the formed oxide layer 106 is about 300 to 1000 angstroms. The thickness is about 3000 Angstroms. Referring to FIG. 1D, the gate and source / drain regions are defined by the polycrystalline silicon layer 108, the oxide layer 106, the polycrystalline silicon layer 104, and the amorphous silicon layer 102, and Sequentially remove the polycrystalline silicon layer 108, the oxide layer 106, and the polycrystal from the source / drain regions. Layer 104 and the amorphous silicon layer 102 with a source / drain region of thickness d removed, so that the interface between the amorphous silicon layer 102 and the polycrystalline silicon layer 104 and the source / drain of the amorphous cut layer 102 The surface of the area is separated by a distance. This amorphous silicon layer of thickness d is the amorphous silicon offset layer (〇ffset) 102a, as shown in the dotted line in the figure. The above definition and removal methods are, for example, lithography and etching. Because the amorphous silicon layer 102 has a higher energy gap, the carriers in the channels of the amorphous sand layer 102 and the polycrystalline sand layer 104 tend to be tended to the polycrystalline silicon channel with a lower energy gap. In layer 104, the on-current, field-effect mobility, and other characteristics of the device are improved, and since the amorphous silicon layer 102 can effectively reduce the electric field in the depletion region near the drain, the proximity to the drain can be reduced. 6 (Please read the precautions on the reverse side before filling out this page) The size of the binding and binding paper is applicable to China National Standards (CNS > A4 specifications (2 丨 0X297 mm > 42? 4i \ v f. doc / 008 409427 A7 B7 Printing Policy of Employee Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Explanation (g) Please refer to FIG. 1E, and then dope the polycrystalline silicon layer 108 in the gate region and the amorphous silicon layer 102 in the source / drain region to improve its conductivity and its doping method. For example, it is performed by ion implantation (Ion Implantation). Then, the amorphous silicon layer 102 in the source / drain region is recrystallized to make it into a polycrystalline silicon layer, such as a polycrystalline silicon source Π2 and a complex silicon layer. Crystal silicon drain Π0. The method for performing recrystallization is, for example, laser recrystallization (laser recrystallization) technology, and the compound crystal cutting layer 108 is used as a mask. If an excimer laser is used, the energy is about 100-300 millimeters. Joules per square centimeter and pulses (pluse) of about 50-200 times / minute. In this way, the production of the polycrystalline silicon thin film transistor is completed. Among them, since the polycrystalline silicon layer 108, the source 112, and the drain Π0 all need to form a polycrystalline silicon layer, it is not necessary to use another photomask, so the use of laser recrystallization has the characteristics of self-aligned. Can simplify the complexity of the process. Please refer to FIG. 2, which illustrates a schematic diagram of a flowing direction of a conduction current in a thin film transistor according to a preferred embodiment of the present invention. When an appropriate working bias voltage is applied to the gate 108, source 112, and drain 110 of the thin-film transistor, the flow direction of the drain on-current ⑴ is as shown in the figure. The current ⑴ From the drain]] 〇 Passed through the amorphous silicon offset layer 〇 02a and passed to the polycrystalline silicon channel layer 104. After the polycrystalline silicon channel layer 104 circulated, the polycrystalline silicon channel layer 104 was shifted through the amorphous silicon The layer 102a is then passed to the source electrode 112. Among them, various characteristics of the device, such as the magnitude of the on-state current ⑴, can be controlled by adjusting the energy gap size and the thickness d of the offset layer 102a. When laser recrystallization is performed to adjust the degree of crystallization of the source Π2 and the drain electrode 10, the degree of crystallization near the interface between the drain Π0 and the amorphous silicon layer 102 can be adjusted indirectly, and 7 paper standards are applicable to Chinese standards (" CNS) Α4ϋ 格 (2 丨 0X297mm) ^^ 1 · ^^^ 1 m ϋ ^ —. I— I-----In m ^^^ 1 ^ ij i (Please read the notes on the back first (Fill in this page again) A7 B7 409427 4254t \ v1-. (| 〇c / 00S ~~ — _ V. Description of the invention (厶) The degree of crystallization near the interface between the source Π2 and the amorphous silicon layer 102 is also the same, so as to adjust it It can be known from the above preferred embodiments of the present invention that the application of the present invention has the following advantages: 1. Because the amorphous silicon offset layer has a higher energy gap, the carriers in the channel will tend to tend to the energy gap. In the lower polycrystalline silicon channel layer, it improves the on-current, field effect mobility, and other characteristics of the device. 2. It can effectively reduce the leakage current near the drain terminal. 3. Laser recrystallization method, It can generate larger crystal grains and reduce the resistance of the source and the drain. 5 Improve the on-current. 4. This structure has self-aligned characteristics. The complexity of the manufacturing process is significantly simplified. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can depart from the spirit and scope of the present invention. Various modifications and retouches are made, so the protection scope of the present invention shall be determined by the scope of the attached patent application.. ^ 1- ^ 1. ^ 1 ^^^ 1 — ^^ 1 Hal ϋϋ 1 ^ 1 m ^ i 1 C Please read the note on the back ^^ Entry and fill in this X) Printed by the Central Economic and Trade Bureau of the Ministry of Economic Affairs and printed by Behr Consumer Cooperatives 8 This paper size is applicable to China National Fengfeng (CNS > A4 size (210X297mm)