經濟部智慧財產局具X消费合作社印製 409369 a? _ B7_ 五、發明說明（1 ) 〔技術領域〕 本發明係爲關於不揮發性半導體記億裝置，特別是關 於混載有以浮動閘極及控制閘極所形成的多層閘極構造之 不揮發性記憶體電晶體及單一閘極構造之MO S電晶體的 半導體裝置之製造方法。 〔背景技術〕 具備高電壓電晶體（例如可以使用MO S電晶體）的 E EPROM之製造方法，例如在美國專利第4，85 1 ，3 6 1號已被記載。依據過去法，在半導體基板形成有 效領域，且形成不揮發性記憶體格的薄彤隧道領域後，將 第1聚合矽層堆積在半導體基板的全面。其次，加工第1 聚合矽層而形成不揮發性記憶格的浮動閘極電極。進而生 成容量絕緣膜、高電壓電晶體的閘極氧化膜及邏輯電路部 分的閘極氧化膜後*在氧化膜的全面堆積第2聚合矽層， 加工此第2聚合矽層而形成記憶體的控制閘極，及高電壓 電晶體的閘極電極和邏輯電路的閘極電極。 〔發明開示〕 不過在如上述混載有E E P ROM等的不揮發性記憶 格及邏輯電路的半導體裝辱之過去的製造方法，在所被堆 積的第2聚合矽層產生第1聚合矽層所造成的段差，當蝕 刻加工第2聚合矽層時，必須除去堆積在第1聚合矽層的 段差側壁部之第2聚合矽，因此必須設定條件使其進行過 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^ H Μ; 」 f I -------r---i.------------訂_!*線..y <請先閲讀背面之注意事項再填寫本頁》 409369 A7 B7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（2 ) 剩的蝕刻而產生側邊蝕刻。但是此情況，降低以第2聚合 矽層所形閘極的尺寸精度，形成微細的閘極會有困難。 另外，爲了同時形成高電壓電晶體的閘極氧化膜及邏 輯電路部的閘極氧化膜，必須較厚地形成閘極氧化膜；邏 輯電路部的微細化會有困難。因而在高電疆Μ 0 S電晶體 的.閘極氧化膜形成較厚的氧化膜，較薄地形成邏輯電路部 '的閘極氧化膜之方法已考慮到，但此方法因增加製程所以 不太理韻。 因此，本發明係爲針對混載有EE PROM等的不揮 發性記億格及邏輯電路的半導體裝置之製造方法；其目的 係爲提供不致增加製造過程，在邏輯電路部形成更微細的 閘極電極之方法。 V - 本發明的第1實施形態係爲包含·：具有以浮動閘極及 控制電極所形成的多層閘極構造之不揮發性記憶體電晶體 與具有車一閘極構造之MO S電晶體其半導體裝置之製造 方法：其特徵爲具備：在半導體基板上形成作爲前述不揮 發性記憶電晶體及Μ 0 S電晶體雙方的閘極氧化膜之第1 絕緣膜之過程，及在前述第1絕緣膜上形成第1導電層之 過程，及從前述第1導電層除去朝與延長前述控制閘極而 彤成的方向垂直之方向延伸之領域，而形成爲了分離前述 浮動閘極的領域之過程·荩在前述第1導電層上形成第2 絕緣膜之過程，及在前述第2絕緣膜上形成第2導電層之 過程，及前述第2導電層經圖案處理後，形成前述控制閘 極之過程，及前述第1導電層經圖案處理後形成前述多層 閲 讀 背 面 之 注Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by X Consumer Cooperatives 409369 a? _ B7_ V. Description of the Invention (1) [Technical Field] The present invention is a device for recording billions of non-volatile semiconductors, and in particular, is mixed with a floating gate and A method for manufacturing a semiconductor device that controls a non-volatile memory transistor with a multilayer gate structure formed by a gate electrode and a MOS transistor with a single gate structure. [Background Art] A manufacturing method of E EPROM including a high-voltage transistor (for example, a MOS transistor can be used) is described in, for example, U.S. Patent Nos. 4,85 1 and 3 61. According to the conventional method, after a semiconductor substrate is formed into an effective field and a thin tunnel region with a nonvolatile memory is formed, a first polymer silicon layer is deposited on the entire surface of the semiconductor substrate. Secondly, the first polysilicon layer is processed to form a non-volatile memory cell floating gate electrode. Further, a capacity insulating film, a gate oxide film of a high-voltage transistor, and a gate oxide film of a logic circuit section are formed. A second polymer silicon layer is deposited on the entire surface of the oxide film, and the second polymer silicon layer is processed to form a memory. Control gate, gate electrode of high voltage transistor and gate electrode of logic circuit. [Invention of the Invention] However, in the past manufacturing method in which semiconductor devices including nonvolatile memory cells and logic circuits mixed with EEP ROM and the like described above were generated, the first polymerized silicon layer was generated in the stacked second polymerized silicon layer. When etching the second polymer silicon layer, it is necessary to remove the second polymer silicon deposited on the side wall portion of the first polymer silicon layer. Therefore, the conditions must be set so that it can pass the Chinese standard (CNS). A4 specification (210 X 297 mm) ^ H Μ; "f I ------- r --- i .------------ order _! * Line..y & lt Please read the notes on the back before filling in this page "409369 A7 B7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) The remaining etching results in side etching. However, in this case, it is difficult to form a fine gate electrode by reducing the dimensional accuracy of the gate electrode formed by the second polymer silicon layer. In addition, in order to form the gate oxide film of the high-voltage transistor and the gate oxide film of the logic circuit portion at the same time, it is necessary to form the gate oxide film thickly; it is difficult to miniaturize the logic circuit portion. Therefore, a method of forming a thicker oxide film and forming a thinner gate oxide film of the logic circuit portion in the M 0 S transistor of the high-voltage transistor has been considered, but this method is not very suitable because of the increase in manufacturing process. Li Yun. Therefore, the present invention is a method for manufacturing a semiconductor device in which nonvolatile memory cells and logic circuits mixed with EE PROM and the like are provided; its purpose is to provide a finer gate electrode in a logic circuit portion without increasing the manufacturing process. Method. V-The first embodiment of the present invention includes: a non-volatile memory transistor having a multi-layer gate structure formed of a floating gate and a control electrode, and a MOS transistor having a car-gate structure. A method for manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate as a gate oxide film of both the nonvolatile memory transistor and the M 0S transistor; and forming the first insulating film on the semiconductor substrate. The process of forming the first conductive layer on the film, and the process of separating the area extending from the first conductive layer in a direction perpendicular to the direction in which the control gate is extended, and forming the area to separate the floating gate.过程 The process of forming a second insulating film on the first conductive layer, the process of forming the second conductive layer on the second insulating film, and the process of forming the control gate electrode after the second conductive layer is patterned. , And the aforementioned first conductive layer is subjected to a pattern treatment to form the above-mentioned multi-layered reading back note
項 本， 頁I w I 麵 I 訂 線 本紙張尺度淖用中國國家標準（CNS)A4規格（210 X 297公*〉 A7 409369 ___B7__ 五、發明說明（3 ) 閘極構造和前述單一閘極構造之過程等的半導體裝置之製 造方法。 <锖先《讀背面之注意事項再填寫4頁) 本發明的第2實施形態係爲如第1實施形態所記載’ 其特徵爲：具有前述單一閘極構造之MO S電晶體係爲構 成高電壓電晶體及周邊電路之MO S電晶體其半導體裝置 之製造方法。 本發明的第3實施形態係爲如第2實施形態所記載’ 其特徵爲：形成前述第1絕緣膜之過程係由形成前述高壓 電晶體的閛極絕緣膜之過程，及在前述浮動閘極與基板之 間形成隧道氧化膜，同時形成前述Μ 0 S電晶體的閘極絕 緣膜之過程等所形成的半導體裝置之製造方法。 本發明的第4實施形態係爲如第1實施形態所記載， 其特徵爲：在於前述第1導電層經圖案處理後形成多層閘 極構造之過程，以構成前述控制閘極之前述第2導電層作 爲遮罩，自我整合地將前述浮動閘極圖案處理的半導體裝 置之製造方法。 經濟部智慧財產局貝工消费合作社印製 本發明的第5實施形態係爲如第1實施形態所記載’ 其特徵爲：以聚合矽構成前述第1導電層及前述第2導電 層的半導體裝置之製造方法。 本發明的第6實施形態係爲如第1實施形態所記載， 其特徵爲：進而具備當前_第2導電層經圖案處理後，在 前述控制閘極的側面形成側壁之過程其半導體裝置之製造 方法" 本發明的第7實施形態係爲如第5‘實施形態所記載1 本紙張尺度適用中國國家標準（CNS)A4規格<210 * 297公釐） 409369 Α7 Β7 五、發明說明（4) 其特徵爲：進而具備在前述第2導電層上形成第1金屬矽 化物層之過程其半導體裝置之製造方法〃 (锖先Μ讀背面之注意事項再填寫本頁) 本發明的第8實施形態係爲如第7實施形態所記載， 其特徵爲：進而具備在前述第1金靥矽化物層上形成第3 絕緣膜之過程，及除去除了前述多層閘極構造的控制閘極 部分以外的前述第3絕緣膜，前述第1金屬矽化物層，前 述第2導電層和前述第2絕緣膜後，形成控制閘極部分之 過程，及在前述控制閘極部分形成側壁之過程，及在所露 出的前述第1導電層和前述第3絕緣膜上，形成第2金屬 矽化物層之過程，及在前述第2金屬矽化物層上，形成第 4絕緣膜之過程，及前述第4絕緣膜，前述第2金屬矽化 物層和前述第1導電層經圖案處理後形成單一閘極構造的 Μ 0 S電晶體，並且以前述控制閘極部分作爲遮罩，蝕刻 前述第1導電層，而自我整合地形成多層閘極構造之過程 等的半導體裝置之製造方法。 經濟部智慧时產局貝工消费合作社印製 本發明的第9實施形態係爲針對具有不揮發性記憶體 格’及電容和/或是電阻*及邏輯電路等的半導體裝置之 製造方法：其特徵爲：進而具備同時形成前述記億體格的 隊道氧化膜和前述邏輯電路之MO S電晶體的閘極氧化膜 之過程，及在前述氧化膜的全面形成第1聚合矽層之過程 ，及除去分離前述第1聚舍矽層的前述記億格的浮動閘極 之領域之過程，及在前述第1絕緣膜的全面形成第2聚合 矽層之過程，及在前述第2聚合矽層上形成第2絕緣膜之 過程，及存留前述記億體格的所望領域及前述電容的上部 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 409369 A7 一―—— B7 五、發明說明（5) (請先閲讀背面之注意事項再填寫本頁) 電極領域，除去前述第2絕緣膜，第2聚合矽層及第1絕 緣膜之過程，及在全面形成第3絕緣膜之過程，及留存前 述第3絕緣膜之前述電容的下部電極領域及電阻領域之部 分，除去其他的部分之過程，及全面異方性蝕刻後形成前 述記憶體的多層閘極的側壁之過程等的半導體裝置之製造 方法》 〔圖面之簡單說明〕 第1〜1 3圖係爲說明本發明第1實施形態的半導體 裝置之製造方法之圖。 第1圖係爲在半導體基板1的表面形成場區氧化膜2 ，較厚的閘極氧化膜3，以及隱道氧化膜4等之上面圖。 第2圖係爲在第1圖所示的部位I I所剖切之斷面圖 第3圖係爲在基板的全面堆積聚合矽層6，作爲第1 導電層之圖。 第4圖係爲表示蝕刻除去所定位置之聚合矽層6的構 造之上面圖。_ 經濟部智慧财產局具工消費合作社印« 第5圖係爲在第4圖所示部位V所剖切之斷面圖。 第6圖係爲表示在聚合矽層6之上形成第1絕緣膜之 斷面圖· 第7圖係爲表示在第1絕緣膜7之上形成第2導電層 之斷面圖· 第8圖係爲在第7圖所示階段的相當於第4圖的部位 本紙張尺度通用中國國家標準（CNSJA4規格（210 * 297公* ) 經濟部智慧財產局貝工消费合作社印製 409369 A7 ..... B7 五、發明說明（6) V所剖切之斷面圖* 第9圖係爲表示在相當於多層閘極的部分設置控制閘 極之斷面圖。 第1 0圖係爲在第9圖所示的部位X所剖切之斷面圖 〇 第1 1圖係爲以本發明第1實施形態所製作的半導體 裝置之斷面圖。 第1 2圖係爲以控制閘極部作爲遮罩之本發明第1實 施形態所作成‘的半導體裝置之上面圖。 第13圖係爲在第12圖所示的部位I I I所剖切之 斷面圖。 第1 4〜2 3圖係爲說明本發明第2實施形態的半導 體裝置之製造方法之圖。 第1 4圖係爲在半導體基板2 1上形成場區氧化膜及 閘極氧化膜之斷面圖β 第1 5圖係爲表示使甩光敏抗蝕劑，除去相當於不揮 發性記憶格的多層閘極及邏輯電路的MO S電晶體的閘極 之一部分的閘極氧化膜2 3之斷面圖。 第1 6圖係爲形成不揮發性記億格的多層閘極之隧道 氧化膜2 5 a及相當於邏輯電路的MO S電晶體的閘極之 —部分的閘極·氧化膜25b之斷面圖。 .第17圖係爲表示在基板的全面形成摻雜過的聚合砂 層2 6，作爲第1導電層的階段之斷面圖。 第1 8圖係爲表示在基板的全面形成以S i 〇2/ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) -i I n ft— n n n I nM n n n I I »^30- - I n L n ϋ I i請先M讀背面之注意事項再填寫本頁)Item, page I w I Surface I Alignment This paper size adopts Chinese National Standard (CNS) A4 specification (210 X 297 male *> A7 409369 ___B7__ V. Description of the invention (3) Gate structure and the aforementioned single gate structure Process for manufacturing semiconductor devices, etc. < 锖 "Read the precautions on the back side and fill in 4 pages first." The second embodiment of the present invention is described in the first embodiment. The MOS transistor system with a pole structure is a method for manufacturing a semiconductor device of a MOS transistor and a peripheral circuit constituting a high voltage transistor. The third embodiment of the present invention is as described in the second embodiment, and is characterized in that the process of forming the first insulating film is a process of forming the pole insulating film of the high-voltage transistor and the floating gate A method for manufacturing a semiconductor device formed by forming a tunnel oxide film between a pole and a substrate, and simultaneously forming a gate insulating film of the aforementioned M 0 S transistor. The fourth embodiment of the present invention is as described in the first embodiment, and is characterized in that the first conductive layer is subjected to a patterning process to form a multi-layered gate structure to form the second conductive layer that controls the gate electrode. A layer is used as a mask, and a method for manufacturing a semiconductor device in which the aforementioned floating gate pattern is self-integrated. The fifth embodiment of the present invention printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is as described in the first embodiment, and is characterized in that the semiconductor device in which the first conductive layer and the second conductive layer are made of polysilicon is a semiconductor device Of manufacturing method. The sixth embodiment of the present invention is as described in the first embodiment, and is characterized by further including a process for forming a side wall on a side surface of the control gate after the current_second conductive layer is subjected to a pattern treatment, and a semiconductor device is manufactured. Method " The seventh embodiment of the present invention is as described in the 5 'embodiment. 1 The paper size applies the Chinese National Standard (CNS) A4 specification < 210 * 297 mm) 409369 Α7 Β7 5. Description of the invention (4 ) It is characterized in that it further includes a method for manufacturing a semiconductor device by forming a first metal silicide layer on the second conductive layer. (锖 Read the precautions on the back before filling this page) The eighth implementation of the present invention The morphology is as described in the seventh embodiment, and further includes a process of forming a third insulating film on the first gold-silicide layer, and removing a portion other than the control gate portion of the multilayer gate structure. Forming the control gate portion after the third insulating film, the first metal silicide layer, the second conductive layer, and the second insulating film, and forming a sidewall of the control gate portion; Process of forming a second metal silicide layer on the exposed first conductive layer and the third insulating film, and process of forming a fourth insulating film on the second metal silicide layer, and The fourth insulating film, the second metal silicide layer, and the first conductive layer are patterned to form an M 0 S transistor with a single gate structure, and the control gate portion is used as a mask to etch the first A method for manufacturing a semiconductor device such as a process in which a conductive layer is self-integrated to form a multilayer gate structure. The ninth embodiment of the present invention printed by the Shellfish Consumer Cooperative of the Smart Time Production Bureau of the Ministry of Economics is a method for manufacturing a semiconductor device having a non-volatile memory cell, a capacitor and / or a resistor *, a logic circuit, and the like: its characteristics In order to further include a process of simultaneously forming the oxide film of the track with a physical size of 100 million and the gate oxide film of the MOS transistor of the logic circuit, and the process of forming the first polymerized silicon layer on the entire surface of the oxide film, and removing it The process of separating the field of the floating gate of the first polysilicon layer described above, and the process of forming the second polysilicon layer on the entire surface of the first insulating film, and forming the second polysilicon layer The process of the second insulation film, and the desired area where the aforementioned physique is stored, and the upper part of the aforementioned capacitor. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 409369 A7 I ------ B7 V. Invention Note (5) (Please read the precautions on the back before filling this page) In the electrode field, the process of removing the aforementioned second insulating film, the second polysilicon layer and the first insulating film, and forming the third insulation in an all-round way Process of the film, and the process of retaining the lower electrode area and the resistance area of the capacitor of the third insulating film, removing the other parts, and forming the side walls of the multilayer gate of the memory after full anisotropic etching [Simplified description of drawings] [Simplified description of drawings] Figures 1 to 13 are diagrams illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention. The first figure is on the surface of the semiconductor substrate 1. The top view of the field oxide film 2, the thicker gate oxide film 3, and the hidden channel oxide film 4 are formed. The second figure is a cross-sectional view cut at the part II shown in the first figure. The picture shows the polymer silicon layer 6 deposited on the entire surface of the substrate as the first conductive layer. The picture 4 shows the top view showing the structure of the polymer silicon layer 6 at a predetermined position by etching. Industrial and consumer cooperative seal «Figure 5 is a cross-sectional view cut at the location V shown in Figure 4. Figure 6 is a cross-sectional view showing the formation of a first insulating film on the polymer silicon layer 6 7 is a view showing formation of a second conductive layer on the first insulating film 7 Cross-section view of the layer. Figure 8 is the part corresponding to Figure 4 at the stage shown in Figure 7. The paper size is common Chinese national standard (CNSJA4 specification (210 * 297) *). Printed by the Consumer Cooperative 409369 A7 ..... B7 V. Description of the invention (6) Sectional drawing cut by V * Figure 9 is a sectional view showing that the control gate is installed in the part corresponding to the multilayer gate Fig. 10 is a cross-sectional view cut at the portion X shown in Fig. 9. Fig. 11 is a cross-sectional view of a semiconductor device manufactured in the first embodiment of the present invention. Fig. 1 2 FIG. Is a top view of a semiconductor device according to the first embodiment of the present invention using a control gate portion as a mask. Fig. 13 is a cross-sectional view taken at the site I II shown in Fig. 12. Figures 14 to 23 are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 14 is a cross-sectional view of a field oxide film and a gate oxide film formed on a semiconductor substrate 21. FIG. 15 is a diagram showing the removal of a photoresist equivalent to a nonvolatile memory cell. A cross-sectional view of a gate oxide film 23 of a multilayer gate and a gate of a MOS transistor of a logic circuit. Fig. 16 is a section of the gate oxide film 25b forming a non-volatile multi-layer grid gate oxide film 25a and the gate corresponding to the MOS transistor of the logic circuit-part of the gate oxide film 25b Illustration. Fig. 17 is a sectional view showing a stage in which a doped polymer sand layer 26 is formed on the entire surface of the substrate as a first conductive layer. Figure 18 shows the full formation of the substrate. S i 〇2 / This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm *) -i I n ft— nnn I nM nnn II »^ 30--I n L n ϋ I i Please read the notes on the back before filling in this page)
I A7 409369 __B7__；_ 五、發明說明（7 ) s i 3N4/S i 〇23層所構成的ΟΝΟ膜2 7的階段之 斷面圖。 第1 9圖係爲表示在所定的位置設置光敏抗蝕層3 1 ，籍由乾式蝕刻除去CVD 51〇2膜30、巩矽化物層 2 9、聚合矽層2 8及ΟΝΟ膜2 7後，形成不揮發性記 憶格的多層閘極及電容器的階段之斷面圖。 第2 0圖係爲表示在基板的全面形成CVD S i 〇2膜 3 2的階段之斷面圖。 第21圖係爲表示在相當於電容及電阻之位置設置光 敏抗蝕劑3 3，藉由乾式蝕刻除去CVD S i 〇2膜後，在 多層閘極部之上部構造的側壁形成側壁3 4的階段之斷面 圖。 第2 2圖係爲表示在基板的全面形成金屬矽化物層， 及在該金屬矽化物層之上形成CVDS i 〇2膜3 6的階段 之斷面圖。 第2 3圖係爲表示將ON ◦膜2 7以上的上部構造物 及被形成在側部之側壁3 4作爲遮罩使用，自我整合地形 成浮動閘極的階段之斷面圖。 第2 4圖係爲以本發明的第2實施形態所製作的半導 體裝置之斷面圖》 第2 5圖係爲表示在對應於不揮發性記億格、MOS 電晶體、電容及電阻之位置，形成以聚合矽層2 6、 ΟΝΟ膜，聚合矽層28及CVDS i 〇2膜30所構成之 積層構造的階段之斷面圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先E讀背面之注意事項再填寫本頁) -----丨丨 i I 訂—I----•線. 經濟部智慧財產局貝工消f合作社印製I A7 409369 __B7__; _ V. Description of the invention (7) A sectional view of the phase 7 of the ONO film 27 composed of s i 3N4 / S i 〇23 layers. FIG. 19 is a view showing that a photoresist layer 3 1 is provided at a predetermined position, and the CVD 51〇2 film 30, the siliicide layer 29, the polymer silicon layer 28, and the ONO film 27 are removed by dry etching. Sectional view of the stages of forming multi-layered gates and capacitors of non-volatile memory cells. FIG. 20 is a cross-sectional view showing a stage of forming a CVD S i 〇2 film 32 on the entire surface of the substrate. FIG. 21 is a view showing that a photoresist 3 3 is provided at a position corresponding to a capacitor and a resistance, and a CVD S i 〇2 film is removed by dry etching, and then a sidewall 34 is formed on a sidewall of a structure above the multilayer gate portion. Sectional view of stages. FIG. 22 is a cross-sectional view showing a stage in which a metal silicide layer is formed on the entire surface of the substrate, and a CVDS i 02 film 36 is formed on the metal silicide layer. Fig. 23 is a cross-sectional view showing a stage in which an upper structure having an ON film of 27 or more and a side wall 34 formed on the side are used as a mask to form a self-integrated floating gate. Fig. 24 is a cross-sectional view of a semiconductor device manufactured according to a second embodiment of the present invention. "Fig. 24 is a diagram showing the positions corresponding to non-volatile terabytes, MOS transistors, capacitors, and resistors. A cross-sectional view at the stage of forming a layered structure composed of a polymer silicon layer 26, an ONO film, a polymer silicon layer 28, and a CVDS10 film 30. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- 丨 丨 I Order—I ---- • Line. Printed by the Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs
W 經濟部智慧財產局員工消费合作社印製 409369 A7 _：_ ________ 五、發明說明（8 ) 第2 6圖係爲表示在存留電容器的下部電極領域及電1 阻器領域之CVD S i 〇2膜3 2的狀態下，藉由面全異方 性蝕刻後在多層閘極的上部構造之側面形成側壁3 4的階 段之斷面圖》 主要元件對照表 1 半導體基板 2 場區氧化膜 3 閘極氧化膜 4 踡道氧化膜 5 閘極氧化膜 6 聚合矽層 7 絕緣膜 8 聚合矽層 9 多層閘極 10 絕緣膜 11 聚合矽層 12 絕緣膜 13 側壁 14 浮動閘極 15 絕緣層 16 選擇閘極電極 17 閘極電極 21 半導體基板 illlr.---— in 11 —訂、----；丨丨丨—線' (諳先閲讀背面之注意事項再填寫本頁) 本紙張尺度_適用中國國家標準（CNS)A4規格（210 X 297公釐）. 409369 Α7 Β7 經濟部智慧財產局員工消费合作社印製 五、發明說明（9) 2 2 場區氧化膜 23 閘極氧化膜 24 光敏抗蝕劑 25a 隧道氧化膜 25b 閘極氧化膜 2 6 聚合砂層 2 7 Ο N 0 膜 28 聚合矽層 29 鎢（W)矽化合物層 30 CVDSi〇2 膜 31 光敏抗蝕劑 32 CVDSi〇2 膜 3 3 光敏抗蝕劑 35 鎢矽化合物層 36 CVDSi〇2 膜 3 7 多層閘極 3 8 選擇閘極 3 9 閘極 4 0 電容 〔實施形態〕 . 參照第1〜13圖說明本發明半導體裝置之製造方法 的第1實施形態。此第1實施形態相當於本發明第1〜6 的形態。此方法係爲混載有E E P R 〇·Μ等的不揮發性記 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公a ) (請先W讀背面之注意事項再填窝本頁) <M. ill —--訂-----II---線 409369 A7 B7 五、發明說明（10) (諳先閲讀背面之注§項再填篇本頁) 億格及MO S電晶體的半導體裝置之製造方法。不揮發性 記憶格具有介隔絕緣膜，浮動閘極及控制閘極積層在隧道 氧化膜上之多層閘極，及選擇所希望的多層閘極之高電壓 電晶體所形成之選擇閘極，藉由通過隧道氧化膜後強制性 注入電荷，而控制多層閘極之電晶體的臨界値電壓，記億 資料。別種方法也有內藏產生以高電壓電晶體所形成之高 電壓，進而進行控制之電路的情況。本發明的方法，因對 閘極的形成法特別具有特徵，所以在有效領域之眾知的通 道、源極、汲極等的形成則省略說明》 第1圖係爲在半導體基板1的表面形成場區氧化膜2 ，較厚的閘極氧化膜3、及隧道氧化膜4之上面圖。第2 圖係爲在第1圖所示的部位II所剖切之斷面圖。於此階 段，在半導體基板1，已經形成有作爲記憶體之電晶體的 源極，汲極及多層閘極及選擇閘極及MO S電晶體的通道 領域，但爲了維持圖面的明瞭性所以未圖示· 經濟部智慧財產局貝工消费合作社印製 最初，以熱氧化形成場區氧化膜2及較厚的閘極氧化 膜3。場區氧化膜的厚度爲4 5. 0 nm，閘極氧化膜的厚 度例如爲4 1 . 5 nm。繼而用遮罩，蝕刻除去相當於不 揮發性記億格的隧道氧化膜4之位置及相當於邏輯電路的 閘極氧化膜5之位置的閘極氧化膜3，進而分別形成1 0 nm厚度的隧道氧化膜4及MO S電晶體的閛極氧化膜5 。在於第2圖，領域i爲不揮發性記憶格的領域’領域 ii爲MOS電晶體的領域。 其次，第3圖係爲將聚合矽層6堆積在該基板的全面 13- 本紙張尺度適用中國國家標準（CNSXA4規格（210 X 297公爱） 409369 經濟部智慧財產局員工消费合作社印製 Α7 Β7 五、發明說明（11) 作爲第1導電層之圖。其次分離構成不揮發性記億格的浮 動閘極之聚合矽層6。第4圖係爲表示蝕刻除去所定位置 的聚合矽層6的構造之上面圖。第5圖係爲在第4圖所示 的部位V所剖斷之斷面圖；此剖斷線則是與第1圖的剖斷 線正交。表示蝕刻聚合矽層6的所定位置後形成溝，在溝 的底部露出場區氧化膜2之樣子。其後只朝與延長控制閘 極而被形成的Y方向垂直之X方向形成溝。不形成此溝則 在之後的過程，若延長控制閘極而未形成切痕時就無法分 離浮動閘極。 繼而，第6圖係爲表示在聚合矽層6之上形成第1絕 緣膜之斷面圖。在聚合矽層6上，以Si 〇2、S i a N 4 、Si〇2的3層構成（以下，稱爲ΟΝΟ膜），形成絕緣 膜7。 第7圖係爲表示在第1絕緣膜7以上形成第2導電層 之斷面圖。堆積聚合矽層8作爲第2導電層。第8圖係爲 在形成聚合矽層8的狀態下，在相當於第4圖的部位V所 剖切之斷面圖》 第9圖係爲表示在相當於多層閘極的部分設置控制閘 極之上面圖》第1 0圖係爲在第9圖所示的部位X所剖切 之斷面圖。表示在聚合矽層8的全面形成絕緣膜1 0 ;進 而在相當於不揮發性記億锋的多層閘極之部分設置遮罩； 利用反應性離子蝕刻，蝕刻除去除了相當於多層閘極的部 分以外的第2絕緣膜10、聚合矽層8及第1絕緣膜7 ’ 形成聚合矽層（控制閘極）11之樣子。 本紙張尺度通用中囡國家標準（CNS)A4規格（210 * 297公釐） ΤΤ2ΓΤ --— 1^----Γ — l·^. -----訂、----.----線S··· (請先閱讀背面之注意Ϋ項再填寫本頁> 4093C9 A7 A7 B7 五、發明說明（12) 繼而，堆積絕緣膜1 2 *反應性離子蝕刻全面，而在 控制閘極1 1的側部形成側壁1 3。.其次，利用此側壁， 蝕刻聚合矽層6，因而自我整合地形成成爲不揮發性記億 格之多層閘極9的一部分之浮動閘極14。當形成浮動閘 極1 4之蝕刻時，可以同時形成不揮發性記億格的選擇閘 極1 6及Μ 0 S電晶體.的閘極電極1 7。最初堆積絕緣膜 1 5，其次在相當於不揮發性記億格的選擇閘極及MO S 電晶體的閘極電極之部分設置遮罩。以此遮罩、絕緣膜 1 2、側壁1 3作爲蝕刻遮罩，蝕刻絕緣餍1 5及聚合矽 層。因而與浮動閘極1 4同時形成不揮發性記憶格的選擇 閘極電極1 6及MOS電晶體的閘極電極1 7。然後除去 相當於不揮發性記憶格的選擇閘極及Μ 0 S電晶體的閘極 之位置的遮罩。繼而以眾知的方法形成選擇閘極及 MOS電晶體的源極及汲極。第11圖表示經該方法所製 作的半導體裝置之斷面圖。i表示不揮發性記憶格領域、 及i i爲MOS電晶體領域。 '自我整合地形成不揮發性記憶格的浮動閘極14,以 第9圖的控制閘極部分（即是第1絕緣膜7、控制閘極 11，及第2絕緣膜10)作爲遮罩，蝕刻聚合矽層6而 可以形成浮動閘極。此時也與前述同樣的方法，可以同時 形成不揮發性記憶格的選-閘極電極1 6及MO S電晶體 的閘極電極1 7。第1 2圖表示經由此方法所作成的半導 體裝置之上面圖。第1 3圖係爲在第1 2圖所示的部位 X I I I所剖斷之斷面圖》 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先Mtl背面之注意事項再填寓本頁) -^--------^.· I I I- I I ---Φ: 經濟部智慧財產局員工消费合作社印製 409369 A7 _^__B7____ 五、發明說明（13) 如上述過，依據本發明，可以與不揮發性記億格之多 層閘極9的隧道氧化膜4 —起形成較薄的MO S電晶體之 閘極氧化膜5;進而自我整合地形成多層閘極9的浮動閘 極1' 4，所以不致增加過程數，且使閘極微細化。 參照第1 4〜2 3圖說明本發明的第2實施形態。此 實施形態係爲相當於本發明的第7及第8實施形態，具有 多層閘極構^之不揮發性記億格及邏輯電路之MO S電晶 體及具有電阻及電容的半導體裝置之製造例。關於不揮發 性記憶格的閘極及MO S電晶體的閘極其雙方之下部活性 領域的形成：逋道或源極，汲極的形成，由於是眾所皆知 所以省略說明。 第14圖係爲表示在半導體基板21上形成場區氧化 膜及閘極氧化膜之斷面圖。在半導體基板21的表面，以 熱氧化形成厚度4 5 0 nm的場區氧化膜2 2及厚度 41 . 5nm的較厚閘極氧化膜23。在此階段，由於在 半導體基板21已經形成不揮發性記億格之多層閘極的源 極、汲極與多層閘極；選擇閘極與Μ 0 S電晶體之通道領 域，所以省略圖示》 繼而，第1 5圖係爲表示使用光敏抗蝕劑，除去相當 於不揮發性記憶格的多層閘極及邏輯電路之MO S電晶體 的閘極其一部分的閘極氧化膜2 3之斷面圖。使用光敏抗 蝕劑2 4，以濕式蝕刻除去不揮發性記憶格之多層閘極的 隧道氧化膜2 5 a及邏輯電路之MO S電晶體的閘極氧化 膜2 5 b其一部分的較厚閘極氧化膜2 3 · 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） (請先Μ讀背面之注意事項再填寫本頁) -，.袭---丨丨丨I I訂I I _丨一！線 經濟部智慧財產局員i消費合作社印製 -ΊΟ - 經濟部智慧財產局貝工消t合作社印製 409369 A7 __- _ 五、發明說明（14) 繼而，第1 6圖係爲形成不揮發性記億格之多層閘極 的隧道氧化膜2 5 a及相當於邏輯電路之M OS電晶體的 閘極之一部分的閘極氧化膜之斷p圖。除去抗蝕劑2 4， 經過必要的洗淨過程，以熱氧化形成厚度1 0 nm的隧氧 氧化膜25及MOS電晶體的閘極氧化膜25b。然後， 如第1 7圖所示，以CVD法在氧化膜的全面形成厚度 2 5 0 nm的聚合矽層2 6。摻雜磷而在聚合矽層2 6使 其具有所定的傳導性，作爲第1導電層。此時，用氟化氫 酸液除去所產生的磷玻璃·繼而，如先前所說明過，以乾 式蝕刻除去聚合矽層2 6的所定部分，進行浮動閘極的分 離。 其次，如第1 8圖所示，在全面形成以厚度1 0 nm 的S i 〇2、厚度10nm的S i3N. 4、厚度5nm的 S i 〇2的3層所形成之ΟΝΟ膜2 7 : S i 〇2以熱化形 成，S i3N4以CVD法形成；在其上面形成厚度250 nm的聚合矽層2 8，摻雜磷使其具有所定的導電性，作 爲第2導電層。此時，用氟氫酸液除去表面所產生的磷玻 璃。經過必要的洗淨過程，在聚合矽層2 8之上，以濺射 法形成厚度1 5 0 nm的金屬矽化物層，本例則是形成 150nm的鎢（W)矽化物層29 *進而，在其上面， 以CVD法形成厚度23Qnm的Si〇2膜30(以下， 稱爲CVDSi〇2膜）。 其次，如第1 9圖所示，爲了形成不揮發性記億格的 多層閘極及電容，而在所定的位置設光敏抗蝕劑3 1，以 本紙張尺度.適用中國國家標竿（CNS>A4規格（210 X 297公釐） T7 _ . ------^-------訂··---,"!!線 <請先«讀背面之注意事項再填窝本頁) 409369 A7 _ B7 五、發明說明（15) 乾式蝕刻除去CVDSi〇2膜30、W矽化物層29、聚 合矽層2 8及ΟΝΟ膜2 7。在此喈段形成多層閘極的上 部構造及用於電容的積層構造。繼而，除去光敏抗蝕劑 3 1後，如第2 0圖所示，在全面形成厚度1 7 0 nm的 CVDS i 〇2 膜 32。 其次*如第2 1圖所示，在相當於電容及電阻之位置 設置光敏抗独劑33，以乾式蝕刻除去CVDS i 〇2膜 32«藉由乾式蝕刻，在露出CVDSi〇2膜32之多層 閘極部的上部構造之側壁，形成側壁3 4，但在披覆於光 敏抗蝕劑3 3之電容部及電阻部則未形成側壁。 其次，除去抗蝕劑，經過必要的洗淨過程，如第2 2 圖所示，在全面形成金屬矽化物層，在此例則是以濺射法 形成15〇nm的W矽化物層35 :在其上面以C V D法 形成厚度23〇nm的CVDS i〇2膜36。最後，在 CVD S i 〇2膜3 6上的相當於選擇閘極及邏輯電路之 Μ 0 S電晶體的閘極之各別位置設置光敏抗蝕劑，以乾式 蝕刻除去除了光敏抗蝕劑下部以外的CVD S i 〇2膜3 6 、界矽化物層3 5、聚合矽層2 6，且除去光敏抗蝕劑。 其結果，如第2 3圖所示，（1 )形成備有以聚合砂層（ 浮動閘極）2 6、ΟΝΟ膜2 7、聚合矽層（控制閘極） 2.8、W矽化物曾29及pVDS i 〇2膜30所形成的多 層閘極3 7、與以聚合矽層2 6、W矽化物層3 5及 CVDS i 〇2膜3 6所形成的選擇閘極3 8之不揮發性記 億體格；（2)形成以聚合矽層2 6、W矽化物層3 5及 本紙張尺度適用中國國家標準（CNS)A4規袼<210 X 297公釐） <請先M讀背面之注意事項再填寫本頁) 、裝·----I i丨訂.i — L-----線 經濟部智慧財產局MK工消费合作社印製 409369 A7 _ B7 五、發明說明（16> CVDS i 〇2膜3 6所形成之MOS電晶體的閘極3 9 9 (3)同時形成以聚合矽層26、0. NO膜27、聚合矽 (請先閲讀背面之注意事項再填寫本頁) 層28、W矽化物層29、 CVDSi〇2膜30及 CVDSi〇2膜32所形成之電容40 ;以及（4)以聚 合矽層2 6及第2 CVD S i 〇2膜3 2所形成之電阻4 1 〇 從第2^圖能明白，多層閘極3 7之浮動閘極（聚合 矽層）26，藉由以0N ◦膜2 7以上的上部構造物及被 形成在側部的側壁3 4作爲遮罩使用，而被自我整合地形 成*進而，以眾知的方法，形成選擇閘極及Μ 0 S電晶體 的源極及汲極。第2 4圖表示以此方法所製作的半導體裝 置之斷面圖。在於第2 4圖，c h表示通道，d表示汲極 ，8表示源極。然而，第1 3圖所示半導體裝置之各閘極 的下部之導通、源極、汲極的構成也是與第24圖同樣， 圖示則省略。 經濟部智慧財產局貝工消f合作社印製 改變爲第14〜2 3圖所示的第2實施形態，也可以 採用省略掉金屬矽化物層之第3實施形態。第3實施形態 相當於本發明的第9實施形態。在於第3實施形態，當製 造不揮發性記億格及邏輯電路的MO S電晶體及具有電阻 與電容之半導體裝置時，不用金屬矽化物層2 9與3 5， 可以以聚合矽層2 6及聚幸矽層2 8作爲電極。即是在沒 有W矽化物層2 9與3 5的形成過程之情況下，在對應於 不揮發性記億格、M0S電晶體、電容及電阻之位置，如 第25圖所示製作以聚合矽層26、 ΟΝΟ膜27、聚合 本紙張尺度適用中國囷家楳準<CNS〉A4規格（210 X 297公釐） 409369 Α7 Β7 五、發明說明（17) 矽層2 8及CVDS i 〇2膜3 0所形成之積層構造。第 2 5圖係爲對應於第2實施形態的第1 9圖所表示的階段 。繼而，在該全體構造上形成CVDS i 〇2腠3 2，如第 2 6圖所示，在留存有電容的下部電極領域及電阻領域之 CVDS i 〇2膜3 2的狀態下，全面經異方性蝕刻而在多 層閘極的上部構造之側面形成側壁34亦可。第26圖係 爲對應於第2實施形態的第2 1圖所表示的階段。藉由此 方法也可以自我整合地形成浮動閘極。其後的過程則與第 2實施形態相同。 〔產業上之實用性〕 如以上所說明過，依據本發明，當製造具有不揮發性 記憶格及邏輯電路之半導體裝置時，除了分離浮動閘極之 領域以外，由於留存有第1導電層（聚合矽層6)，所以 維持表面的平坦性。因此，第2導電層的蝕刻過程等其後 過程的加工變爲容易，可以提高尺寸精度，且能微細化。W Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 409369 A7 _: _ ________ V. Description of Invention (8) Figures 2 and 6 show the CVD S i 〇2 in the field of the lower electrode of the capacitor and the resistor of the capacitor. In the state of the film 32, the cross-sectional view of the stage where the sidewall 34 is formed on the side surface of the upper structure of the multi-layer gate after the surface is completely anisotropically etched. Main component comparison table 1 Semiconductor substrate 2 Field oxide film 3 Gate Polar oxide film 4 Channel oxide film 5 Gate oxide film 6 Polysilicon layer 7 Insulating film 8 Polysilicon layer 9 Multi-layer gate 10 Insulating film 11 Polysilicon layer 12 Insulating film 13 Side wall 14 Floating gate 15 Insulating layer 16 Selecting gate Electrode 17 Gate electrode 21 Semiconductor substrate illlr .----- in 11 —Order, ----; 丨 丨 丨 —Wire '(谙 Please read the precautions on the back before filling this page) This paper size_Applicable in China National Standard (CNS) A4 specification (210 X 297 mm). 409369 Α7 Β7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (9) 2 2 Field oxide film 23 Gate oxide film 24 Photoresist Agent 25a tunnel oxide film 25b gate Chemical film 2 6 Polymer sand layer 2 7 〇 N 0 Film 28 Polymer silicon layer 29 Tungsten (W) silicon compound layer 30 CVDSi〇2 film 31 Photoresist 32 CVDSi〇2 Film 3 3 Photoresist 35 Tungsten silicon compound layer 36 CVDSi〇2 film 3 7 Multi-layer gate 3 8 Select gate 3 9 Gate 4 0 Capacitance [Embodiment]. A first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 to 13. This first embodiment corresponds to the first to sixth aspects of the present invention. This method is a non-volatile notebook paper mixed with EEPR 0 · M, etc. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male a) (Please read the precautions on the back before filling in this page) < M. ill --- order ----- II --- line 409369 A7 B7 V. Description of the invention (10) (谙 Please read the Note § on the back and fill in this page first) Billion grid and MO S Manufacturing method of crystal semiconductor device. The non-volatile memory cell has a dielectric barrier film, a floating gate and a multi-layer gate that controls the gate layer on the oxide film of the tunnel, and a selection gate formed by selecting a desired high-voltage transistor of the multi-layer gate. The charge is forcibly injected after passing through the tunnel oxide film, and the critical threshold voltage of the multi-gate transistor is controlled. In other methods, there is a case where a circuit that generates a high voltage formed by a high-voltage transistor and further controls it is built in. The method of the present invention is particularly characterized by the formation method of the gate electrode, so the formation of the well-known channels, sources, and drain electrodes in the effective field is omitted. The first figure is the formation on the surface of the semiconductor substrate 1 Top view of the field oxide film 2, the thicker gate oxide film 3, and the tunnel oxide film 4. Fig. 2 is a cross-sectional view taken at a part II shown in Fig. 1. At this stage, in the semiconductor substrate 1, the source of the transistor, the drain and the multilayer gate, and the channel of the selection gate and the MOS transistor have been formed as the memory, but in order to maintain the clarity of the drawing, Not shown. • Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Initially, a field oxide film 2 and a thicker gate oxide film 3 were formed by thermal oxidation. The thickness of the field oxide film is 45.0 nm, and the thickness of the gate oxide film is, for example, 41.5 nm. Next, using a mask, the gate oxide film 3 corresponding to the position of the tunnel oxide film 4 corresponding to the non-volatile memory and the gate oxide film 5 corresponding to the gate circuit oxide film 5 of the logic circuit was removed by etching to form a 10 nm thickness. The tunnel oxide film 4 and the cathode oxide film 5 of the MOS transistor. In Figure 2, the area i is the area of the non-volatile memory cell 'area ii is the area of the MOS transistor. Secondly, the third picture is a comprehensive 13 of the polymer silicon layer 6 stacked on the substrate. This paper size applies the Chinese national standard (CNSXA4 specification (210 X 297 public love)) 409369 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (11) As a diagram of the first conductive layer. Secondly, the polymer silicon layer 6 which constitutes a nonvolatile memory gate of a floating gate is separated. The fourth figure shows the removal of the polymer silicon layer 6 at a predetermined position by etching. The top view of the structure. Fig. 5 is a cross-sectional view taken at the position V shown in Fig. 4; this cut line is orthogonal to the cut line in Fig. 1. It shows the etching of the polymer silicon layer 6 A trench is formed after the predetermined position of the trench, and the field oxide film 2 is exposed at the bottom of the trench. Thereafter, the trench is formed only in the X direction perpendicular to the Y direction formed by extending the control gate. If this trench is not formed, the subsequent In the process, if the control gate is extended without forming a cut, the floating gate cannot be separated. Next, FIG. 6 is a cross-sectional view showing the formation of a first insulating film on the polymer silicon layer 6. The polymer silicon layer 6 Above, it is composed of three layers of Si 〇2, Sia N 4 and Si 〇2 (to (Referred to as ΝΟΟ film) to form an insulating film 7. Fig. 7 is a cross-sectional view showing that a second conductive layer is formed on the first insulating film 7 or more. A polymer silicon layer 8 is deposited as a second conductive layer. A cross-sectional view cut at a position V corresponding to FIG. 4 in a state where the polysilicon layer 8 is formed. FIG. 9 is a top view showing that a control gate is provided at a portion corresponding to a multilayer gate. Fig. 10 is a cross-sectional view cut at the portion X shown in Fig. 9. It shows that the insulating film 10 is formed on the entire surface of the polymer silicon layer 8; A mask is provided on the electrode portion; the second insulating film 10, the polysilicon layer 8 and the first insulating film 7 'except the portion corresponding to the multilayer gate are removed by reactive ion etching to form a polysilicon layer (control gate ) 11. The size of this paper is in accordance with China National Standard (CNS) A4 specification (210 * 297 mm) ΤΤ2ΓΤ-1 ^ ---- Γ-l · ^. ----- Order,- --.---- Line S ... (Please read the note on the back before filling in this page> 4093C9 A7 A7 B7 V. Description of the invention (12) The edge film 1 2 * reactive ion etching is comprehensive, and the side wall 13 is formed on the side of the control gate 1 1. Second, using this side wall, the polymer silicon layer 6 is etched, so that it is self-integrated and becomes nonvolatile. Part of the multi-layer gate 9 is the floating gate 14. When the floating gate 14 is etched, the non-volatile memory gate of the selective gate 16 and the gate of the M 0 S transistor can be formed at the same time. Electrode 17. Firstly, an insulating film 15 is deposited, and then a mask is provided on a portion of the gate electrode corresponding to the nonvolatile gate electrode and the MOS transistor. Using this mask, the insulating film 12 and the side wall 13 as an etching mask, the insulating layer 15 and the polymer silicon layer are etched. Therefore, the selection of a non-volatile memory cell is formed simultaneously with the floating gate 14 and the gate electrode 16 of the MOS transistor and the gate electrode 17 of the MOS transistor. Then, the mask corresponding to the position of the selection gate of the nonvolatile memory cell and the gate of the M 0S transistor is removed. Then, the source and the drain of the selection gate and the MOS transistor are formed in a known method. Fig. 11 is a sectional view of a semiconductor device manufactured by this method. i indicates a non-volatile memory cell field, and i i is a MOS transistor field. 'Self-integrated floating gate 14 forming a non-volatile memory cell, and using the control gate portion of FIG. 9 (that is, the first insulating film 7, the control gate 11, and the second insulating film 10) as a mask, The polymer silicon layer 6 is etched to form a floating gate. At this time, the same method as described above can be used to simultaneously form the non-volatile memory cell gate electrode 16 and the gate electrode 17 of the MOS transistor. Figure 12 shows the top view of a semiconductor device made by this method. Figure 13 is a cross-sectional view cut at the part XIII shown in Figure 12 "This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please note on the back of Mtl first Please fill in this page for further information)-^ -------- ^. · II I- II --- Φ: Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 409369 A7 _ ^ __ B7____ V. Description of Invention (13 As mentioned above, according to the present invention, a thin oxide gate oxide film 5 of a MOS transistor can be formed together with a tunnel oxide film 4 of a non-volatile memory multi-layer gate 9; The floating gates 1 ′ 4 of the gate 9 do not increase the number of processes and make the gates finer. A second embodiment of the present invention will be described with reference to Figs. This embodiment corresponds to the seventh and eighth embodiments of the present invention, and is a manufacturing example of a non-volatile memory cell with a multi-layer gate structure, a MOS transistor with a logic circuit, and a semiconductor device having a resistor and a capacitor. . Regarding the formation of the gate of the non-volatile memory cell and the gate of the MOS transistor, the formation of the lower active area: the channel or the source, and the formation of the drain are well known, so the description is omitted. FIG. 14 is a cross-sectional view showing the formation of a field oxide film and a gate oxide film on the semiconductor substrate 21. FIG. On the surface of the semiconductor substrate 21, a field oxide film 22 with a thickness of 450 nm and a thick gate oxide film 23 with a thickness of 41.5 nm are formed by thermal oxidation. At this stage, the source, drain, and multilayer gates of the non-volatile memory multi-layer gate have been formed on the semiconductor substrate 21; the channel area of the gate and the M 0s transistor is selected, so the illustration is omitted. Next, FIG. 15 is a sectional view showing a gate oxide film 23 using a photoresist to remove a part of the gate electrode of the MOS transistor corresponding to the multilayer gate of the nonvolatile memory cell and the logic circuit. . Using photoresist 24, wet etching is used to remove the tunnel oxide film 2 5a of the multilayer gate of the nonvolatile memory cell and the gate oxide film 2 5 b of the MOS transistor of the logic circuit. Gate oxide film 2 3 · This paper size applies to Chinese national standard (CNS > A4 specification (210 X 297 mm) (please read the precautions on the back before filling in this page)-，. 袭 --- 丨 丨 丨Order II II _ 丨 一! Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -ΊΟ-Printed by the Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economy 409369 A7 __- _ V. Description of Invention (14) Then, No. 1 6 The figure is a broken p-shaped picture of the tunnel oxide film 2 5 a forming a non-volatile memory multi-layer gate and a gate oxide film corresponding to a part of the gate of the M OS transistor of the logic circuit. Remove the resist 24. After the necessary cleaning process, thermal oxidation is performed to form a tunnel oxygen oxide film 25 with a thickness of 10 nm and a gate oxide film 25b of the MOS transistor. Then, as shown in FIG. The entire surface of the film forms a polymer silicon layer 26 with a thickness of 250 nm. Phosphorus is doped and the polymer silicon layer 26 has The predetermined conductivity is used as the first conductive layer. At this time, the generated phosphorous glass is removed with a hydrogen fluoride acid solution. Then, as described above, a predetermined portion of the polymer silicon layer 26 is removed by dry etching, and a floating gate is performed. Secondly, as shown in FIG. 18, a 100 nm film of Si 〇2 with a thickness of 10 nm, Si 3N with a thickness of 10 nm, and a SiO 2 film with a thickness of 5 nm are formed. 27: S i 〇2 is formed by heating, S i3N4 is formed by CVD method; a polymer silicon layer 28 with a thickness of 250 nm is formed thereon, and phosphorus is doped to make it have a predetermined conductivity as a second conductive layer. At this time, the phosphorous glass produced on the surface is removed with a hydrofluoric acid solution. After necessary cleaning processes, a metal silicide layer having a thickness of 150 nm is formed on the polymer silicon layer 28 by sputtering, in this example. Then, a tungsten (W) silicide layer 29 with a thickness of 150 nm is formed. * Furthermore, a Si02 film 30 (hereinafter, referred to as a CVDSi02 film) with a thickness of 23 Qnm is formed by a CVD method thereon. Next, as shown in FIG. 19 As shown, a photoresist 3 is provided at a predetermined position in order to form a non-volatile multi-layer gate and capacitor. 1. Based on this paper standard. Applicable to China's national standard (CNS > A4 specification (210 X 297 mm) T7 _. ------ ^ ------- Order ·· ---, " !! Line «Please read the precautions on the back before filling in this page) 409369 A7 _ B7 V. Description of the invention (15) Dry etching removes CVDSi02 film 30, W silicide layer 29, polysilicon layer 2 8 And ONO film 27. In this section, the upper structure of the multilayer gate and the multilayer structure for capacitors are formed. Then, after removing the photoresist 31, a CVDS iO2 film 32 having a thickness of 170 nm is formed over the entire surface as shown in FIG. 20. Secondly, as shown in FIG. 21, a photosensitive anti-solubilizer 33 is provided at a position corresponding to the capacitance and resistance, and the CVDS i 〇2 film 32 is removed by dry etching. By dry etching, multiple layers of the CVDSi02 film 32 are exposed. The side wall 34 is formed on the side wall of the gate structure's upper structure, but the side wall is not formed on the capacitor portion and the resistance portion covered with the photoresist 33. Next, the resist is removed, and after necessary cleaning processes, as shown in FIG. 2, a metal silicide layer is formed on the entire surface. In this example, a W silicide layer 35 of 15 nm is formed by a sputtering method: A CVDS 102 film having a thickness of 23 nm is formed thereon by a CVD method. Finally, a photoresist is provided on each of the positions corresponding to the gates of the M 0 S transistor that selects the gate and logic circuit on the CVD Si 02 film 36, and the lower part of the photoresist is removed by dry etching. Except for the CVD Si 2 film 36, the boundary silicide layer 35, and the polymer silicon layer 26, the photoresist is removed. As a result, as shown in FIG. 23, (1) formation of a polymer sand layer (floating gate) 2 6, a 0NO film 27, a polysilicon layer (control gate) 2.8, W silicide 29 and pVDS were formed. i 〇2 film 30 of the multi-layer gate 37, and the polymer silicon layer 26, W silicide layer 35, and CVDS i 〇2 film 36 formed non-volatile gate 8 8 billion Physique; (2) Formed with polymer silicon layer 26, W silicide layer 3 5 and this paper size is applicable to Chinese National Standard (CNS) A4 Regulations < 210 X 297 mm) < Please read the note on the back first Please fill in this page again for the items), install · ---- I i 丨 Order.i — L ----- Printed by the MK Industrial Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 409369 A7 _ B7 V. Description of Invention (16 > CVDS i 〇2 film 3 6 gate of MOS transistor 3 9 9 (3) Simultaneously formed with polymer silicon layer 26, 0. NO film 27, polymer silicon (Please read the precautions on the back before filling this page) Capacitance 40 formed by layer 28, W silicide layer 29, CVDSi02 film 30 and CVDSi02 film 32; and (4) formed by polymerizing silicon layer 26 and second CVD Si02 film 32 Resistance 4 1 〇 As can be understood from Figure 2 ^, the multilayer gate The floating gate (polymeric silicon layer) 26 of the electrode 37 is formed by self-integration by using the upper structure of the film 7 or more and the side wall 34 formed on the side as a mask. In a well-known method, a selection gate and a source and a drain of the M 0 S transistor are formed. Fig. 24 shows a cross-sectional view of a semiconductor device manufactured by this method. In Fig. 24, ch indicates In the channel, d indicates the drain and 8 indicates the source. However, the structure of the conduction, the source, and the drain below each gate of the semiconductor device shown in FIG. 13 is the same as that of FIG. 24, and the illustration is omitted. The print by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Cooperative Cooperative has been changed to the second embodiment shown in Figs. 14 to 23, and a third embodiment in which the metal silicide layer is omitted may be adopted. The third embodiment is equivalent to this The ninth embodiment of the invention is that in the third embodiment, the metal silicide layers 29 and 35 are not used when manufacturing MOS transistors with nonvolatile memory and logic circuits and semiconductor devices having resistance and capacitance. The poly silicon layer 26 and the poly silicon layer 28 can be used as electrodes. In the case where there is no formation process of W silicide layers 29 and 35, the polysilicon layer is fabricated as shown in FIG. 25 at the position corresponding to the non-volatile gigabyte, MOS transistor, capacitor, and resistance. 26. 〇ΝΟ film 27. Polymerization of this paper is applicable to China's standard < CNS> A4 size (210 X 297 mm) 409369 Α7 Β7 5. Description of the invention (17) Silicon layer 2 8 and CVDS i 〇2 film 3 0 layered structure. Fig. 25 is a stage corresponding to Fig. 19 corresponding to the second embodiment. Then, as shown in FIG. 26, a CVDS i 〇2 腠 32 2 is formed on the entire structure, and the CVDS i 〇2 film 3 2 in the lower electrode area and the resistance area where the capacitor is left is completely changed. The side wall 34 may be formed on the side surface of the upper structure of the multilayer gate by the square etching. Fig. 26 is a diagram showing stages corresponding to Fig. 21 corresponding to the second embodiment. In this way, floating gates can also be self-integrated. The subsequent processes are the same as those of the second embodiment. [Industrial Applicability] As explained above, according to the present invention, when a semiconductor device having a non-volatile memory cell and a logic circuit is manufactured, the first conductive layer (except for the field where the floating gate is separated) remains ( Polymerized silicon layer 6), so surface flatness is maintained. Therefore, processing of the subsequent processes such as the etching process of the second conductive layer becomes easy, the dimensional accuracy can be improved, and the size can be reduced.
由於在進行蝕刻邏輯電路的閘極電極時不須要過剩的蝕刻 處理，所以能形成更微細的閘極電極。進而，可以將不揮 發性記憶格的多層閘極之隧道氧化膜，及邏輯電路的 MO S電晶體之閘極氧化膜形成更薄；另外用可以自我整 合地形成多層閘極的浮動Μ極，所以能提高混載有 E E P R 0Μ等不揮發性記億格及MO S電晶體之半導體 裝置的尺寸精度，且可以使微細化提昇。另外由於可以在 2層的導電層形成多層閘極構造及單一閛極構造之MO S 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (諝先W讀背面之注t事項再填窝本頁) M -------訂-i 丨 L-----線、 經濟部智慧財產局MK工消费合作社印製 409369 A7 _B7 ___ 五、發明說明（18) 電晶體、電阻、電容，所以能減少製程，且與類比電路的 易 容 爲 變也戴 1置 混 (請先W讀背面之注意ί項再填笃本頁) !—訂 Γ--『I 線 經濟部智慧財產局員工消费合作社印製 -ΖΊ - 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐）Since an excessive etching process is not required to etch the gate electrode of the logic circuit, a finer gate electrode can be formed. Furthermore, the tunnel oxide film of the multilayer gate of the non-volatile memory cell and the gate oxide film of the MOS transistor of the logic circuit can be formed thinner; in addition, a floating M electrode that can form a multilayer gate by itself can be integrated, Therefore, it is possible to improve the dimensional accuracy of a semiconductor device in which non-volatile terabytes such as EEPR 0M and MOS transistors are mixed, and it is possible to improve the miniaturization. In addition, because the MOS of a multi-layer gate structure and a single pole structure can be formed on two conductive layers, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (谞 Read the note on the back first Matters will be refilled on this page) M ------- Order-i 丨 L ----- line, printed by MK Industrial Consumer Cooperative of Intellectual Property Bureau of Ministry of Economic Affairs 409369 A7 _B7 ___ V. Description of Invention (18) Electricity Crystals, resistors, and capacitors, so it can reduce the process, and it is also mixed with the analog circuit's easy-to-change capacity (please read the note on the back before filling this page)! — Order Γ-『I line Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-Ί Ί-This paper size applies to Chinese National Standard < CNS) A4 (210 X 297 mm)