經濟部中央標準局員工消費合作社印製 408376 44S2twf.d〇c/006 A7 B7 五、發明説明（/) 本發明是有關於一種金氧半電晶體的製造方法，且特 別是有關於一種於自行對準金屬矽化物製程（Self-aligned Silicide Process ; 簡稱 Salicide Process) .中 可避免窄線效應（Narrow Line Effect)之金氧半電晶體 的製造方法。 隨著複晶矽閘極電極尺寸的日漸縮小，在進行自動對 準金屬矽化物製程時，會產生窄線效應，特別是以矽化鈦 (TiSn)金屬更爲嚴重。所謂窄線效應係由於閘極電極尺 寸太小，在複晶矽閘極電極上之金屬矽化物的成長會因金 屬矽化物與複晶矽接觸的應力（Stress)太大，或是成核 位置（NucleationSite)太少，造成TiSid$ X比例有所 改變，導致金屬矽化物薄膜品質不佳，致使片電阻增加， 而影響閘極電極操作的效能。 因此，本發明提供一種金氧半電晶體的製造方法，包 括：提供一基底，其上已形成閘極電極，且閘極電極兩側 的基底中已形成第一摻雜區；接著於閘極電極兩旁的基底 上形成介電層，並於閘極電極側壁形成間隙壁，再以間隙 壁爲罩幕，將介電層圖案化。續剝除間隙壁，以暴露出介 電層做爲閘極電極和第一摻雜區轉角處的保護層，之後進 行自行對準金屬矽化物製程，以於第一摻雜區和閘極電極 所暴露出的表面形成金屬矽化物層。 依照本發明的一較佳實施例，其中在剝除間隙壁之 前，更包括以間隙壁和閘極電極爲罩幕，進行植入製程， 以於基底中形成第二摻雜區，而第二摻雜區和第一摻雜區 3 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） 408376 4482twf.d〇c/006 ^ B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（l) 構成源極/汲極區。其中介電層的材質不同於間隙壁的材 質，而金屬矽化物層的材質包括矽化鈦。 由於本發明在進行自行對準金屬矽化物的製程中，部 份閘極電極的側壁亦與金屬發生矽化反應，因此增加矽化 金屬成核的空間，故可以避免窄線效應。而閘極電極和摻 雜區轉角處的保護層，可以避免閘極電極和摻雜區之間短 路的情況發生。再者，由於本發明之閘極電極表面的金屬 矽化物，不僅形成於其上表面，其部份側壁亦有金屬矽化 物形成，故可以有效降低閘極電極的電阻。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，.作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1D圖係繪示根據本發明較佳實施例之一 種金氧半電晶體的製造流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 100 ··基底 104 :閘極氧化層 106 :複晶矽閘極電極 102、114 :摻雜區 122 :源極/汲極區 108、108a、108b :介電層 120 :厚度 110 :間隙壁 4 - : *---0¾-- (請先聞讀背面之注$項再填寫本頁) 、τ 本紙張尺度適用中國國家梯準（CNS ) A4^ ( 210X297公釐） A7 B7 408376 4482twf.doc/006 五、發明説明（i) U6a、116b :金屬矽化物層 實施例 第1A圖至第id圖所示，爲根據本發明一較佳實施例 之一種金氧半電晶體的製造流程剖面圖。 首先請參照第1A圖，提供一棊底1〇〇 ’比如是半導體 矽基底，於基底1〇〇上依序形成己完成圖案化之閘極氧化 層104和複晶矽閘極電極106，再以複晶矽閘極電極1〇6 爲離子植入罩幕，以於複晶砂閘極電極106兩側下方的基 底100中形成摻雜區102，比如裹較低濃度的摻雜區’所 摻雜的離子端看欲形成之金氧半電晶體爲N型或P型而 定。之後，於複晶砂聞極電極1〇6上形成一層已平坦化的 介電層108，其平坦化的方法比如晏化學機械硏磨法，其 材質比如是氧化矽。 接著請參照第1B圖，剝除部份介電層108 ’至其剩餘 的厚度120約爲1500埃至3000埃，以形成如圖示之介電 層108a，其剝除的方法比如是非等向性的回蝕刻製程。續 於複晶砍閘極電極106的側壁形成間隙壁丨10，其材質須 異於介電層108a，間隙壁110的材質比如是氮化矽。 接著請參照第1C圖，以複晶矽閘極電極106和間隙 壁110爲罩幕，蝕刻介電層l〇8a，以形成如圖所示之介電 層108b，再以複晶矽閘極電極106和間隙壁110爲離子植 入罩幕，於基底1〇〇中形成摻雜區114，比如是較高濃度 的摻雜區，所摻雜的離子同於摻雜區102。其中摻雜區102 和114即爲源極/汲極區122。 5 本紙張尺度適用中國國家棣準（CNS ) A4规格（2〗〇X297公釐） -----.J— -Ί---裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作杜印製 4482twt；doc/〇〇6 408376 A7 B7 經濟部中央樣準局貝工消費合作社印製 五、發明説明（y ) . 接著靖參照第ID圖，剝除間隙壁no，其方法比如是 用濕蝕刻法，所使用的蝕刻劑比如是熱磷酸。接著進行自 行對準金屬矽化物製程，其方法比如是於整個基底100結 構表面形成一層金屬層，較佳的是鈦金屬，之後在氮氣的 環境下，於攝氏約650至750度之間進行快速熱製程，使 鈦金屬與矽原子反應’之後移除未反應的鈦金屬，於是鈦 金屬與複晶矽閘極電極106接觸的區域反應形成金屬矽化 物層116a，同時於與源極/汲極122接觸的區域反應形成 金屬矽化物層116b，矽化金屬層116a和116b之較佳的材 質是砂化鈦。另外，複晶砂聞極電極106和源極/汲極區 122轉角處之介電層l〇8b的存在，於上述之自行對準矽化 物製程期間，可以避免複晶矽閘極電極106和源極/汲極 區丨22之間的短路。 在此實施例之閘極電極106的材質係以複晶矽爲例， 然本發明之閘極電極106的材質並不局限於此，非晶矽的 材質亦可以適用，亦可以是任何含矽成份的材質。 由於本發明在進行自行對準金屬矽化物的製程中，閘 極電極106參與反應的區域不只像習知只局限於其上表 面’部份閘極電極106的側壁亦參與反應，因此增加矽化 金屬成核的空間，故可以有效避免窄線效應，因而降低閘 極電;極的電阻，且提高金屬矽化物薄膜的品質，進而提高 閘極電極的操作效能。 本發明的特徵如下： 1.由於本發明在進行自行對準金屬矽化物的製程 6 本紙張適用中囷固家椟準（CNS) A4^ (21()>:297公簸） -----νιΊ_---裝------訂------線 (請先閲讀背面之注11^項再填寫本頁) 408376 4482twf.doc/006 A7 B7 五、發明説明（Γ) 中，部份閘極電極的側壁亦參與和金屬的矽化反應，因此 增加金屬矽化物成核的空間，故可以避免窄線效應。 2.在不造成閘極電極和源極/汲極區之間短路的情況 下，本發明之閘極電極表面的金屬矽化物，不僅彤成於其 上表面，其部份側壁亦有金屬矽化物形成，故可以有效降 低閘極電極的電阻，以提高資料傳輸的速度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ---Τ--Ί--1.---裝------訂------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 408376 44S2twf.d0c / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a gold-oxygen semi-transistor, and in particular to A method for manufacturing a metal-oxygen semi-transistor in a self-aligned silicide process (Salicide Process) for avoiding the narrow line effect. As the size of the polycrystalline silicon gate electrode becomes smaller and smaller, a narrow line effect will occur in the process of automatically aligning metal silicide, especially with titanium silicide (TiSn) metal. The so-called narrow line effect is because the size of the gate electrode is too small, the growth of the metal silicide on the polycrystalline silicon gate electrode will be due to the stress (Stress) between the metal silicide and the polycrystalline silicon being too large, or the nucleation location. (NucleationSite) is too small, resulting in a change in the TiSid $ X ratio, resulting in poor quality of the metal silicide film, resulting in an increase in sheet resistance and affecting the efficiency of the gate electrode operation. Therefore, the present invention provides a method for manufacturing a metal-oxide semiconductor transistor, comprising: providing a substrate on which a gate electrode has been formed; and a first doped region has been formed in the substrate on both sides of the gate electrode; A dielectric layer is formed on the substrate on both sides of the electrode, and a gap wall is formed on the side wall of the gate electrode. Then, the gap layer is used as a cover to pattern the dielectric layer. Continue stripping the gap wall to expose the dielectric layer as the gate electrode and the protective layer at the corner of the first doped region, and then perform a self-aligned metal silicide process for the first doped region and the gate electrode. A metal silicide layer is formed on the exposed surface. According to a preferred embodiment of the present invention, before peeling off the spacer wall, the method further includes using the spacer wall and the gate electrode as a mask to perform an implantation process to form a second doped region in the substrate, and the second Doped region and the first doped region 3 (Please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) M specification (210X297 mm) 408376 4482twf.d〇c / 006 ^ B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (l) Form the source / drain region. The material of the dielectric layer is different from that of the spacer, and the material of the metal silicide layer includes titanium silicide. Since the present invention performs the process of self-aligning metal silicide, the sidewalls of some of the gate electrodes also undergo silicidation with the metal, so the space for nucleation of the silicide metal is increased, so the narrow line effect can be avoided. The protective layer at the corners of the gate electrode and the doped region can prevent a short circuit between the gate electrode and the doped region. In addition, since the metal silicide on the surface of the gate electrode of the present invention is not only formed on the upper surface thereof, but also part of the sidewall is also formed with metal silicide, the resistance of the gate electrode can be effectively reduced. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in conjunction with the accompanying drawings. The detailed description is as follows: Brief description of the drawings: FIG. 1A Figures 1 to 1D are cross-sectional views showing a manufacturing process of a metal-oxide semiconductor transistor according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 100 ·· substrate 104: gate oxide layer 106: polycrystalline silicon gate electrode 102, 114: doped region 122: source / drain region 108, 108a, 108b : Dielectric layer 120: Thickness 110: Spacer 4-: * --- 0¾-- (Please read the note on the back side before filling in this page), τ This paper size applies to China National Standards (CNS) A4 ^ (210X297 mm) A7 B7 408376 4482twf.doc / 006 V. Description of the invention (i) U6a, 116b: Examples of metal silicide layers shown in Figures 1A to 1D are a preferred embodiment according to the present invention A cross-sectional view of the manufacturing process of a metal-oxide semiconductor. First, please refer to FIG. 1A, provide a substrate 100 ′ such as a semiconductor silicon substrate, and sequentially form a patterned gate oxide layer 104 and a polycrystalline silicon gate electrode 106 on the substrate 100, and then The polycrystalline silicon gate electrode 106 is used as an ion implantation mask to form a doped region 102 in the substrate 100 below both sides of the polycrystalline sand gate electrode 106, such as a doped region with a lower concentration. The doped ionic end depends on whether the metal-oxide semi-transistor to be formed is N-type or P-type. Thereafter, a flattened dielectric layer 108 is formed on the polycrystalline sand electrode 106. The planarization method is, for example, a chemical mechanical honing method, and the material is, for example, silicon oxide. Next, referring to FIG. 1B, a portion of the dielectric layer 108 'is stripped to a remaining thickness 120 of about 1500 angstroms to about 3,000 angstroms to form a dielectric layer 108a as shown in the figure. Etching process. Continued from the side wall of the polycrystalline gate electrode 106 is a spacer 10, which is made of a material different from the dielectric layer 108a. The material of the spacer 110 is, for example, silicon nitride. Next, referring to FIG. 1C, using the polycrystalline silicon gate electrode 106 and the spacer 110 as a mask, the dielectric layer 108a is etched to form a dielectric layer 108b as shown in the figure, and then the polycrystalline silicon gate is used. The electrode 106 and the spacer 110 are ion implantation masks, and a doped region 114 is formed in the substrate 100, for example, a doped region with a higher concentration, and the doped ions are the same as the doped region 102. The doped regions 102 and 114 are the source / drain regions 122. 5 This paper size is applicable to China National Standards (CNS) A4 specifications (2〗 〇297297 mm) -----. J— -Ί --- installation ------ order ------ line (Please read the notes on the back before filling out this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs for the printing of shellfish, 4482 twt; doc / 〇〇6 408376 A7 B7 Explanation (y). Next, referring to the figure ID, peel off the spacer no. The method is, for example, wet etching, and the etchant used is, for example, hot phosphoric acid. Next, a self-aligned metal silicide process is performed. The method is, for example, forming a metal layer on the surface of the entire substrate 100 structure, preferably titanium, and then quickly performing a nitrogen atmosphere at a temperature of about 650 to 750 degrees Celsius. The thermal process removes unreacted titanium after reacting the titanium metal with silicon atoms, so the area where the titanium metal contacts the polycrystalline silicon gate electrode 106 reacts to form a metal silicide layer 116a, and at the same time it contacts the source / drain The area in contact with 122 reacts to form a metal silicide layer 116b. The preferred material for the silicide metal layers 116a and 116b is titanium sand. In addition, the presence of the dielectric layer 108b at the corners of the polycrystalline sand electrode 106 and the source / drain region 122 prevents the polycrystalline silicon gate electrode 106 and the polycrystalline silicon gate electrode 106 and A short circuit between the source / drain regions. In this embodiment, the material of the gate electrode 106 is polycrystalline silicon. However, the material of the gate electrode 106 of the present invention is not limited to this. The material of the amorphous silicon can also be applied, and it can be any silicon-containing material. Material of ingredients. Since the present invention performs the process of self-aligning metal silicide, the area where the gate electrode 106 participates in the reaction is not limited to the upper surface of the gate electrode 106 as it is conventionally known. Part of the side wall of the gate electrode 106 also participates in the reaction, so silicide metal is added. The nucleation space can effectively avoid the narrow line effect, thereby reducing the gate resistance and electrode resistance, and improving the quality of the metal silicide film, thereby improving the operating efficiency of the gate electrode. The features of the present invention are as follows: 1. Because the present invention is in the process of self-aligning metal silicide 6 The paper is suitable for use in China (CNS) A4 ^ (21 () >: 297mm) --- --νιΊ _---- install ------ order ------ line (please read Note 11 ^ on the back before filling this page) 408376 4482twf.doc / 006 A7 B7 V. Description of the invention (Γ ), Part of the side wall of the gate electrode also participates in the silicidation reaction with the metal, so the space for metal silicide nucleation is increased, so the narrow line effect can be avoided. 2. Without causing a short circuit between the gate electrode and the source / drain region, the metal silicide on the surface of the gate electrode of the present invention is not only formed on the upper surface, but also part of the side wall is also metal silicided. Material formation, so the resistance of the gate electrode can be effectively reduced to increase the speed of data transmission. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. --- T--Ί--1 .--- install ------ order ------ line (please read the precautions on the back before filling out this page) The paper size printed by the cooperative applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm)