TW407232B - Data transferring/separating controller - Google Patents

Abstract

A data transferring/separating controller is provided for supplying the function of hot swap in Ultra DMA mode, which includes a bus buffer device and a bus command monitoring device. Wherein the bus buffer device is between the host and the peripheral devices, the bus command monitoring device decodes the bus command from the host by a bus command interpreter, then the control signals corresponding to the bus commands are output via a bus controller inclusive of direction signals and enable signals to control the transmission direction and transmission model of the bus buffer devices, and the data separation under hot swap' therefore it confirms the data accuracy between the host and the peripheral devices.

Description

407232

The present invention relates to a data transfer / separating controller, and more particularly, to a method capable of providing a hot swap function in a high-speed direct memory access mode (Ultra DMA Mode). Data transmission / isolation control device. Generally speaking, a peripheral device (device), such as a data storage device such as a driye or a hard disk (HD.hard disk), and a host system such as a computer must be transmitted through a standard interface (丨Data 'and protocols that communicate with each other, such as data transmission and control methods, are called interface specifications. The current disk interface specification commonly used in personal computers is the so-called Integrated Device Interface (Integrated Device). Electronics), and with the acceleration of CPU speed and the increasing complexity of application software, the Enhanced (EIDE) interface is used to replace the traditional IDE interface. Its features include lba (l0gicai block addressing) addressing mode to make storage capacity 3MBps。 Giga listening level, in terms of data transmission speed, the highest transmission speed in Ultra]) ^ mode, it can reach up to 33.3MBps. Generally speaking, data transmission methods include PI0 mode (Pr0gramine (1 I / O mode) and DMA mode (direct memory access). As shown in Figure 13, general peripheral devices 15 such as data storage devices include memory and hardware Disk drives, floppy disks, and other disk drive devices, PI0 mode uses the bus 1: 3 and I / O port 12 to directly use the central processing unit (CPU) to process data. , Instruction codes, or instruction parameters such as non-data (non-data.) Instruction transmission tasks, therefore, before the access action is not completed 'CPU10 0 can not perform other tasks, as for the data transmission rate to

C: \ ProgramFiles \ Patent \ 0356-3759-E.ptd page 4 407232 V. Description of the invention (2) PIO mode 4 (PI0 mode 4) is taken as an example, which is approximately 16. 6MByte per second. As shown in Figure lb, the DMA mode is that the CPU 10 sets some initial settings to the DMA control chip (DMA control ler), and then the DMA control chip Π is responsible for data transmission. Therefore, using the DMA mode can not only reduce the CPU Burden 'can also speed up execution. Another Ultra DMA mode is developed by companies such as Intel. It not only has compatibility with traditional IDE interfaces, but also has built-in (crc: Cyclical Redundancy Check 1 ng) function. Once an error in data transmission is detected, the data is retransmitted, and the data transmission rate of Ui tra DMA mode can be increased from 16.6Mbyte / sec to 33.3Mbyte / sec. The data transmission rate of the original PI0 mode 4 is 16. 6 Mbyte / sec. Its data occurs at the rising edge of the square wave signal, and in the Ultra DMA mode, it uses the rising and falling edges of the (square wave) signal at the same time. Trigger the transmission of data, so the maximum transmission rate is 16.6x2 =: 33.3 Mbyte / sec. As for the main signal names defined in the current interface agreement "^" "卩 ^ 比 ⑶" are shown in Table 1:

407232 V. Description of Invention (3) Table 1

Definition (Description) Host DIR Device signal (acronym) Chip selection CS0-CS1 Data bits DD0-DD15 Peripheral device address bits— > DA0-DA2 DMA approval- > DMACK DMA requirement <-DMARQ interrupt request INTRQ I / O reads DIOR Ultra DMA data input fast # DMA is ready during HDMARDY Ultra DMA data output fast transmission data strobe HSTROBE I / O is ready < r- IORDY Ultra DMA data output fast transmission DMA is ready < r- DDMARDY Ultra DMA data strobe during data input fast transfer DSTROBE I / O write DIOW Ultra DMA data fast transfer terminates STOP and enables host system and peripheral device Perform hot swap without power on, such as removable hard disks commonly used today. The general solution is to insert a buffer into the bus between the main system and peripheral devices. (Bu ff er) to avoid loss of transmission data. For example, as shown in Figure 5, an IDE bus 510 passes through an IDE flat cable.

C: \ ProgramFiles \ Patent \ 0356-3759-E.ptd page 6 __407232 V. Description of the invention (4) 520, 530 can connect two peripheral devices such as IDE disk drive 54, 550 'buffers 600a, 60 0b is set on 11) 1: flat cables 520, 530 'so that CPU50 0 and drives 540, 5 50 can be hot-swapped without power on. However, the conventional DMA mode and the u 1 tra DMA mode cannot control the transfer direction of the aforementioned buffer with a simple read / write signal due to the following differences. (1) As shown in Table 2, as far as the aforementioned conventional technologies are concerned, since the conventional DMA data transfer mode of direct direc.t memory access uses only pure read / write signals (U / W; Read / Write signals) to control the transmission direction of the buffer, but the read / write signals (R / W) have different definitions in the Ultra DMA mode, so dare you ca n’t just use the simple read / write Signal to control the transmission direction of the buffer. Table 2 Definition of read / write signals in traditional mode Definition of read / write signals in Ultra DMA mode PIO read / write (READ / WRITE) Ultra DMA READ Ultra DMA WRITE DIOW STOP STOP DIOR HDMARDY hstrobe IORDY DSTROBE " a-ddmardy _ ------ (2) As shown in Figure '2a, the timing diagram of a conventional DMA read / write mode is as follows. When the peripheral device sends a DMARQ request signal to the main system, and inrai i ^ m C: \ ProgramFiles \ Patent \ 0356-3759-E. Ptd page 7--4072 ^ ¾ ----- V. Description of the invention (5) After the DMACK approval signal is indicated by the main system, it will be in DI〇R / DI〇w At the rising edge of the signal at 21 ', transmission of Vand data DATA is performed. However, the U1 tra DMA mode is different. For example, in the timing chart of U1 tr a DMA read mode in Figure 2b, an input strobe (str0be_in) signal DSTR0BE is included, and the Ultra DMA write in Figure 2c The timing diagram of the mode includes an output strobe (^ 1; 1'〇56 ~ 〇111;) signal 115? 1? 06. Among them, in the aforementioned Ultra DMA read / write mode, in order to double the data transmission, the Ultra DMA read mode in FIG. 21) is based on the input strobe signal 1) 51 < 1? (^ £ of rising edge 22 ( riSing edge) and falling edge 23 (falling edge) respectively for effective data DATA transmission. In the ^^ MA write mode of Figure 2c, the rising edge 24 (rising edge) of the strobe signal HSTR is output. And falling edge 25 (fal 1 ing edge) to transmit valid data DATA, respectively.

(3) Before the end of the aforementioned Ultra DMA mode transfer, whether it is the Ultra DMA read mode in Figure 2b or the UUra DMA write mode in Figure 2c, the main system will be recognized by the main system when the recognition signal DMACK reaches the rising edge 26. Write a piece of CRC error check data to the peripheral device and compare it with the error check CRC data generated by the peripheral device itself to judge the correctness of the transmitted data DATA. However, the traditional DMA mode shown in Figure 2a does not have a 1 ^ timing cycle for writing CRC data. W In addition, it should be noted that in the reading mode in Figure 2b, the reading period of the transmission data DATA and the writing of the CRC data are included. In the write mode, no one belongs to the data transmission due to data DATA & CRC error check.

407232 V. Description of the invention (6) The write cycle, so the data transfer wheel of the two does not have this problem in the traditional DMA mode. ] Β is the same direction. In Figure 2a, therefore, combined with the above, the DIOR / DIOtf signal on the bus to control the data money & amps cannot be transmitted in a separate direction. ... 枓 ... the timing and buffer data are there. The purpose of the present invention is to solve the problem of data transmission / isolation control split, which interprets the bus (commands) to generate corresponding numbers. , And to control the direction and accuracy of data transmission. In order to achieve the above purpose, the present invention provides a data transmission / isolation control device, which provides a hot swap function under the high-speed direct memory access mode (UHra DMa), which includes a bus buffer And a bus instruction monitoring (moni toring) device, wherein the bus buffer device is located between the main system and the peripheral device, and the bus instruction monitoring device decodes the bus instruction from the main system with a bus instruction interpreter , And then output a control signal corresponding to the bus command through a bus controller, including a direction signal and an enable signal, to control the transmission direction, transmission mode, and data isolation of the bus buffering device so as to ensure that The correctness of the data transmission between the main system and the peripheral devices, and can provide a hot swap function in the Ultra DMA mode. 'The following' illustrates the information of the present invention in a diagrammatic manner. An embodiment of transmission / isolation control, where the same reference symbols are used in different illustrations to indicate the same or synonymous elements

C: \ ProgramFiIes \ Patent \ 0356-3759-E.ptd page 9 07232 V. Description of the invention (7) Brief description of the diagram. The diagram shows a kind of data transmission in PI0 mode. Figure lb shows data transmission in a DMA mode. Figure 2a shows the pulse timing of the transmission wheel model ^ A 2 shows the pulse timing of the _tra DMA data read mode Figure 2c shows the ultra DMA data 耷 λ γ j 冩Figure 3 of the pulse wave timing of the branch type shows the data transmission wheel number / isolation control device block of the present invention

Figure Figure Figure Figure Isolation Control Device Figure 4 shows a detailed embodiment of data transmission according to Figure 3. Insert ☆ The fifth. The diagram shows a traditional application circuit that performs a hot swap between the main system and peripheral devices. Fig. 6 shows a detailed embodiment of the data transmission device according to Figs. a Bus monitoring device FIG. 7 is a detailed circuit block diagram of an embodiment according to FIG. 6. [Symbol description] 10 ~ CPU; 13 ~ bus; 12 ~ 1/0 port; 14 ~ memory; 15 ~ peripheral equipment; 11 ~ DMA control chip; 100 ~ main system; 2000 ~ bus Buffer device; 300 to bus command monitoring device; 400 to peripheral devices; 21 to two-way > material buffer unit; 230 to one-way control buffer unit; 212, 214,

C: \ ProgramFiles \ Patent \ 0356-3759-E.ptd page 10 V. Description of the invention (8) 2 3 2, 2 3 4 ~ buffer; 31 0 ~ bus instruction interpreter; 3 3 0 ~ bus Controller; 5 0 0 ~ processor; 5 0 0 ~ I DE bus; 5 2 0, 530 ~ IDE cable; 600a.'600b ~ buffer; 540, 550 ~ IDE drive; CTRL ~ control signal 7 1 0 ~ bidirectional data buffer unit; 7 3 0 ~ unidirectional control buffer unit; 712, 714, 732, 734 ~ buffers; 800 ~ bus instruction monitoring device; 8 0 ~ bus instruction interpreter; 83 〇 ~ bus controller; 817, 850 ~ power controller; 900, 940 ~ power supply; 920 ~ switch; 81 decoder; 812 ~ D type flip-flop; 813 ~ and gate; 814a, 81 6a ~ and gate 814b'817a ~ reverse gate; 814c'buffer; 815 ~ multiplexer; 816 ~ enable signal generator; 81 6a ~ or gate. Embodiment '凊 Refer to FIG. 3, which shows an embodiment of a data transfer / separating controller of the Ricotek, which includes a bus buffering device 2000 and a bus command monitoring Device (bus command monitoring device) 300. Among them, the main system 100 and the peripheral device 400 transmit data through the busbar 200, and the bus buffer device 2000 is located between the main system 00 and the peripheral device 400: the busbar. Λ outside 'Bus command monitoring device 300 is used to resolve the bus command of the autonomous system 100, and output the f signal corresponding to the bus command to control the transmission direction and transfer wheel of the bus buffer device 2000 ^ It is isolated from the data during hot swapping. This can ensure the correctness of data transmission on the main system side. It can also provide hot swapping in high-speed direct memory ^ = mode (Ultr.a DMA mode) (heart month b 0 4

V. Description of the invention

In the isolation diagram, the data transmission device in the embodiment of the present invention includes a bus buffer device 200 and a sink method 300. Among them, the main system 100 and the peripheral device 40 0: use the data bus L1 and the control buses L2 and L3 to input data (data), commands (common), and control (common) signals. , The bus buffer device 200 is inserted into the main system 100 and ^ 210 and a control buffer unit 2 on the control bus L2, u where ΓΓΠί = Γ! Using a bus command interpreter 31 ° to solve指令 The bus commands B1 and B2 from the main system 100 are output, and the bus controller 33 0 generates the control number CTRL corresponding to the bus commands B1 and B2, including the direction signal DIR and the enable signal 〇1 / 〇Ε2 ° system = data transmission direction of the buffer device 200, data isolation of the transmission die. Among them, the direction signal DIR is used to control the data buffer unit 21 to lose the direction of the party. For example, according to the direction signal DIR, the main system 100 can purchase the data of the peripheral device 4GG via 214 5 or the main system 1GQ. The data is written to the peripheral device 400 through 212. The enable signal OE1 / OE2 of the W device is used to control whether the data buffer control buffer unit 230 is enabled or not, for example, according to the enable signal, the input or isolation status is £ 2. If it is in the transmission state, the control buffering buffer "^ 's buffer 234 is transmitted from the main system 100 to the peripheral device (the transmission control means a read / write control)', and the data buffer unit 21 is enabled at 0E1. To perform 7 transfers. However, the peripheral device 400 may directly transmit the control instruction to the main system 100.

— 407232_ V. Description of the invention (10) " '---—— order, no need to control the control signal CTRL enable signal 0E2. For example, please refer to FIG. 6, which is a combination of the present invention of FIG. 4 and the IDE architecture of FIG. 5. Among them, only the bus commands related to the UUra MA mode cannot control the transmission of only one direction with DI0R and 耵 ⑽ signals. Therefore, in all IDE bus commands, it can be related to the old eight-branch type. The bus instructions are separated and processed, and the remaining bus instructions can directly control the transmission direction by using the DIOR and DI0W signals. The data transmission / isolation control device in the embodiment of the present invention includes a bus buffer device 700 and a bus command monitoring device 800. Among them, the main system 5 0 0 and the IDE drive 540 are bidirectional transmission of data signals and control signals through the data bus [I 0 and the control bus L20, L30, such as DD 0 on the data bus L1 0 -D D1 5 signal 'controls the DMARQ / IORDY / INTRQ signal on the bus 12 and the control bus [DIOR / DIOW / CSO / CS1 / DA0-DA2 / DMACK / RESET signal, of which CSO / The CS1 / DAO-DA2 / DIOR / DIOW signals are used to select registers (not shown) in a specific peripheral device, such as an IDE drive 540. In addition, the bus buffer device 700 is inserted between the IDE bus 510 and the IDE disk drive 540, and includes a bi-directional tri-state data bus buffer 710 that isolates the data bus L10 and A unidirectional control buffer unit 730 for isolating the control bus L20, L30. Generally, before executing the bus command, the main system 500 first transmits the bus command to be executed through the data bus L1 0 and the control bus L30.

V. Description of the invention (11) Send to peripheral devices such as IDE disk drive 540. At this time, the bus command monitoring device 800 uses a bus command interpreter 8100 to obtain the data transmitted by the main system 500. , Which contains the bus command (bus command), and then interpret and judge the characteristics of the contained bus command. Then, a bus controller 830, such as a timing generator, is used to generate a control signal corresponding to the bus command CTRL ', which includes a direction signal DIR and enable signals 〇Ει, 〇E2, which are used to make a 1-bus The transmission direction of the buffer device 700 and the data in the transmission mode are isolated. … The direction k number DIR is used to control the two-way data buffer unit. For example, in the data bus L1G, according to the direction signal dir, the main system 500 reads the data of the drive 54 through the buffer 712. Or, the main system 500 writes data to the disk drive 54 through the buffer 714. The enabling signal OE1 is used to control the data buffering unit. * For example, the transmission or isolation I can be selected according to the enabling signal OE2. When the transmission state is on the right, the unidirectional unit 734 of the control buffer unit 73 is enabled. The host system 500 transfers control / read / write control to the disk drive 54) at the same time enables the buffer 712 of the buffer unit 710 or the buffer 5 | 714 & ^ {1 " = # ^ 1 f 枓Write) transfer. According to the information (read / In addition, the power controller 8 5 0 is usually 雷. S 0 η η ω Α is set to a power source 940 like a magnetic disk, and the input should be opened to the peripheral device 920 to form a circuit, and output — Disconnection; ^ p, E swapping ', then use Kaiyu h number OPEN to the bus controller C: \ Program Files \ Patent \ 0356-3759-E, ptd page 14 407232 V. Description of the invention (12) 830 Causing a control signal CTRL corresponding to the hot swap to be used to disable the bidirectional data buffer unit 71 and the unidirectional control buffer unit 730 to isolate the data bus 110 and the control bus L30. Signal. Please cooperate with Figures 2a to 2c, and refer to the detailed embodiment of the bus command monitoring device 800 in Figure 6 shown in Figure 7. The decoder 8 11 is mainly used to control the bus L 3 0. (^ S0 / CS1 / DA0-I) A2 signal is decoded if it belongs to the write bus command code and the data DD0-DD7 on the data bus L10 contains Ultra DMA read When the mode is related to the instruction code, the DMA READ signal output by the decoder 811 is [True], and when the data is within DD0-DD7 series When the Ultra DMA write mode is related to the instruction code, the DMA READ signal output by the decoder 811 is [False] v The D-type delay flip-flop 812 is used to continue the valid period of the dm a READ signal until the end of the DMA period. Among them, the gate 8 丨 3 uses the D 丨 〇w and DMACK signals as inputs to provide the latch clock period of the d-type delay flip-flop 812. For example, the gate 813 can ensure the DMA cycle. Just at the beginning, a latching clock cycle is provided to latch the result [DMA READ signal] decoded and output by the decoder 811 to the D-type delay positive after the command code transmitted in the last PI 0 transmission mode. Inverter 812. _ In addition, according to the reading mode in Figure 2b, the DMA cycle includes a reading cycle with data DATA and a writing cycle with CRC data. The data transmission direction of the two is reverse. Therefore, DM must be used. The READ signal and the DMARQ signal are the sum gate 814a of the input to adjust the direction of the data buffer unit 7 1 0 as shown in FIG. 6, that is, the reading direction is changed to the writing direction, so that the main system C: \ ProgramFiles \ Patent \ 0356-3759-E.ptd page 15 Explanation (13) The system 500 writes the CRC data to the disk drive 540. The multiplexer 815 is used to switch the ρmode (the input dI0r signal of the back gate 814b) and the DMA mode (and the input DMA READ of the gate 81 4a) Signal), and the DMACK signal is delayed (de 1 ay) through the buffer 814c and used as a control signal for switching the p I 0 mode and the D μ A mode. · As for the output of the enabling number generator 816, the output of the anti-gate 817a and the gate 816a is used as the input of the OR gate 816b. Among them, the input end face of the anti-gate 81 7a is connected to the power control unit 817, and the power control unit 817 is used. In order to control the power supply to the peripheral devices, the DI OR read signal, DIOW write signal, and DMACK of the approved number k are the input terminals of the gate 81 6a. Therefore, only the power control unit 8 1 7 remains on (the power of the peripheral device). ), And when one of the D 丨 〇R read signal, the DI0W write signal, and the acknowledgement signal DMACK is active, or the gate 816b outputs the enable signal 〇El to the buffer unit 710, otherwise maintain high impedance (high impedence) ) Status, does not affect another connected disk drive 550 (Figure 5) on the IDE bus, the same, or the gate 817b when the power control unit 817 remains on, the output signal is enabled 〇E2 to the buffer unit 7 3 0 'Otherwise the high impedance (highimpedence) state is maintained. According to the detailed embodiment of FIG. 7 described above, the following functions can be performed: The bus instruction is a DMA read related instruction. When the DMA read related instruction is decoded by the demodulator 811, the DMA READ p number is [True] 'and this signal Will be latched in the d-type flip-flop gig, and at the beginning of the DMA cycle, the direction signal DIR of the buffer is switched from the multiplexer 81 5 to the output of the gate 81 4a (DMA mode). During the read cycle of transferring data DATA, the DMA READ signal is [True] for reading

May Day's invention explains Hu's side ----take direction, but when the DMA cycle is about to end, such as entering the CRC data write cycle, when the acknowledgement signal DMACK is pulled up, the host system will write a crc error check data to the peripheral device ' The DMARQ signal is pulled down before the DMACK signal is pulled up, so the DMARQ signal and the [True] DMA READ signal pass through the output DMA READ signal of the gate 814a to [False] and change to the writing direction. The bus instruction is a DMA write related instruction. When the decoder 8 11 decodes the DMA write related instruction, the DMA READ signal is [False]. At the same time, this signal will be latched in the ρ-type flip-flop η. Figure 2c shows that the entire DMA cycle remains in the write direction and has not changed. Therefore, at the beginning, when the data DATA write cycle is transmitted, the DMA READ6 number is [False] representing the write direction, and when the DMA cycle is about to end, such as entering the CRC data write cycle, the DMARQ signal and the [False] DMA The output of the READ signal through the gate 8i4a is still [False], so the writing direction remains unchanged. · The bus instruction is other instructions. When the decoder 8 11 decodes an instruction code that is not related to DMA, such as p 丨 〇 mode, the direction signal DIR is controlled by the multiplexer 815 through the reverse gate 8141) to select the DI0R signal. To sum up, both the PI0 transmission mode and the DMA transmission mode can be performed by the data transmission / isolation control device of the present invention. It can not only use the = monitoring device to output the control signal corresponding to the bus command, but also I To the signal and the enable signal to control the transmission side of the bus buffer device σ] mode and the data isolation during hot swap, so it can ensure the main

__407232 V. Description of the invention (15) The correctness of data transmission between the system and peripheral devices, and can provide hot swap in high-speed direct memory access mode (ultra DMA mode) without affecting the data transmission rate ( h〇t swap) function, and its application is used in storage devices such as RAID disk arrays (Redundant Arrarys of Inexpensive. Drives). Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

C: \ ProgramFiles \ Patent \ 0356-3759-E. Ptd page 18

Claims (1)

范围 6. Scope of applying for patents 6. Scope of applying for patents 丨 1. f. Material transmission / isolation control device, including on the bus between the system; and at least one peripheral device-a bus command monitoring 奘Stop multiple rows of instructions and generate a corresponding transmission direction and transmission mode that control the bus 3 on the bus ^ 'erleM controls the bus buffer installation u- 丄 style and implementation of hot swapping Dazzling red: The command monitoring device includes: the device described in 'wherein the bus is a bus buckle order interpreter that receives the above-mentioned translated output; and, τ M resolves a bus controller based on the bus The rotation of the instruction interpreter generates a control signal corresponding to the above-mentioned bus instruction. '3. The device described in item 2 of the patent scope, which includes-a power controller that outputs a disconnection signal to the bus controller when performing a hot swap, so that a pair of hot swaps should be generated The state control signal is used to inhibit the bus buffer device. 4. The device described in item 2 or 3 of the scope of patent application, wherein the bus includes at least-data bus and at least 〆 control bus. 5. The device according to item 4 of the scope of patent application, wherein the data bus includes a two-way data bus. 6. The device described in item 5 of the scope of the patent application, wherein the control bus includes a one-way control bus from the peripheral device to the main system, and one from the main system to the peripheral device. The second one-way control of the direction is the 19th purchase. 6. The scope of the patent application. 6. The scope of the patent application. 丨 1. The f material transmission / isolation control device includes the bus between the system and at least A peripheral device — A bus instruction monitors multiple instructions, and generates a corresponding transmission direction and transmission mode that controls the bus 3 on the bus ^ 'erleM controls the bus buffer device u- 丄Auntie style and implementation of hot swapping: The command monitoring device includes: The device described in 1 wherein the bus is a bus buckle order interpreter that receives the above-mentioned translated output; and, τ Μ A bus controller is solved, and a control signal corresponding to the bus instruction is generated according to the rotation of the bus instruction interpreter. '3. The device described in item 2 of the patent scope, which includes-a power controller that outputs a disconnection signal to the bus controller when performing a hot swap, so that a pair of hot swaps should be generated The state control signal is used to inhibit the bus buffer device. 4. The device described in item 2 or 3 of the scope of patent application, wherein the bus includes at least-data bus and at least 〆 control bus. 5. The device according to item 4 of the scope of patent application, wherein the data bus includes a two-way data bus. 6. The device described in item 5 of the scope of the patent application, wherein the control bus includes a one-way control bus from the peripheral device to the main system, and one from the main system to the peripheral device. The second one-way control of the direction is the 19th purchase. 6. The scope of patent application. The bus buffer 7 is equipped with the device described in item 6 of the patent scope, in which the bus is provided with a transmission-data-control buffer 'located on the first unidirectional control bus to transfer material; a data buffer unit located in the Two-way data input control instruction; and control: ί: the control buffer is located on the second unidirectional control bus to transmit the unit described in item 7 of the patent scope, wherein the direction of the data is: i Ϊ 料A buffer for transmitting the direction from the peripheral device to the main system Ϊ Ϊ: a material buffer for transmitting the device described in item 8 of the 9-series range from the main system to the peripheral device, wherein the power supply The first data buffer / second data} M and the second control buffer are 'banned' during the material control buffer swap. The controller produces the device described in item ^ of the small patent range, wherein the direction of the bus transport direction ㈣ 'is used to transfer the data buffer unit to the device described in item 7 of the product range. The second control slow signal of the bus bar, the material buffer unit and the old punch are in a transmission / isolation state. 6. Scope of patent application 12. —A kind of data transfer wheel / isolation control-bus buffer device, located in the “set”, which includes: IDE bus between the ;; — the main system and at least one peripheral device a bus instruction An interpreter that outputs the bus command and interprets it; and the bus-to-bus controller from the I bus, which is secretly generated, and the output is determined according to the bus command, +, and interpreted according to the bus command The output of the device generates the protection sister corresponding to the other bus command, the transmission direction of the bus buffer device, and the transmission === beat to control the bus isolation. Transmission mode and information during the implementation of hot swap. The device described in item 12 of the scope of the patent application, in which the multi-power controller is used to output a disconnection message when the hot swap is performed. Device to generate a pair of control signals u which should be hot-swappable to inhibit the bus buffer device. 14. The device according to item 12 or 13 of the scope of patent application, wherein the IDE bus is compatible with DMA transmission mode, Ultra DMA transmission mode and P10 transmission mode. 1 5. The device according to item 14 of the scope of patent application, wherein the peripheral device includes at least one data storage device. 16. The device described in item 15 of the scope of patent application, wherein the data storage device is a disk drive. 17. The device according to item 15 of the scope of patent application, wherein the data storage device is a RAID disk array.