TW406270B - A charge pump circuit includes a plurality of pumping units connected - Google Patents

Abstract

A charge pump circuit includes a plurality of pumping units connected between a first voltage source and an output terminal, the pumping unit comprising a transistor having a bulk of a floating condition in which active regions of the transistor are formed, and a plurality of discharge transistors connecting the bulks of the transistors to a second voltage source in response to a first control signal. The circuit also provides a precharge transistor connecting the output terminal to a third voltage source in response to a second control signal. The circuit is employed for generate positive and negative high voltages on a nonvolatile memory.

Description

2832pif.doc / 002 406270-V. Description of the invention (I) The present invention relates to a semiconductor memory having a charge pump circuit, and in particular to a method for utilizing a charge pump circuit Semiconductor memory that generates high voltage, such as flash electrically erase and program in read only memory. In the current development trend of portable computers, there is an increasing demand for reduced power supply. In order to reduce the waste of power, the integrated circuits in most personal computers are redesigned to meet the requirements of low voltage. Generally, the operating voltage of circuits or components in portable computers is designed to be about 5V, or 3.3V or lower, to reduce the power required by such computers. Unfortunately, some components in portable computers require high voltage. For example, in recent portable computers, flash EEPROM is used to store the basic input / output system (Basic Input / Output System; BIOS). )data. When you want to change the basic input / output system (BIOS) data, this flash read-only memory can be erased and programmed as long as you perform a small update program without removing it from the computer. action. However, erasing and programming of flash read-only memory requires more than 10V to complete effectively. Such high voltage cannot be provided by ordinary low-voltage portable computers. In some other areas of electrical arrangements, the function of the charging pump circuit is usually used to provide a high voltage from a low voltage source. The method of using the charging pump circuit to generate the cylinder pressure was disclosed in the 1976 journal "IEEE Journal of Solid State Circuit" in Vol. SC-11, pages pp.374-378, and titled " 〇n-chip High- (Please read the note ^ h on the back before filling this page) This paper size applies to Chinese national standards (CNS > A4 size (210X297 mm) 2832pif.doc / 002 406270 at __B7 V. Invention Explanation (2) Figure 1 in the “Voltage Generation In NMOS Integrated Circuit” (please read the precautions on the back before filling this page). The pump operation in the circuit is described in this conventional technique, which will be connected in series. A plurality of pump units, and the pump unit is composed of a plurality of capacitors C1-Cn. And a plurality of NMOS strengthening transistors MN1-MNn (enhancement transistors) are selected. Each strengthening transistor is located between the node N1 and the output terminal Between T1, node N1 is connected to the source voltage Vcc through a precharging transistor MNO (precharging transistor), and the output terminal T1 can generate a high pumping voltage Vpp (pumped voltage). The gate and sink of the transistor in the above-mentioned pump unit Extremely straight Connected to the capacitor, and the source is connected to the gate and the drain of the next transistor, and the base of the transistor MNl-MNn is kept grounded. The pump unit can alternate according to the pump timers P1 and P2 (pumping clocks) Timers P1 and P2 have complementary phase differences. As shown in Figure 2, timer P1 is applied to even-numbered capacitors C1, C3 ..., and timer P2 is applied to odd-numbered capacitors C2, C4 .... If yes The state of timer P1 is set to high, and the state of timer P2 is set to low. In the initial state, once the memory element is powered, node N1 is charged at the voltage Vcc-Vth, where Vth is the voltage of transistor MN0. Threshold voltage. Corresponding to the rise and fall of timers P1 and P2, the voltage level from N2 to T1 will gradually increase until it reaches Vpp. This voltage Vpp is required to complete erase and programming The voltage VSB between the source and the substrate will gradually increase when using the circuit structure in Figure 1 to charge the pump, and it will reach the starting voltage of the transistor, so the source voltage will rise. High, while the voltage of the substrate is still connected to isr *, this is called integral Body effect. Please refer to Figure 3. The 5 paper sizes of the source to the base are applicable to China National Standard (CNS) A4 (210X297 mm) 2832pif.doc / 002 40 627〇A? V. Invention Explanation (,) The voltage VSB gradually increases from OV to 3V, so that the voltage of the gate-to-source will also move, from 0.8V to 1.3V, because the zero reference point of the drain-to-source current Ids. And the starting voltage Vt increases as the curve increases in proportion to the voltage VSB. Such a shift of the starting voltage Vt will reduce the efficiency of the pump charging, resulting in the inability to obtain a high voltage (or pump voltage) for erasing and programming in a low voltage memory element. In view of this, the main object of the present invention is to propose a semiconductor memory with a charging pump circuit, which can further enhance the boosting efficiency. Another object of the present invention is to propose a charging pump circuit The semiconductor memory can avoid the overall effect. Another object of the present invention is to provide a semiconductor memory having a charging pump circuit. After the pump is charged, the substrate voltage will drop to a predetermined voltage quickly. Another object of the present invention is to provide a semiconductor memory having a charging pump circuit. Even if the memory is operated at a low voltage, it can have a good pump charging efficiency. In order to achieve the above object, the present invention provides a semiconductor memory with a charging pump circuit, which includes: an array of 100 million cells, a row decoder and a column decoder. There is also a first charging pump circuit. The first charging pump circuit includes a plurality of pump units connected between a first voltage source and a first output terminal, and the first output terminal is connected to the row decoder. The pump unit includes a transistor, which is disposed on a floating substrate, and the substrate has a plurality of active regions. And a number of discharge transistors, which are set on a substrate, this base 6 III — I. Reservation.-(Please read the precautions on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 Specifications (210X297 mm) 2832pif.doc / 002 A7 B7 V. Description of the invention (f). The bottom is connected to a second voltage source, corresponding to a control signal. Furthermore, there is a second charging pump circuit. The second charging pump circuit includes a plurality of pump units connected between a third voltage source and a second output terminal, and the second output terminal is connected to Line decoder. The pump unit includes a transistor, which is disposed on a floating substrate, and the substrate has a plurality of active regions. And a plurality of discharge transistors. The discharge transistors are arranged on a substrate, and the substrate is connected to a fourth voltage source corresponding to a control signal. In addition, the first charging pump circuit further includes a transistor, which is connected to the first output terminal to a fifth voltage source and corresponds to the first advance charging control signal. And the second charging pump circuit further includes a transistor, which is connected to the second output terminal to a sixth voltage source and corresponds to a second advance charging control signal. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 , Which shows a schematic diagram of a charging pump circuit in a conventional nonvolatile memory; FIG. 2 shows a timing diagram of FIG. 1; FIG. 3 shows Shown is a schematic diagram of a change in the conventional starting voltage affected by the overall effect; FIG. 4 is a block diagram showing a non-volatile memory structure according to the present invention; FIG. 5 , Which shows the first preferred embodiment of the present invention, 7 Binding Dream (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ) 2832pif.doc / 002 406270 A7 B7 V. Description of the invention (Γ) A schematic circuit diagram of a charging pump used in Figure 4; Figure 6 'cannot be drawn according to Figure 5, the part of the charging pump Schematic diagram; Figure 7 'its drawing FIG. 5 is a timing diagram of the charging pump operation according to FIG. 5; FIG. 8 ′ is a schematic diagram of a charging pump circuit according to the second preferred embodiment of the present invention for FIG. 4; And FIG. 9 is a schematic structural diagram of a charging pump according to FIG. 8. Embodiment Please refer to FIG. 4, which is a block diagram showing a NOR flash EEPROM structure with a charging pump circuit according to the present invention. The column and row partial circuits 120 and 160 each select one of the word lines WL1 to WLn and one of the bit lines bli to BLn. These word lines and bit lines are distributed in a matrix manner in the memory cell array 100. The memory cells are, for example, flash EEPROM cells. The row portion circuit 160 connects the selected bit line to a corresponding sense amplifier (not shown). The column part circuit 120 drives all the word lines having a negative high voltage Vpp. This negative voltage Vpp · is provided by the negative charging pump circuit 150 during the erasing operation. Therefore, the billion-units formed on the substrate will be erased. Along with the negative charging pump circuit 150, the voltage VPP for erasing and repairing is erased. The positive charging pump circuit 140 provides a positive high voltage Vpp + to the column circuit 120 for programming and confirming the programming action. . The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) by listing part of the paper. ----------- (Please read the 1 ^^^^^^ item on this page before filling in this page} * 1T 2832pif.doc / 002 406270 A7 B7 V. Description of the invention (6) Select operation of the circuit 120, this positive voltage Vpp + is provided to the selected word line. At the output terminal of the positive voltage Vpp +, and the voltage node V〇D (This voltage is about the source voltage Vcc), the gate of the PMOS transistor 142 will be coupled to the signal ΦΕΝΟϋΒ. Between the output of the positive voltage Vpp · and the base voltage Vss (or ground), the NMOS voltage The gate of the crystal 152 is coupled to the signal (DENODB. The substrates of the PMOS transistor 142 and the NMOS transistor 152 are connected to the voltage node VOD and the substrate voltage Vss, respectively. Before or after the pump charging, the transistor 142 changes the voltage Vpp + The magnitude of the voltage pulled down from the output to VOD corresponds to the activation of the signal ΦΕΝΟϋΒ. Before or after the pump is charged, the transistor 152 pulls the output of Vpp- to the voltage of Vss, corresponding to the activation of the signal ΦΕΝΟϋΒ. FIG. 5 is a drawing showing The first preferred embodiment is a schematic diagram of a positive charging pump circuit M0 for generating Vpp + corresponding to FIG. 4. Among them, a plurality of pump units UP1 to UPn are connected in series between the power supply voltage Vcc and the output terminal of Vpp +. Each pump unit is composed of a coupling capacitor, a PMOS switching transistor and two parasitic diodes. The pump units UP1 to Upn have the same structure , And both are connected to the discharge voltage VBDp (discharge voltage) 'This VBDp voltage is in the NMOS transistors BDT1 to BDTn, and each of them is coupled to the discharge signal ΦΕΝΒϋ. For example, in the first pump unit UP1 One electrode of the capacitor C1 is connected to the pump timer ΦP1, and the other electrode is connected to the gate of the PMOS selection transistor MP1, and this gate is further connected to the drain node (or 9 paper sizes are applicable to China) Standard (CNS) Α4 specification (2 丨 0 X 297 mm) (Please read the precautions on the back before filling in this page) Binding · Order 2832pif.doc / 002

40627Q ί \ 7 Β7 V. Description of the invention (q) First pump node) N1. The transistor MP1 is connected to the power supply voltage Vcc, its source is connected to the base node B1 through the parasitic diode Dls, and its drain is connected to the base node B1 through the parasitic diode Did. In addition, the base of the electric crystal MP1 is also connected to the base node B1. Parasitic diodes Dls and Did are formed on the interface between the source region and the drain region and the base region, respectively, as shown in FIG. 6. Discharge node B1 is connected to VBDp through transistor BDT1. With the pump unit UP2 as the next pushing unit of UP1, the capacitor C2 will correspond to the pump timer ΦP2, and it has a phase complementary to the pump timer ΦP1. The other electrode of the capacitor C2 is connected to the gate of the PMOS selection transistor MP2, and this gate is further connected to the drain node (or the second pump node) N2. The drain node N2 is connected to the base node B2 through a parasitic diode D2d. The source of the transistor MP2 is connected to the base node B2 through the parasitic diode D2s. As in the transistor MP1, the substrate of the transistor MP2 is connected to the substrate node B2, and the parasitic diodes D2d and D2s are formed on the source region and the drain region, respectively, on the interface with the substrate region. Base node B2 is connected to VBDp through transistor BDT2. Pump units of similar structure are repeatedly arranged on the line to form a series of pump unit chains. Pump timers ΦP1 and ΦP2 are alternately applied to capacitors Cl-Cn, timer ΦP1 is applied to even-numbered capacitors C1, C3 ..., and timer ΦP2 is applied to odd-numbered capacitors C2, C4 ... As shown in Fig. 4, the leading charge transistor 142 of the PMOS FET is connected to the output terminal of Vpp +. Please refer to Figure 6, which shows a schematic diagram of the structure of the charging pump according to Figure 5. The formation of parasitic diodes can be understood from this Figure 6. The transistors MP1-MP2 are selected, and they are formed in their own paper. The paper standards are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). ^ -----. # '.-(Please read the notes on the back before filling this page) 2832pif.doc / 002 406270 A7 B7 V. Description of the invention (y) N · (micro-doped N · type ion ) In well 2, this N · well 2 is used as the base of the transistor. The N · well 2 is formed in a ρ · (micro-hybrid ρ · type ion) semiconductor substrate 1 ', and the semiconductor substrate 1 is connected to Vss (for example, 0V) through a P + region (concentively doped ρ + type ion). In N · well 2, the P + active region is formed to be used as a source and the drain, and the N + active region 9 is formed to receive a well bias when necessary. The N + active regions 7 and 8 are formed in the semiconductor substrate 1 for the drain and source of a discharge transistor, such as BDT1. The N + active regions 8 of this discharge transistor are all connected to the discharge voltage VBDp in common. The N + active region 7 of a discharge transistor, such as BDT1, is directly connected to the N + region in N · well 2 (or the base of the transistor selected in the pump unit) through node B1, and the N-well is not coupled with any bias voltage. It is floating. Because no bias voltage is applied to the N · well base of the transistor selected in the pump unit, the following two are connected horizontally, for example, between P + region 4 and N + region 9 and between P + region 4 and Between the N + regions 9, it is highly likely that a structure of parasitic diodes Dls and Did is generated, in which the anode is connected to VBDp through the channels of nodes B1 and BDT1. It is well known that the diode will maintain the predetermined voltage of the starting voltage and the current passing from the source and drain regions to B1, so that the potential difference between the cathode and the anode of the diode can be maintained. Please refer to FIG. 7, which shows a timing diagram of charging pump operation according to FIG. 5 (or FIG. 6). PGMB is a signal that initiates the programming action. PGMvfB allows a program verifying mode. First, when the pre-charging signal φΕΝΟϋ is low, the output of Vpp + and the positive charging pump circuit 140 will be based on the pre-charging transistor I42. The paper size applies to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm). 〉 (Please read the notes on the back before filling this page)

'IT 4 Qi Nianya-each bears one's share 1. Xiao Shehe: i.fft. ^ 06270 2832pif.doc / 〇〇2 A7 B7___ 5. The description of the invention (^) is opened, and the pre-charging voltage set to VOD Size (the voltage of Vcc). Then, if PGMB is low at time t1, the circuit starts to push VPP + to a voltage of about 10V for programming voltage, corresponding to the pump timers ΦP1 and ΦP2, which oscillate alternately and continuously with each other. At the same time, the voltage at the base node B1 of transistor MP1 becomes Vcc-Vtd (Vtd is the starting voltage of Dls), and node N1 is charged to Vcc-Vtpl (Vtpl is the starting voltage of MP1). Because Vtpl is generally higher than Vtd, Did cannot be turned on, and the voltage at node N1 remains at the current voltage, so that ΦP2 is high and ΦP1 is low, so that MP1 will be turned off. At time t2, ΦP1 is high and ΦP2 is low, MP1 and MP2 will be turned off and on respectively. The conditions can produce the following equations:

Vnl = (Vcc-Vtpl) X α X Vcc [1] Here, a = Cl / (Cl + Cl ′), and Cl ’is the capacitance of the node N1. The relationship between the voltage at node N2 and Vn2 is as follows:

Vn2 = (Vcc-Vtpl) X a X Vcc-Vtp2 [2] Here, Vtp2 is the starting voltage of MP2. When the time is from t2 to t3, the turn-off of transistor MP1 can protect the current from flowing from node N1 to Vcc. The base node B2 is charged to the voltage Vnl-Vtd, and VB2 is the voltage reduced from Vnl: VB2 = (Vcc-Vtpl) X aX Vcc-Vtd [3] As shown in equations [2] and [3] 'At the time of pumping operation, the voltage VSB between well 2 (the base of MP1) and P + region 4 (the source of MP1) is maintained at the start of the parasitic diode Dis (i means 1 to n arbitrary 値). Starting voltage Vtd. Therefore, the positive high voltage Vpp + is obtained according to the following formula: (Please read the precautions on the back before filling this page)%

* 1T This paper size applies to Chinese national standard (CNS > A4 specification (210 × 297 mm) 2832pif.doc / 002 406270 A7 B7 V. Description of invention (丨 i?)

Vpp + = Vcc + nX (aXVcc- | vtp |) [4] (Please read the note on the back before filling this page) During programming, the discharge signal ΦΕΝΒϋ and the pre-charge signal 0 > ENODB are kept at the predetermined high voltage respectively Vpp and low voltage. If the programming operation uses a positive high voltage Vpp + of about 10V when the time t4 is exceeded, the pre-charging signal ΦΕΝΟ 则 Β is low, which is used to pull down the voltage Vpp + to the voltage VOD, and Vcc is used as the charging voltage Vpp +, in order to prepare for subsequent programming confirmation operating. However, ΦP1 and ΦP2 have no effect until the programming confirmation starts. Even during the push operation, the voltage VSB is set to the voltage Vtd, and the inevitable substrate voltage will still increase, because the voltage of the 1ST well substrate will increase with the selection of the source voltage of the transistor, and the voltage difference is about Vtd. Such a high substrate voltage will exceed the source voltage of the selected transistor and reduce the boosting efficiency of the circuit. Therefore, when the time is from t4 to t5, the discharge signal ΦΕΝΒϋ will become high voltage Vpp to turn on the transistors BDTl-BDTn, and the driving voltage of the transistor substrate will be reduced to VBDp. For example, the substrate voltage will be discharged to make VBDp 0V . it · If PGMvfB goes low at time t6, the program confirm operation is started. From the positive charge pump circuit 140, ΦP1 and ΦP2 are started again, and Vpp + is generated to about 6V. We know that the size of Vpp + can be adjusted by controlling the number of times the pump timers ΦP1 and ΦP2 are operated. After finishing the programming confirmation operation, in order to charge the output of Vpp + in advance, ΦΕΝΟΒϋ will go low during the programming process. If necessary, < DENBD will be started in the same way during the programming operation. On the other hand, Figures 8 and 9 show a negative charging pump circuit for Figure 4 according to the second preferred embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS). Α4 specification (210X297 mm) 2832pif.doc / 002 406270 at B7 I-_______ ____ ______ _ 5. Schematic diagram of the description of the invention (丨 I). It can generate negative high voltage Vpp · for erasing and erasing confirmation. Each of the pump units UN1 to UNn is connected in series between the output terminals of the base voltage Vss and Vpp ·, and each pump unit is composed of a coupling capacitor, an NMOS selection transistor, and two parasitic diodes. The pump units UN1-UNn have the same structure and are connected to the discharge voltage VBDn. This VBDn is coupled to the discharge signal OENBD through the gate of the NMOS selection transistor BDT1-BDTn. For example, in the first pump unit UN1, one electrode of the capacitor C1 is coupled to the pump timer ΦP1, and the other electrode is connected to the gate of the NMOS selection transistor MN1, and this MN1 is further connected to the drain node N1. (Or the first pump node). The source of the selection transistor MN1 is connected to Vss, which is also connected to the base node B1 through the parasitic diode Dls, and the drain of the selection transistor MN1 is connected to the base node B1 through the parasitic diode Did. In addition, the base of the selection transistor MN1 is also connected to the base node B1. Parasitic diodes Dls and Did are formed on the interface between the source and drain regions and the base region, respectively, as shown in Figure 9. The discharge node B1 is connected to VBDn through a selection transistor BDT1. With the pump unit UP2 as the next driving unit of UP1, the capacitor C2 will correspond to the pump timer ΦP2, and it has a phase that complements the pump timer ΦP1. The other electrode of the capacitor C2 is connected to the gate of the NMOS selection transistor MN2, and this gate is further connected to the drain node (or the second pump node) N2. The drain node N2 is connected to the base node B2 through a parasitic diode D2d. The source of the transistor MN2 is connected to the base node B2 through the parasitic diode D2s. Just as in transistor MN1, the base of transistor MN2 is connected to the base node B2, and the parasitic diodes D2s and D2d respectively apply the Chinese National Standard (CNS) A4 specification (210X297 mm) for this paper. (Read the notes on the back and fill out this page)

1T 1 «TUT UK c f .1 ρΐ * 2832pif.doc / 002 4〇627〇 A7 _____B7_ 5. Description of the invention (11) It is formed on the interface between the source region and the drain region and the base region. Base node B2 is connected to VBDn via transistor BDT2. Pump units of similar structure are repeatedly arranged on the line to form a series of pump unit chains. The helper timers ΦP1 and ΦP2 are alternately applied to the capacitors C1_Cn, the timer ΦP1 is applied to the even-numbered capacitors C1, C3 ..., and the timer ΦP2 is applied to the odd-numbered capacitors C2, C4. As shown in Figure 4, the NMOS FET's leading charge transistor I52 is connected between the output of Vpp · and Vss. Please refer to FIG. 9, which shows a schematic diagram of a part of the charging pump according to FIG. 8. The formation of parasitic diodes can be understood from this Figure 9. The transistors MN1-MN2 are selected and formed in the P · (micro-doped P_-type ion) wells 12 which belong to them, and this P · well 12 is used as the substrate of the transistor. The P · well 12 is formed in the N · well 11, and the N · well 11 is in the F semiconductor substrate 10, and the N_well 11 is connected to Vcc through the N + region. in? _ Well 12 'N + active regions 14 and 15 are formed for source and sink, while P + active region 19 is formed for receiving well bias. The P + active regions 17 and 18 are formed in the N · well 11 for the drain and source of a discharge transistor, such as BDT1. The P + active regions 18 of this discharge transistor are all connected in common to the discharge voltage VBDn. The P + active region 17 of a discharge transistor, such as BDT1, is directly connected to the P + region in the 卩 _well 12 (or the base of the transistor selected in the pump unit) through the node B1. The P_ well is not coupled to any bias voltage. In a floating state. Because no bias voltage is applied to the P · well base of the transistor selected in the pump unit, the following two are horizontally connected, for example, between P + region 19 and N + region 14 and between P + region 19 and N + region 15 There is a high probability that parasitic diodes Dls will be produced. This paper size is applicable to China National Standard (CNS) A4 (2 丨 〇 X 297 mm) --------- i ----- -IT ------. #--(Please read the note on the back before filling in this page) 406S70 2832pif.doc / 002 A7 B7 V. Description of the invention (丨) Connect to VBDn through the channels of node B1 and BDT1. The well-known 'diode will be maintained at a predetermined threshold of the starting voltage between p-region 2 and N + active regions 14 and 15, so that the diode's own cathode (base) and anode (source and drain) can be maintained. The potential difference. When the negative charging pump circuit 150 performs a pumping operation, it is similar to the positive charging pump circuit 140, but the voltage is slightly different. For example, the voltage Vpp_ for erasing is about -12V 'and the voltage Vpp + is about 10V. . As shown in Figure 7, when the erase operation is performed, the programming signal PGMB and the program confirmation signal PGMvfB will correspond to the erase signal (such as ERSB) and the erase confirmation signal (such as ERSvfB). The gate of the advance charging signal OEOND provided to the transistor 152 will be set to high before or after the erase operation. The erase confirmation operation is the same as the programmed confirmation operation. This ΦΕΝΟϋ and the discharge transistor BDTl-BDTn still play a useful role, which can enhance the driving efficiency. As mentioned earlier, VBDn can be used to discharge to reduce the increased voltage on the transistor substrate. For example, 'VBDn is preferably Vcc. In summary, the present invention has the advantage of reducing some disadvantages or overall effects caused by an increase in substrate-to-source voltage. And strengthen the promotion efficiency of the subsequent pump unit chain in the pump unit. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. 'Any person skilled in the art' can make various changes and modifications without departing from the spirit and scope of the present invention. "Retouching" Therefore, the scope of protection of the present invention should be defined as the scope of the patent application attached to this paper. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297). I— ^ H Order I key 1-. (锖 先(Read the notes on the back and fill out this page)

Claims (1)

2832pif.doc / 002 ^ | Qg27〇g8g D8 6. Scope of patent application 1. A charging pump circuit including: a first conductive substrate; (please read the precautions on the back before filling this page) Wells provided in the first conductivity type substrate, the well systems being the second conductivity type and floating conditions; and a plurality of first conductivity type transistors, each of the first conductivity type transistors having a plurality in the well Each active region and each of the first conductive transistors have a gate; the gate corresponds to a capacitive coupling. The memory according to item 1 of the scope of the patent application, wherein 2. a kind of charging pump circuit, the circuit includes: a plurality of pump units connected between a first voltage source and an output terminal, the battery The pump unit includes a transistor provided on a floating substrate having a plurality of active regions; and a plurality of discharge transistors provided on a substrate and connecting the substrate to A second voltage source corresponds to a first control signal. 3. The circuit according to item 2 of the scope of patent application, further comprising a transistor connected between the output terminal and a second voltage source, corresponding to a second control signal. 4. A non-volatile memory having a memory cell array, a row of decoders and a column of decoders, comprising: a first charging pump circuit, the first charging pump circuit including a plurality of pumps A unit connected between a first voltage source and a first output terminal, the first output terminal being connected to the row decoder, the pump unit including a transistor, the transistor being disposed on a floating substrate And the substrate has a plurality of active regions and a plurality of discharge transistors. The discharge transistors are set on a paper ruler. The standard is Chinese Standard (CNS) A4 (210X297). A8 2832pif.doc / 002 406270 B8 D8 6. Apply for a patent on a substrate, connect the substrate to a second voltage source, corresponding to a control signal; and (Please read the precautions on the back before filling this page) A second charging help Pump circuit, the second charging pump circuit includes a plurality of pump units connected between a third voltage source and a second output terminal, the second output terminal is connected to the row decoder, the pump single The transistor comprises a transistor, which is arranged on a floating substrate, and the substrate has a plurality of active regions, and a plurality of discharge transistors. The discharge transistors are arranged on a substrate, and the substrate is connected to A fourth voltage source corresponds to a control signal. 5. The memory according to item 4 of the scope of patent application, wherein the first charging pump circuit further includes a transistor, the transistor is connected to the first output terminal to a fifth voltage source, corresponding to a first The advance charge control signal, and the second charge pump circuit further includes a transistor connected to the second output terminal to a sixth voltage source, corresponding to a second advance charge control signal. 18 Taipan Hui ruler uses China National Standard (CNS) A4 specification (210X297 mm)