TW403980B - Wafer level chip scale package structure and the manufacturing method of the same - Google Patents

Abstract

A wafer level chip scale package structure is provided, which comprises a die on its surface with a plural of die pads; a first dielectric layer located on surface; a preset damascene pattern is formed in first dielectric layer; a first layer of the metal wiring is positioned in the damascene pattern of the first dielectric layer to connect the first pad; a second dielectric layer is positioned on first dielectric layer and on the surface of the first layer of metal wiring ; and a plural of via plugs are positioned in the second dielectric layer to connect the first layer of metal wiring. And form a redistribution pad on the exposed surface of via plugs on the second dielectric. This invention also provides a method for manufacturing wafer level chip scale package structure.

Description

V. Description of the Invention (1) [Field of the Invention] The present invention relates to a wafer level wafer scale package structure (CSP) and a method thereof, and more particularly to a wafer level wafer scale package structure. And its method, a structure and a method for rewiring a wafer recording pad by a chemical mechanical polishing (CMP) method. [Background of the Invention] With the increasing demand for lighter and more complex electronic devices, the speed and complexity of the chip are relatively higher and higher, so higher packaging efficiency is needed. In the first-level packaging, flip chip (Flip chip) has a packaging efficiency of about 90% (calculated on a 10mm square chip), and wire bonding (Tape Automated Bonding, TAB) packaging efficiency (calculated on the same size chip) ) Are only about 75% and 50% respectively. The flip chip is a solder bump formed directly on the die pad on the surface of the wafer to directly fix and electrically connect it to a substrate or A printed circuit board. However, the size and spacing of solder pads on wafers are generally too small to form solder ball bumps directly on wafer pads using existing technology and equipment. Because the smaller the size and spacing of the solder pads on the wafer, the more accurate the volume of the solder ball protrusions needs to be controlled, because if the amount is not enough, it will easily cause inadequate adhesion, and if the amount is too large, it will increase the solder ball protrusions. The probability of a short circuit. a In addition, because the flip chip is directly fixed and electrically connected to a substrate or printed circuit board, the corresponding electrical contacts and

V. Description of the invention (2) The circuit must match the size and spacing of the pads on the wafer, so the density of the corresponding electrical contacts and circuits needs to be higher than that of ordinary users, thus increasing the manufacturing cost of the substrate or printed circuit board . Therefore, if the size and arrangement of the pads on the chip can be redistributed during chip packaging to match the corresponding electrical contacts and circuits on the substrate or printed circuit board, it will become the future trend of the semiconductor industry. … [Summary of the Invention] The main object of the present invention is to provide a wafer-level wafer size sealing structure and method thereof, which mainly utilizes photolithography, etching, and chemical-mechanical polishing (CMP) technology When the chip is packaged, the original solder pads on the chip are re-routed to match the corresponding electrical contacts and lines on the substrate or printed circuit board. Another object of the present invention is to provide a wafer-level wafer size package and a method of 'when the wafer is packaged', re-arrange the original recording on the wafer so that it can directly use the existing technology and equipment on the wafer pad Forming Ball Bumps® To achieve the above purpose, the present invention provides a wafer-level wafer-size package structure including a wafer having a plurality of first wafer pads on the wafer surface; a first dielectric layer on the wafer On the surface, a predetermined pattern is formed in the first dielectric layer; a first layer of metal wiring is located in the pattern of the first dielectric layer to connect the first wafer pad; a second dielectric layer is positioned on the first A dielectric layer and a first layer of metal wiring surface; and a plurality of vias of the vias in the second dielectric layer to connect the first layer of metal wiring, each

V. Description of the invention (3) ::: Hole: plugging a rewiring pad on the exposed surface of the second dielectric layer to re-evaluate the use of this rewiring circuit can increase the original solder size and spacing on the wafer to Utilizing the existing technology and equipment, solder ball bumps are formed directly on the wafer pads. By providing another wafer-level wafer-size packaging method, wiring on the wafer 'which includes α) coating a first dielectric layer on the surface having aa, (β) lithography and etching on the first A dielectric layer is formed with a damascene pattern; (C) coating a first metal layer on the surface of the first dielectric layer, and filling the lines thereon; (D) grinding the first A metal layer until the first dielectric layer is exposed to form a first metal wiring; (E) coating a second dielectric layer on the surface of the first dielectric layer and the first metal wiring; (F) using micro Forming a via hole in the second dielectric layer by means of shadowing and etching; (G) coating a second metal layer on the surface of the second dielectric layer and filling the via hole thereon; Second grinding the second metal layer until the second dielectric layer is exposed to form a new solder pad. [Illustration of the Drawings] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention in detail with the accompanying drawings. The first to ninth diagrams are used to explain the steps of the wafer-level wafer-size packaging method of the present invention 'rewiring the pads on the wafer; and the tenth diagram' is a preferred embodiment of the wafer-level wafer-size packaging structure of the present invention. After reassignment, solder bump is added

C: \ Program Fiies \ patent \ PK6685.ptd page 6 403980

Sectional view. [Illustration of drawing number 10 wafer 12 wafer fresh 20 first dielectric layer 22 trench 30 first-layer metal 40 second dielectric layer 42 interlayer hole 50 second layer metal 52 rewiring pad [Explanation of the Invention] Figures 9 through 9 are used to explain the steps of rewiring the pads on the wafer according to the present invention. Please refer to Figure »Figure-A wafer 1 0 1 * Γ has a plurality of wafer pads 1 2 (For: you will explain that only one solder pad is shown in the figure) 〇 It can be understood that the wafer 10 can be a part of a wafer (not shown) 5 means that The processing steps for rewiring the pads on the wafer according to the present invention can be directly implemented on an uncut wafer on the wafer to manufacture a wafer scale package (CSP). Please refer to the second figure. The first step of the present invention is to apply a first dielectric layer 20 on the surface of the wafer 10 with the solder pads ^ The first dielectric layer 20 preferably uses an inorganic dielectric. The material, such as silicon dioxide (SiO 2), can be applied to the surface of the wafer 10 and covered with the solder pad 12 by conventional techniques such as screen printing and roller coating. The first dielectric layer 20 is more preferably a spin-on glass (8 male 111-〇11-61 & 53,506) coated by a conventional spin coating method or a conventional electrode 2. Plasma Enhanced Chemical Vapor

C: \ Program Files \ patent \ PK6685. Ptd page 7 403980 V. Description of the invention (5)

Deposition (PECVD) -coated TEOSCtetraethoxysi lane) -Si02 (which refers to the silica dioxide deposited with TEOS as a precursor), phosphosilicate glass (PSG) (which is a kind of phosphorus-containing two Oxidized stone) or borophosphosilicate glass (BPSG) (which is a type of oxidized stone containing both boron and scale). If necessary, chemical-mechanical polishing (CMP) can be used to talk about planarizing the first dielectric layer 20 to facilitate the next step. Please refer to the third figure. The second step of the present invention is to form a required damascene pattern such as a horizontal trench 22 in the first dielectric layer 20 by photolithography and etching. And vertical holes (not shown). It is a layer of photoresist on the surface of the first dielectric layer 20, and then the pattern transfer of the first layer layout is performed by lithography, and the portion protected by the photoresist on the first dielectric layer 20 is etched. Remove it to form a corresponding pattern, and finally remove the photoresist — remove it. The etch step is preferably performed by a reactive ion etching (Reactive Ion Etch, RIE) method using a gas plasma containing CHF3, CF4, and Ar in a high density plasma (HDp) etcher. Please refer to the fourth figure. The third step of the present invention is to coat a first metal layer 30 on the first dielectric layer 20 and fill the lines formed thereon (as shown in FIG. 4). The trench 22 has been filled). The first metal layer 30 is preferably a Si-Cu Alloy, copper, gold, silver, or ore. If an aluminum-silicon-copper alloy, copper, gold, or silver is used, it is preferably SputterUg

403980 V. Description of the invention (6) 1 Coating; if tungsten is used, it is preferably coated by the conventional Plasma Enhanced Chemical Vapor Deposition (PECVD). Referring to the fifth figure, the fourth step of the present invention is to grind the first metal layer 30 by a conventional chemical mechanical polishing method until the first dielectric layer 20 is exposed to form a first layer structure. At this time, the metal filling the lines on the first dielectric layer 20 forms a first-layer metal wiring. Referring to the sixth figure, the fifth step of the present invention is to apply another second dielectric layer 40 on the surface of the first layer structure. The second dielectric layer 40 is preferably made of an inorganic dielectric material such as silicon dioxide (3 ^ 02). The second dielectric layer 40 can be applied to the surface of the first layer structure by a conventional technique such as screen printing or roll coating. The second dielectric layer 4 is more preferably a spin-on glass coated by a conventional spin-coating method or TEOS-Si02, a phosphosilicate glass, or a conventional plasma chemical vapor deposition coating. It is borophosphosilicate glass. If necessary, the second dielectric layer 40 can be chemically and mechanically ground to planarize it to facilitate the next step.凊 Referring to the seventh figure, the sixth step of the present invention is to form a reticle via hole (vU hole) such as hole 42 in the second dielectric layer 40 by lithography and etching. A photoresist is formed on the surface of the second dielectric layer 40, and then the second layer of the circuit layout is transferred by lithography, and the portion of the first dielectric layer 40 that is not protected by the photoresist is removed by etching: Corresponding interlayers and holes' are then used to remove the photoresist. This etching step is performed in a high-density plasma etcher using reactive ion ㈣ & with a gas plasma containing CHF3, Hf, and Ar.

In March, reference is made to the tenth figure ', which illustrates a solder bump with a solder bump after the redistribution structure of the wafer of the present invention is redistributed. Because the size and spacing of the redistributed pads can be designed to be larger than the original wafer ’, it can use conventional techniques to add

C: \ Program Files \ patent \ PK6685. Ptd page 10 403980 V. Description of the invention (8) The solder ball is protruding, and the density of its corresponding electrical contacts and lines needs to be lower than that of ordinary users, so The manufacturing cost of the substrate or printed circuit board can also be relatively reduced. In addition, since the size and spacing of the re-assigned pad can be designed to match the corresponding electrical contacts and circuits on the substrate or printed circuit board, the manufacturing cost of the substrate or printed circuit board can be further reduced. Moreover, according to the structure of the present invention, the first dielectric layer 20 of the package structure, the first metal wiring, the second dielectric layer 40, the plurality of via plugs and the rewiring pads 52 may be used. Designed to be equivalent to the size of the chip 12, the package structure can form a chip size package structure (chi {) sCaie package (CSP) 'to achieve higher packaging efficiency. Although the present invention has been determined by the foregoing preferred implementation, anyone skilled in the art can, within the scope, make various changes and repair new wiring as the preferred embodiment, and rewiring to meet actual needs The examples defined in the appended patent application scope are disclosed, but they are not intended to be limited to the spirit and modification of the present invention. As in the present invention, although there are two layers. However, the present invention can also be two layers C. Therefore, the scope of protection of the present invention shall prevail.

Claims (1)

-403L 6. Application patent scope 1: A wafer-level wafer size packaging method, which includes the following steps: providing a wafer with a plurality of wafer pads on the wafer surface; coating a first dielectric layer on the wafer The wafer of the first bonding pad covers the wafer front; a predetermined pattern is formed on the first dielectric layer by lithography and etching; a first metal layer is coated to cover the first dielectric The surface of the layer and fills the pattern on it; the first metal layer is chemically and mechanically polished until the first dielectric layer is exposed to form a first layer of metal wiring and coated in the pattern of the first dielectric layer A second dielectric layer is coated on the surface of the first dielectric layer and the first line with a lithography at 9 to form a second layer. The second layer is chemically mechanically formed with a dielectric layer and a via hole. New wiring is available upon request. The method comprises: forming a metal layer hole in the first dielectric layer and covering the surface of the second dielectric layer with a layer of 0 metal cloth and a engraving method; and interposing the hole of the second dielectric layer; and grinding the second dielectric layer; Metal layer until the second dielectric layer is exposed, Therefore, a plug is inserted into a dielectric hole of the second dielectric layer ', so that the plug forms a bonding pad on the exposed surface of the second dielectric layer. Take the wafer-level wafer size packaging method of item 1 in the 2nd range, and form a solder ball bump on the re-routed pads in one step. C: \ Program Files \ patent \ PK6685.ptd page 12 The wafer-level wafer size packaging method according to item 1 of the patent application scope, wherein the first layer and the second dielectric layer are made of spin-on glass, TEOS-Si02, phosphosilicate glass, and borophosphosilicate glass "Choose from the group of members" "#, the wafer-level wafer size packaging method according to the first patent application scope, wherein the first layer and the second metal layer are composed of aluminum silicon copper alloy, feed gold and silver Selected from the ethnic group. The method of sealing the wafer-level wafer size according to item 4 of the patent application range, wherein the first layer and the second metal layer are coated by sputtering. 2. The wafer-level wafer size packaging method according to item 1 of the application, wherein the first layer and the second metal layer are tungsten. ′, The wafer-level wafer size package according to item 6 of the patent application scope, wherein the first layer and the second metal layer are coated by a plasma chemistry method. Only ten thousand faces;-in the dielectric layer A wafer-level wafer-size package structure for connecting crystalline layer metal wiring, which includes a wafer having a plurality of wafer pads located on the wafer, a first dielectric layer on the surface of the wafer, and the first formation of a predetermined A pattern; a first layer of metal wiring pads in the pattern of the first dielectric layer; a second dielectric layer on the first dielectric layer and the first surface; and a plurality of via holes in the via The second dielectric layer is interconnected with metal wiring. The plugs of each interlayer are exposed at the second dielectric & first percent increase. C: \ Program Fi 1 es \ patent \ PK6685. Ptd page —13 " — _4Π · υ »π 6. Application scope of patents-The surface of '* --- forms a rewiring pad. 9. The wafer-level wafer size package structure according to item 8 of the patent application scope, which further includes a solder ball protrusion formed on the rewiring pad. 10. The wafer-level wafer size package structure according to item 8 of the scope of the patent application, wherein the first layer and the second dielectric layer are made of spin-on glass, TEOS-Si 02, phosphosilicate glass, and borophosphorus. Selected from the group consisting of silica glass. 11. Wafer-level wafer size package structure according to item 8 of the scope of the patent application, wherein the first layer of metal wiring and via plugs are Mingshixi copper alloy. 0 2. According to item 8 of the scope of patent application The wafer-level chip-size package structure, wherein the first metal wiring and the via plug are selected from the group consisting of crane, Mingshixi copper alloy, copper, gold and silver. C: \ Program Files \ patent \ PK6685.ptd page 14