TW400584B - Method of forming the ultra-short channel and MOSFETs with raised S/D on the ultra-thin SOI substrate - Google Patents

Abstract

The method of the invention includes the step of: forming a buried-in oxide on the substrate; forming a pad oxide on the surface of the substrate; forming a pattern of silicon nitride on the surface of the pad oxide; forming a thick field oxide (FOX) on the pad oxide; forming the sidewall on the side of an opening and etching the FOX; proceeding an ion implantation procedure to adjust the threshold voltage and to implant the anti-punchthrough ions; depositing a nitride oxide on the surface of the silicon nitride, sidewall and opening in order to form a polysilicon gate in the opening; removing the silicon nitride oxide, silicon nitride and sidewall; subsequently, forming a source and a drain, removing the pad oxide and the FOX, and forming a lightly doped drain (LDD); finally, forming self-aligned salicide and polysilicon salicide on the substrate exposed by the gate and on the gate, respectively.

Description

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ---------- B7 _____ V. Description of the Invention () Field: The present invention relates to a semiconductor device, especially a device with an ultra-short channel and a difference , Λ, ^ ^ liter / primary electrode and deep electrode sub-micron metal oxide half-oxide on ultra-thin SOI substrate J: Manufacturing method of high efficiency transistor (MOSFET). Bi Li background: μ a Recently the semiconductor industry has developed very prosperously. In order to obtain high-performance integrated circuits and increase the density of the wafer, in the ultra-large integrated circuit (ULSI) technology, the size of semiconductor components is continuously reduced. Integrated circuits are formed in a specific area on the wafer. Millions = π pieces and electronic link structures that connect these components with νχ to enable specific functions required by the lamp. The metal oxide half field effect transistor (MOSFET) is typical = ① of the _ 'has been widely used in semiconductor technology. With the trend of integrated circuit progress, it is also 1 «when manufacturing m〇sFet Many problems, typical problems such as the hot carrier effect, have been overcome by the development of lightly doped drain (LDD) structures. The structure of Xicheng silicon film on the isolation layer (sj 丨 jc〇n 〇n Ms ... atorSQi) is greatly weighted because it has the function of reducing the short channel effect. In addition, the demand for components is directed toward high driving capacity. Development of 疋 x For the sub-micron MOS device, the smc (smconn insulator) is an ideal structure for manufacturing '3 devices. In the current development of semiconductor technology, the thin films on the structure can meet the low operation requirements.

This paper standard IT account 1¾¾. (CNS) A4 ^ T21〇X 297 / Jt ~ T (Please read the precautions on the back before filling this page) ___ ”-------------- --- G ----------- # ------- A7 B7 V. Description of the invention () Power and low power consumption requirements play a very important role. What's more, the Compared with silicon blocks or partially-depleted (PD) SOI MOS, fully-depleted (FD) SOI MOS can provide a higher driving capability, reduce parasitic capacitance, and reduce short-channel effects. Therefore, it is often recommended to use components with p DS Ο 丨 structure in ultra-low voltage operation. Literature on SOI such as "Thin Film Silicon on I n su I ator: A η E nab 1 ing Technology, Michael Alles. Et al_, S nternational, p_ 67,1 997. ". There are many ways to form the SOI structure. One of them is the so-called SI MOX (separation by implantation of oxygen). This method involves implanting oxygen ions into the substrate and then Tempering at high temperature to form the desired SiO structure. As another method for forming the S 01 structure at a lower cost is wafer bonding, First, an emulsion layer was formed on each of the two wafers ', and then a tempering process was performed at room temperature to strengthen the bonding between the two wafers, thereby bonding the two wafers together. However,' the thin FDS 0 I transistor has its source The high series resistance between the pole and the drain will reduce the performance of the device. A method is provided by su to reduce the series resistance. Please refer to '' 〇ptjmjzatj〇n of Series

Resistance in Sub-0.2 μηπ SOI M0SFET, S, LKSu et al., IEEE, Electron Device Lett., Vol. EDL-1 5, P. 1 45, 1 994 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling out this page) ''. One of the solutions is to reduce the resistance of the S / D chip by using silicide metal. Su recommends using titanium / cobalt silicide to overcome this problem. In addition, due to the limitation of the resolution of current lithography technology, it is difficult to define a gate pattern with a length of less than 0.1 μηπ in the manufacture of components. Please refer to "short- This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) V. Description of invention (A7 B7

Channel-Effect-Suppressed Sub-0_1pm Grooved-Gate MOSFET'S with W Gate, S. Kimura et al. JEEE Trans. Electron Device Lett., V〇I.ED-42, p.94,1 995. "In this document In the description, Kimuma discloses a trench gate sj m0S with a tungsten gate, which can be used to suppress the short channel effect. Purpose of the invention and sincerity: The purpose of the present invention is to provide an ultra short channel and a rising source and drain. Method for manufacturing deep sub-micron metal oxide half field-effect transistor (MOSFET) on ultra-thin SOI substrate. (Please read the notes on the back before filling out this page} Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs An oxide layer is formed on the surface of the substrate to form a buried oxide layer, so a stone layer is formed between the buried oxide layers. Then, a silicon nitride layer with an opening pattern is formed on the substrate to expose the oxide layer. Then, a thick field oxide region (F0X) is formed on the exposed layer by using a thermal oxidation method. Next, a sidewall of the sidewall is formed, and the sidewall is used as an exposed component. F 〇 X for I insect engraving. Then through the opening The sequence 'implants impurities into the substrate to adjust the starting voltage and sub-implants. Then a sequence is performed in the environment of 0 2 and N 2 0' to restore defects caused during etching, and at the same time, a nitrous oxide sludge is formed. Layer, a part of the opening of the re-oxidized oxide layer, and an ion as a high-temperature heat-resistant opening in the bottom layer and the surface of the surface and the surface of the cushion I cushion oxygen " fl side wall_ί Implanted Wei Penetration Tempering Tempering Base Paper This paper applies the Zhongguanjia Standard (CNS) A4 specification (210X297 mm A7 B7) Five invention instructions ('remove the oxide layer of the child' while using chemical gas An oxide layer is formed on the silicon nitride layer, the sidewall of the sidewall, and the surface of the opening. A polysilicon layer is formed on the thin CVD oxynitride layer and fills the opening. Then, the polycrystalline silicon layer is etched to form a gate. The CVD oxynitride layer, the nitride layer and the sidewall of the sidewall are removed using a touch-engraving process. Next, ion implantation is performed to form a source and a drain, and high temperature thermal tempering is performed. The impurity is activated by the procedure. Subsequently, the pad oxide layer and FOX are removed to expose The surface of the substrate was subjected to a low-energy and low-dose comprehensive ion implantation to form a lightly doped drain (DD). Next, a thick oxide layer was formed on the surface of the substrate by the CVD method. The oxide layer is etched to form a side wall sidewall on the side wall of the gate. Finally, a portion of the substrate exposed by the gate and a self-aligned silicide metal layer (sALICIDE) are formed on the gate, And polycrystalline silicon silicide layer. (Please read the precautions on the back before filling this page)

Printed by the Central Standards Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs, Type II, a simple description: With the following detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily understood, of which the first picture is a semiconductor chip A cross-sectional view showing a step of forming a buried oxide layer in a semiconductor substrate according to the present invention. The second figure is a cross-sectional view of a semiconductor wafer, showing a step of forming a silicon nitride layer pattern according to the present invention. The third figure is a cross-sectional view of a semiconductor wafer, showing a step of forming a thermal oxide layer on a substrate according to the present invention. Ming Mingming (7 Ί This paper size is in accordance with Chinese national standard (CNS> Α4 size (2ΐ〇χ297mm> Α7 Β7) Sectional view of the printed sheet printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, showing the steps of the wall. Sectional view of the sheet Shows the steps of the thermal emulsified layer. Cross-section view of the sheet, cross-section view of the sheet, cross-section view of the sheet, display step. Cross-section view of the sheet, cross-section view of the sheet, step of ion implantation. Cross-section view of the wafer The cross-sectional view of the wafer is shown, showing the step of the LDD structure, the cross-sectional view of the wafer, the cross-section view of the wafer, and the steps of the I process. According to the present invention according to the present invention according to the present invention According to the present invention, according to the present invention, according to the present invention, according to the present invention, according to the present invention, and according to the present invention (5) The fourth picture is a semiconductor crystal formed on the side wall of the silicon nitride layer. The fifth picture is a semiconductor crystal using the sidewall. As the mask etching, the sixth figure is a step of performing an ion implantation of a semiconductor crystal. The seventh figure is a step of performing a thermal oxidation of the semiconductor crystal. The eighth figure is The ninth picture of a semiconductor crystal forming a CVD oxynitride layer is the step of forming a silicon gate of a semiconductor crystal. The tenth picture is a semiconductor crystal performing the gate, and the source and the drain are eleventh. Impurity steps. Figure 11 shows the semiconductor oxide to remove the thermal oxide layer and form the 13th figure shows the steps of the semiconductor oxide to form the oxide sidewall. Figure 14 shows the semiconductor Ming to perform a self-aligned silicided metal. Elg |. This paper size is in accordance with Chinese National Standard (CNS) A4 (2ωχ297mm A7 B7) 5. Description of the invention () This invention provides a new method for manufacturing ultra-thin SOI (silicon on insulator) substrate The short-channel rising S / D MOSFET can be obtained by using the side wall as an etch mask. The rising metal silicide S / D contact is used to reduce the parasitic resistance to obtain a high-performance SOI device. In addition, the ultra-thin silicon layer of the high-performance SOI device can be obtained by the area thermal oxidation method. A related literature was proposed by Faynot. High Pergormance Ultrathin SOI M0SFET5S Obtained by Locali zed Oxidation, IEEE, Electron Device Lett., vol. EDL-15, P.175, 1994. "In the present invention, the" short channel effect "can be achieved by using a rising source-drain interface and an ultra-short channel. Suppressed, the embodiment of the present invention is described below. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) In a preferred embodiment, a < 1 〇 > A single crystal silicon substrate 2 in a crystal orientation, and an SOI structure 4 is formed in the substrate 2. As is well known in the art, there are many methods for forming the SOI structure 4 in the substrate 2. For example, 'separation by implatation of oxygen (SIMOX) can be used to fabricate a buried isolation layer under the SOI structure 4. First, an oxygen ion implantation procedure is performed, the oxygen ions are implanted into the substrate 2, and then a high temperature thermal tempering procedure is used to form an 801 structure 4 at a temperature of about 100 to 135 ° c. Next, a pad oxide layer 8 is formed on the surface of the substrate 2, so that a stone layer 6 is generated between the SOI structure 4 and the plastic oxide layer 8. Generally speaking, the pad oxide layer 8 is at a temperature of about 800 to 1100. 〇 and formed in an oxygen-filled environment, and in a specific embodiment, the thickness of the pad oxide layer 8 is about 15-250 angstroms. Similarly, the pad oxide layer 8 can also be formed by a suitable oxide and its chemical combination and procedure, such as chemical vapor deposition. This paper size applies to China National Standards (CNS) 8-4 specifications (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Please refer to the second picture on the surface of the oxide layer 8 of this pad A silicon nitride layer with an opening 12 pattern is formed thereon to expose a portion of the pad oxide layer 8 and define the active region. Then, a thick field oxide region (Fox) 14 is formed on the exposed part of the pad oxide layer 8 by using a thermal oxidation method. Generally speaking, by performing thermal oxidation in a vapor environment, a FOX region 14 'having a thickness of about 1,000 to 80,000 Angstroms can be formed. As shown in the third figure, a silicon layer 6 under the Fox region is formed. Its thickness will be reduced due to the oxidation of this area. Next, referring to the fourth figure, a side wall 16 is formed on the side wall of the opening 丨 2. In order to obtain the sidewall of the side wall, a thick dielectric layer is first formed along the surface of the silicon nitride layer j 0 and F0X14, and then an anisotropic etching is performed. The side wall 16 of the side wall will expose a part of ρ × 14, and the side wall 16 is preferably formed of nitrided stone. In this way, the nitrided dream layer 10 will be able to communicate with the side wall. The side walls 16 are removed together in the same subsequent step. Next, the side wall 16 is used as a mask to etch the exposed part F0X14, thereby exposing a part of the silicon layer 6 to form a deeper opening 18 in FOXI4. This result is depicted in section Five figures. Then "refer to the sixth figure" to perform an ion implantation procedure through the opening 8 "to implant the impurities into the substrate to adjust the starting voltage and implant as an anti-passage ion. For example, for an NMOS transistor, the impurity of the ion implantation is B or Eh ions, and the impurity of the anti-penetration ion implantation is As, P, or Sb ions. Furthermore, the dose and ion implantation energy in this step are 5E11 to 5E13 atoms / cm2, 0.1 to 50 KeV, respectively. Next, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)

Employees' Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China, A7 ", ^ ___ B7 V. Inventive Test () ~~~ As shown in the seventh figure, a high temperature thermal tempering process is performed in the environment of 0 2 and N 2 0 In order to restore the defects caused by the etching process, the temperature of this step is about 750 to 1100 t :. At the same time, a dielectric layer 20 (which may be an oxide layer or an oxynitride layer) will be formed at the bottom of the opening 18 due to the thallium effect in an oxidizing environment.

A portion of the polycrystalline silicon layer in the opening 18 is formed below, thereby forming the gate 24, and a portion of the silicon oxynitride layer 22 under the gate 24 is used as a gate dielectric layer. Then, referring to the tenth figure, an etching process is performed to remove the CVD silicon oxynitride layer 22, the silicon nitride layer 10, and the sidewall of the side wall 16. Thus, the hafnium oxide layer 8 and the FOX1 4 will be exposed. . Generally speaking, CF4 / H2, CHF3 or CH3CHF2 can be selected as the etching formula when performing the etching process. Then, by performing an ion implantation, a source electrode and a non-electrode electrode can be formed in the silicon layer 6, and the gate electrode 24 is doped with impurities in this step. The ion implantation agent is about 1E14 to 2E16 atoms / cm2, and the energy of this step is about 0.5 to 80 KeV. Subsequently, the impurities can be activated by performing a high-temperature thermal tempering procedure at 0 2 and n 2 0. As shown in the eleventh figure, the temperature of this step is about 750 to 1 100. 〇.

This paper is standard tHCNS) A4tm (21〇T29 ^ tT (Read the precautions on the back before filling in this page)

---- ----. IT ------ MA 7 ------ ---- B7 V. Description of the invention () ~~ '(谙 Please read the notes on the back before filling this page) Please refer to In the twelfth figure, the oxide layer 8 and f 0 X 1 4 are then removed to expose the surface of the substrate, and a low-energy 1 low-dose comprehensive ion implantation is performed, and impurities are implanted into the substrate so that A lightly doped drain (LDD) 28 is formed adjacent to the gate 24. The dose and ion implantation energy for this step are 1E12 to 1E14 atoms / cm2 and 0 to 5 KeV. After F0X14 is removed, a recessed portion 30 will be formed adjacent to the gate 24. Next, referring to the thirteenth figure, a thick oxide layer is formed on the surface of the substrate 2 by using the CVD method, and then by etching the oxide layer, edges are formed on the side wall of the gate 24 and the recessed portion 30. Wall side wall 32. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, as shown in Figure 14, self-aligned silicide metal layer (SALICIDE) 34, polycrystalline silicide metal layer 3 6 will be at the source and drain 26, and the gate 2 4 on top. Generally speaking, this result can be achieved by well-known procedures, for example, the substrate 2 and the gate electrode 24 are conditioned to form a solvent-resistant metal layer or a heavy metal layer. The metals used are Ti, Pt, Co, W, N ^. Then perform a rapid thermal tempering (RTA) in a full environment at about 350 to 700 ° C, so that the refractory metal reacts with the gate 24 and the silicon substrate 2 and forms on these parts. Silicides metal to reduce parasitic effects. Next, a removing step is used to remove the unreacted refractory metal on the side wall 32. Thus, the self-aligned silicided metal layer 34 and the polycrystalline siliconized metal layer 36 will be self-aligned on these regions. The temperature in this step is approximately 750-1050 ° C. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). 5. Description of the invention (A7 B7 is for use. Nefel is surrounded by examples. It is given to the Natural Real God Garden, a fine-home here. The benefits are as clear as in the Ming Dynasty. Please explain only this application example. The separated entity is better than the real one in the first round, including the encapsulation of the divine art. Refined limited masterpieces (please read the notes on the back before filling out this page) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

6. Scope of patent application i. A method for manufacturing a transistor on a semiconductor substrate, wherein the semiconductor substrate has a silicon layer on an isolation structure ', and the method includes at least the following steps: forming a buried oxide layer on the semiconductor substrate Forming a pad oxide layer on the semiconductor substrate, and thereby generating a silicon layer between the buried oxide layer and the pad oxide layer; forming a silicon nitride layer having a first opening pattern on the semiconductor substrate; A part of the pad oxide layer is exposed on the pad oxide layer; a thermal oxide layer is formed on the exposed pad oxide layer to reduce the stone layer. The thermal oxide layer is generated by thermal oxidation; The side wall of the first side wall is on the side wall of the first opening; the thermal oxidation layer is etched to expose the semiconductor substrate, the etching process uses the side wall of the first side wall as a mask, and thereby forms a second opening on the side wall of the first opening. In the thermal oxidation layer, the second opening is deeper than the first opening; a silicon oxynitride layer is formed on the surface of the silicon nitride layer and the second opening; a gate is formed in the second opening ; Remove this Silicon nitride layer, the side wall of the first side wall and part of the silicon oxynitride layer; printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) for the first ion implantation So as to form a source electrode and an electrode electrode adjacent to the gate electrode; remove the thermal oxide layer and the pad oxide layer; perform a second ion implantation to form an LDD structure adjacent to the drain electrode; Printed with Chinese National Standard (CNS) A4 (210 × 297 mm) 8 888 ABCD Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, applying for a patent to form the side wall of the second side wall on the side of the gate j 2. If applied The method of the first item of the patent park further includes a step of performing a third ion implantation after adjusting the thermal oxidation layer to adjust the initial voltage and as a step of anti-penetration. 3. The method according to item 2 of the patent application scope, further comprising performing a thermal tempering process to restore the etching defects after the third ion implantation. 4. For the method of applying for the first item of the patent fan park, further comprising forming a silicided metal layer on the source and the drain electrode after forming the sidewall of the second side wall, and forming a polycrystalline silicided metal layer on the alarm electrode. . 5. The method according to item 1 of the patent application park, further comprising the following steps of forming the gate: forming a polycrystalline silicon layer on the silicon oxynitride layer; and etching the polycrystalline silicon layer to form the gate. 6. The method according to item 1 of the patent application scope further includes the following steps of forming the buried oxide layer: implanting oxygen ions into the semiconductor substrate; and performing a thermal process to form the buried oxide layer. 7. The method according to item 1 of the patent application park, wherein the dose of the above-mentioned ion implantation is approximately 5E11. To 5E13 atoms / cm2. This paper size adopts Chinese National Standard (CNS) A4 specification (210X297 mm) -------------------: --- r Order ------- (Please read the precautions on the back before filling out this page) xny 6. Application for patent scope 8. For the method of applying for patent scope item 1, the energy of the above-mentioned first ion implantation is about 0.1 to 50Kev. 9. The method according to item 1 of the scope of patent application, wherein the dose of the above-mentioned second ion implantation is approximately 1E14 to 2E16 atoms / cm2. 10. The method according to item 1 of the patent application range, wherein the energy of the second ion implantation is about 0.5 to 80 Kev. 1 1. The method according to item 2 of the patent application range, wherein the dose of the third ion implantation described above is approximately 1E12 to 1E14 atoms / cm2. 1 2. The method according to item 2 of the patent application range, wherein the energy of the third ion implantation described above is approximately 0.5 to 60 Kev. 13. The method according to item 3 of the scope of patent application, wherein the thermal tempering procedure for recovering the etching defect is performed in an N20 environment. 1 4. The method according to item 3 of the scope of patent application, wherein the thermal tempering procedure used to restore the etching defects is performed in an environment of 02 ° Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the first Note: Please fill in this page again.) 15. The method according to item 1 of the patent application, wherein the impurity located in the source and the drain is activated in an N2 / 02 environment. 1 6. The method according to item 1 of the scope of patent application, in which the paper size at the source is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A8 B8 C8 _; _ D8_ '7T, the scope of patent application and the The impurity in the drain is activated in a 02 environment. 1 7. The method according to item 1 of the scope of patent application, wherein the side wall of the second side wall is formed of silicon oxide. 1 8. The method according to item 1 of the patent application park, wherein the activation temperature of the aforementioned impurities is about 750 to 110 ° C. 19. The method according to item 3 of the patent application park, wherein the temperature of the thermal tempering procedure used to restore the etching defect is about 750 to 110 ° C. (Please read the notes on the back before filling out this page). Order: Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 size (210X297 mm)