經濟部中央櫟準局員工消费合作杜印裂 A7 J B7 五、發明説明（） 本發明係有關於一種使用在電腦系統所外接之快取記 mm±- (Externa 1 Cache ,係指包裝於電腦CPU晶片内部以 外之擴充t夫取記憶,用Μ有效的管理該外接快取記憶 體的電源使用情形，提高其能源的使用效益。 快取記憶體（CACHE) 的運用，自從INTEL386 CPU的發 展使用Μ來，在中央處理單元的執行處理速度及功能大幅 提昇之後，為配合前述的發展，避免執行處理時間浪費在 較慢的一般記<噫體之資料存取週期上；因此，在中央處理 單元内有了内部快取記憶體的設計，存放著最近使用到的 - — --- -- 資泡加快了料的存取動作，並減少了匯流排傳 遞的擁擒。然，近期電腦糸統的進步，無論是硬體或軟體 上的發展，已使得其所提供的内部快取記憶體不敷使用， ，為有效的發揮中央處理單元的功能，因而應蕴了外接快 取記憶體的建立之設計，亦成為目前近代電腦系統所必需 之裝置。 至於，有關現今電腦系統之電源管理電路部份，一般 來說桌上型電腦的電源是直接連接於使用場所的電源插座 上，在使用上是不虜匮乏的，因此對於節省不必要耗電的 設計及設想是相當欠缺的，更何況是有關於存取率高、著 重速度快之外接快取記憶體部份的電源管理更是未有所聞 :,而，可攜式電腦係Μ電Ϋ也供電，苜重電池之供電使用時 間，因此對於節省電力耗費的電源管理尤為注重；一般而 言，在可機式電腦中，使用的電源管理主要的係針對m央 處理單元及其他如液晶顯示器、砍硬式磁碟饑..串並列輸 出V库等輔ϊ出入設備，在持鑛一段時間内未操作或使用到 時，g卩予以部份或全部的ί亭止工作、或只供應維持電力， 而節.省耗電，即所稱之PMU < Power Managemen t Un i t :電 源管理輩元）。對於外接快取記憶體的電源使用，因為外 接快取紀憧體存取率高，a要求速度快，所以溥統墨將外 接f夫取記4意體始终保持在即時工作狀9有.而-怔決對其當雁 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 83.3.10,000 (請先閲讀背面之注意Ϋ項再填寫本貰) 裝· 訂 線 A7 B7 經濟部中央標準局貝工消费合作社印簟 五、發明説明（） 供電時機作有效的規範，因此Μ往並未提供任何省電方案 或電路裝置，來達到節省其外接快取記憶體在未使用時的 不必要耗電，延長電池之可使闬時間，並且不影響到糸統 功能及執行速度之目的：， M——個編號IDT71420的32K*18之常用同步SRAM (Stat i Random Access Memory :靜態隨機存取§己憶體）作夕卜接f夬 取記憶體為例時，工作用電量約1.6W，未被選取的等待保 持用電童僅約為0.15W〜0.25W左右；當電腦糸統使用256K 或512K的外接快取記憶時，工作用電量約為6.4W或12.8W ，其耗電量佔糸統的1/4至1/3強；而在未被選取之等待狀 態僅0.8W〜1.6W，相差甚遠。且，在一般正常程式執行時 ,原主機之中央處理單元内部的快取記憶體即有約80%〜 85%的可提供命中率，因此這80¾〜85%的時間，加上所有 I/O週期，均可讓外接快取記憶體保持於省電狀態，以前 述之5121<：之夕卜接快取記憶體為例，可自原用電量12.8W降 至 3.28W 左右 Μ 下（12.8:::15% + 1.6々85% = 3*28W)。因此所達 到的節^效果是具相當大的效益；若中央處理單元處於 LT (停止）或進入睡眠狀態，則可節省的用電量更多，此對 於靠電池供電的可攜式電腦來說是絕對重要的；且為使桌 上型電腦符合省電環保（Green PC)的訴求，此項需求亦是 不可或缺的。 爰是，本發明之主要目的係提供一種有關於外接快取 記憶體的用電管理控制方法；尤其是，平常未使用到外接 快取記憶體時，只供給其少部份之維持電流，而在該外接 快取記憶體可能被存取時，才決定给予完全之電能，並旦 是在可能被讀寫之前，先使之進入工作狀態，而不會影響 到讓寫之時序週期，及系統處理功能。其中，最可行的控 制方式是藉由操作外接快取記憶體之晶片選擇線CS Ch [ P SeLect)輸入的” HIGH”、”L0W”訊號來使該外接快取紀憶 體處於非選取之保持電流的等待狀態（S band By丨或游_ ίί7 n· ^^^1 Hu nn ί ί 1 1^1 I (請先閲讀背面之注意事項再填寫本頁) 訂 i丨線- V HAH fn^ · 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公釐） 83. 3.10,000 B7 五、發明説明（） 之工作電流的工作狀態；至於何時須使外接快取記憶體處 於工作狀態，何時只需維持電能而已，是一相當重要的技 術。 為有效而適當的控制外接快取記憶體之工作狀態來達 到節省耗電量的目的，本發明主要特點係根據所接受之糸 統匯流排中的M/ IOtf線（記憶體或輸出入裝置週期控制線） 、HLD Α線（匯流排持有認可線）等訊號來判定得知糸統狀態 及匯流排使用情形，Μ作為CE#訊號的控制依據，決定電 能提供的時機。而可行的處理實施方法，是在糸統匯流排 中的M/IO#線處於” HIGH”的糸統記憶體週期，或當HLDA線 亦為” HIGH” 即 DMA(Direct Memory Access ·直接記憶體 存取）模式時，系統發生了匯流排持有要求訊號，才需使 外接快取記憶體進入工作狀態。其餘：在糸統非記憶體週 其月時（M/IOtf = ”LOW”），處方令 I/O週其月（M/Ι◦井=”LOW.，）、Consumption cooperation between employees of the Central Oakland Provincial Bureau of the Ministry of Economic Affairs Du Yincha A7 J B7 V. Description of the invention () The invention relates to a cache memory mm ±-(Externa 1 Cache, which refers to packaging in a computer) Expand the external memory of the CPU chip and use M to effectively manage the power usage of the external cache memory and improve its energy efficiency. The use of cache memory (CACHE) has been used since the development of the INTEL386 CPU. In the past, after the execution processing speed and functions of the central processing unit have been greatly improved, in order to cope with the aforementioned developments and avoid wasting execution processing time on the slower data access cycle of the general record < The unit has an internal cache memory design, which stores the recently used --- ----data bubbles to speed up the access operation of materials and reduce the capture of bus transfers. However, the recent computer 糸The advancement of the system, whether it is hardware or software development, has made the internal cache memory provided by it inadequate. In order to effectively play the function of the central processing unit, It should contain the design of the establishment of external cache memory, and it has become a necessary device for modern computer systems. As for the power management circuit part of modern computer systems, generally, the power of desktop computers is directly connected to The power outlets in the places of use are not scarce in use, so the design and assumptions to save unnecessary power consumption are quite lacking, not to mention the high access rate and fast speed of access to cache memory Part of the power management is unheard of: And, portable computers are also powered by the M battery, and the power supply time of the alfalfa heavy battery, so it pays special attention to power management to save power consumption; in general, In machine computers, the main power management used is for the central processing unit and other auxiliary access devices such as LCD monitors, hard disk drives, etc. Serial and parallel output V library, etc. When it is operated or used, g 卩 will partially or completely stop the work, or only supply and maintain power, and save power. It is called PMU < Power Managemen t Un i t: power management generation). For the power supply of the external cache memory, because the external cache memory has a high access rate and requires a fast speed, the system will always take the external fetcher 4 mind body always in the real-time working state. 9 -The Chinese paper standard (CNS) A4 (210X297mm) 83.3.10,000 (Please read the note on the back before filling this card) is applicable to the paper size of this book Printed by the Central Standards Bureau, Shellfish Consumer Cooperatives. 5. Description of the invention () The timing of power supply is effectively regulated, so M has not provided any power saving solutions or circuit devices to save its external cache memory when it is not in use. Unnecessary power consumption, extending the battery's time, without affecting the function of the system and the speed of execution: M-32K * 18 commonly used synchronous SRAM (Stat i Random Access Memory: static random (Access § Memory) As an example, f fetching memory as an example, the working power consumption is about 1.6W, and the unselected waiting and holding battery is only about 0.15W ~ 0.25W; when the computer is 256K or 512K external speed When taking memory, the working power consumption is about 6.4W or 12.8W, and its power consumption accounts for more than 1/4 to 1/3 of the conventional system; while in the unselected waiting state, it is only 0.8W ~ 1.6W, which is far from . And, during normal program execution, the cache memory in the central processing unit of the original host has about 80% ~ 85% of the available hit rate, so this 80¾ ~ 85% of the time, plus all I / O The cycle can keep the external cache memory in a power-saving state. Taking the aforementioned 5121 <: Xibubu cache memory as an example, it can reduce the original power consumption from 12.8W to about 3.28W (12.8W). ::: 15% + 1.6々85% = 3 * 28W). Therefore, the savings achieved are quite significant; if the central processing unit is in LT (stop) or goes to sleep, it can save more power consumption. This is the case for battery-powered portable computers. It is absolutely important; and in order to meet the requirements of Green PC for desktop computers, this demand is also indispensable. That is, the main purpose of the present invention is to provide a power management and control method for external cache memory; in particular, when an external cache memory is not usually used, only a small part of the sustain current is supplied, and When the external cache memory may be accessed, it is decided to give full power, and before it can be read and written, it is put into working state without affecting the timing cycle of writing and the system. Processing functions. Among them, the most feasible control method is to keep the external cache memory in a non-selected state by operating the "HIGH" and "L0W" signals input by the chip select line CS Ch [P SeLect) of the external cache memory. Waiting state of current (S band By 丨 or swim _ίί7 n · ^^^ 1 Hu nn ί ί 1 1 ^ 1 I (Please read the precautions on the back before filling this page) Order i 丨 line-V HAH fn ^ · This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 B7 V. Description of the working current of the invention (); As for when the external cache memory must be in working state, It is a very important technology when it is only necessary to maintain electrical energy. In order to effectively and appropriately control the working state of the external cache memory to achieve the purpose of saving power consumption, the main feature of the present invention is based on the accepted system bus M / IOtf line (memory or input / output device cycle control line), HLD Α line (bus holding approval line) and other signals to determine the status of the system and the use of the bus, M as the CE # signal Control basis The timing of power supply. The feasible method of implementation is the system memory cycle where the M / IO # line in the system bus is at "HIGH", or when the HLDA line is also "HIGH", that is, DMA (Direct Memory) Access · Direct memory access) mode, the system has a bus holding request signal, the external cache memory is required to enter the working state. The rest: at the time of the system non-memory week (M / IOtf = ”LOW”), prescription order I / O week month (M / Ι◦WELL = ”LOW.,”)
Stop Grant週期或HALT週期，且未產生腫流排持有認可訊 號（HLDA=”LOW”），作DMA要求時，皆由本發明之用電管理 控制方法所實施之用電管理控制電路輸出一節電控制訊號 ，操作該外接快取記憶體進入非工作的節電等待犹態，進 而達到省電節電的目的。 經濟部中央梯率扃Λ工消费合作社印装 (請先閲讀背面之注意事項再填寫本頁) 對於本發明所述之方法、特點及功效，Μ —本發明所 演生之實施例並配合所附圖式詳述如下，使之可對本發明 更進一步趨於了解。 第一圖係本發明實施例之電路圖。 第二圖係本發明實施例實施時，對於須使外接快取 記憶體處於工作狀態用電時機之糸統匯流排 有關訊號之時序圖。 第三圖係有關同步SRAM輸入訊號及動作參考表。 第畔圖係本發明實拖例實施時，對於須使外接快取 記憶體處於等待狀態節電時機之系統匯流排 有關訊號之時序____ 本紙張尺度逍用中國國家揉率（CNS ) A4规格（210X297公釐） 經濟部中央糅率扃—工消费合作社印装 A7 B7 五、發明説明（） 為了容晃了解本發明的發明特點及作動控制情形，因 此所舉的實施例係以基本組成要件之邏輯電路來探討。如 第一圖所示，為該用電管理控制電路實施例之電路圖，主 要可由一NOR之邏輯鬧所構成。該NOR鬧的兩個輸入端係 分別與電腦糸統中控制匯流排之M/IOtf及HLDA線連接，而 該NOR閘之輸出端是接至外接快取記憶體之同步SRAM的CS# (晶Μ選擇腳）端；另夕卜，同步SRAM白勺ADSC井（Address Status Cache Contro 1 1 er )端，基本上貝U與電腦系統内匯 流排之位址狀態線ADS#連接。 一般而言，糸統欲對記憶體謓寫資料時，特別是指首 先謓寫，旦快速、頻繁的外接快取記憶體，系統匯流排的 M/IOtt會圼”HIGH”的狀態，表匯流排週期為記憶體週期， 方令ADSit (位址狀態線）每有一短暫之”LOW”訊號，即開始一 匯流排週期，在RDYtf (資料備妥線）=”LOW”時，讓糸統完 成對外'接快取記憶體的讀寫動作。因此，請參第二圖，為 使外接快取記憶體能於讀寫前，即進入工作狀態且而不影 響到系統作業功能及時間；故於M/IOtf = ”HIGH”而為記憶體 週期時，即由該用電管理控制電路的NOR閘產生一”LOW”的 工作訊號至外接快取記憶體的CS#端，使同步SRAM先行進 入工作狀態，等待ADStt (位址狀態線）的”LOW”訊號，開始 一記憶體讀寫之匯流排週期。除此之外，在DMA模式狀態 ，亦應加Μ考盧的；即在外部設備要求DMA時，HLDA = ”HIGH”的匯流排持有認可，亦須有同樣的情形，經用電管 理控制電路的NOR閘產生一” LOW”的工作訊號，使該外接快 取記憶體進入工作狀態。 其餘，在I/O週其月（M/IO井=，，LOW”）、 stop GrantiS其月或 HALT週期，且未發生DMA要求時（HLDA=”LOW”），則該用電 管理控制電路NOR閘的輸出將維持為” H IGΗ ”的節電訊號給 外接快取記憶體（Extsrna 1 Cache )，而達到節電之用電管 壬里控制目白勺。 本紙張尺度適用中國國家樑準（CNS ) A4规格（21〇X297公釐） --------> Ϊ裝------訂------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部肀央揉車局貝工消费合作社印S. A7 B7___ 五、發明説明（） 須加Μ說明的，對於一般同步SRAM而言，由於要進入 非選擇的節電狀態（即Stand-By)，如第三圖所示參考資料 ，MHIGH" , rfn ADSCtt "L〇y" , _&同時 IS 在 時脈訊號（CLOCK)的上升緣，啟動致使該同步SRAM進入節 電的Stand-By狀態。纟象此，本發明之用電管理控制電路中 同步 SR AM&勺 ADSC 并(Address Status Cache Control ler) ，係與電腦系統内匯流排之位址狀態線ADStf連接，即如第 四圖戶斤示，在Μ/IOtf與HLDA皆為” LOW”的同時，用電管理控 制電路亦使CS#為”HIGH”，在ADStf開始一匯流排週期而圼 ” LOW”訊號時，亦由於糸統的時脈訊號上緣使同步SRAM進 入Stand-By狀態而節電。 而在目前大多數的電腦糸統上，尤其是筆記型電腦等 ，内部多設計有PMU (電源管理單元），在該單元動作時， 貝U系統進入Stop Grant週其月或CPU進入HALT之時機，將使 得前述本發明之用電管理控制電路，促使外接記憶體進入 Stand-By的節電狀態之頻率極高，則使省電效益更佳。 至於，本發明所演生的實施方式和態樣，除了 Μ上述 邏輯電路來達成外，在本發明特點的揭露後，亦可輕易由 微處理器结合處理程序，或由PLD (Programmable Logic De v i ce :可程式邏輯兀件）、AS IC (Appl ication Specific Integrated Circuit:特殊應用集成電路）等，可為特殊 功能而設計之時序控制器等類，皆可結合本發明之方法而 製作完成。 綜上所論，本發明之電腦系統外接快取記憶體的電源 管理控制方法，除了可在平常未使用到該外接快取記憶體 時，只供給其少部份之維持電流，而於可能被存取時，才 決定給予完全之電能；尤其是，在可能被謓寫之前，先使 之進入工作狀態，而不會影響到讀寫之時序週期，及系統 的執行處理功能。並且，本發明在實施上雖然可用一簡單 的實施態樣顒明，但其所态半的者堂柳於卻堂+ 對於η 本纸張尺度適用中國國家橾準（CNS ) Α4规格（210Χ297公釐） I mV m· nn ^fn w n^i ml —HI II 一 nn ml* 1^1 —^n n- (請先Htt背面之注意事項再填寫本頁) A7 λ_5Ζ_ 五、發明説明（） 可攜式電腦系統延長電池的使用時間，或桌上型電腦系統 在省電環保的訴求上，是絕對需要的。因此，本發明不僅 產生了極佳的效益，且為一新穎.、進步之設計，誠已符合 發明專利之要件,:、 請 先 閎 背 Λ 之 注Stop Grant cycle or HALT cycle, and no swollen current holding approval signal (HLDA = "LOW") is required. When a DMA request is made, the power management control circuit implemented by the power management control method of the present invention outputs a power saving. Control the signal, operate the external cache memory to enter the non-working power saving wait state, and then achieve the purpose of power saving. Printed by the Central Ramp of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling out this page). For the methods, features and effects described in the present invention, M — the embodiment of the present invention and cooperate with the The drawings are detailed below, so that the present invention can be further understood. The first diagram is a circuit diagram of an embodiment of the present invention. The second diagram is a timing diagram of signals related to the system bus when the external cache memory is required to be in working state when the embodiment of the present invention is implemented. The third picture is a reference table of synchronous SRAM input signals and actions. The following figure shows the timing of the signals related to the system bus that requires the external cache memory to be in a waiting state to save power when the actual implementation of the invention is implemented. __ This paper standard uses the Chinese National Kneading Rate (CNS) A4 specification ( 210X297mm) Central Government Department of the Ministry of Economic Affairs—Industrial and Consumer Cooperative Cooperative Printing A7 B7 V. Description of Invention () In order to understand the invention's invention characteristics and operation control situation, the examples given are based on the basic components. Logic circuit to explore. As shown in the first figure, it is a circuit diagram of the embodiment of the power management control circuit, which can be mainly composed of a logic logic of NOR. The two input terminals of the NOR are respectively connected to the M / IOtf and HLDA lines of the control bus in the computer system, and the output terminal of the NOR gate is the CS # (crystal) of the synchronous SRAM connected to the external cache memory. (M selects the pin) terminal; in addition, the synchronous SRAM ADSC well (Address Status Cache Contro 1 er) terminal is basically connected to the address status line ADS # of the bus in the computer system. Generally speaking, when you want to write data to the memory, especially when you first write, once the external cache memory is fast and frequent, the M / IOtt of the system bus will be in the "HIGH" state. The memory cycle is the memory cycle, so that each time ADSit (address status line) has a short "LOW" signal, it starts a bus cycle. When RDYtf (data ready line) = "LOW", let the system complete External 'read and write action of cache memory. Therefore, please refer to the second figure, in order to enable the external cache memory to enter the working state before reading and writing without affecting the system operation function and time; therefore, when M / IOtf = "HIGH" is the memory cycle That is, a “LOW” working signal is generated by the NOR gate of the power management control circuit to the CS # terminal of the external cache memory, so that the synchronous SRAM enters the working state first, and waits for the “LOW” of ADStt (address status line) Signal to start a bus cycle of memory reads and writes. In addition, in the DMA mode status, M Kalu should also be added; that is, when external devices require DMA, the bus with HLDA = "HIGH" holds approval, and must also have the same situation and be controlled by power management The NOR gate of the circuit generates a “LOW” working signal, which causes the external cache memory to enter the working state. The rest, in the I / O week (M / IO well = ,, LOW "), stop GrantiS month or HALT cycle, and no DMA request occurs (HLDA =" LOW "), the power management control circuit The output of the NOR gate will be maintained as a "H IGΗ" power-saving signal to the external cache memory (Extsrna 1 Cache), so as to achieve the power-saving control of the power tube. This paper standard is applicable to China National Standards (CNS) A4 size (21 × 297mm) -------- > Outfit -------- Order ------ Line (Please read the notes on the back before filling this page) Ministry of Economy S. A7 B7___ printed by Yongyang Rubbing Co., Ltd. Fifth, the invention description () must be added, for general synchronous SRAM, because it is to enter a non-selected power-saving state (ie Stand-By), such as the third The reference material shown in the figure, MHIGH ", rfn ADSCtt " L〇y ", _ & At the same time, IS is on the rising edge of the clock signal (CLOCK), and starts the synchronous SRAM into a power-saving Stand-By state. Like this, The SR AM & ADSC synchronization (Address Status Cache Control ler) in the power management control circuit of the present invention is The address status line ADStf of the bus in the computer system is connected, that is, as shown in the fourth figure, while M / IOtf and HLDA are both "LOW", the power management control circuit also makes CS # "HIGH", When ADStf starts a bus cycle and sends a "LOW" signal, it also saves power due to the clock edge of the system that causes the synchronous SRAM to enter the Stand-By state, and saves power. On most current computer systems, especially notes PMUs (power management units) are often designed in internal computers. When the unit operates, the timing of the U system entering the Stop Grant week or the CPU entering the HALT will make the aforementioned power management control circuit of the present invention promote The frequency at which the external memory enters the Stand-By power-saving state is extremely high, which makes the power-saving benefit better. As for the implementation modes and aspects generated by the present invention, in addition to the above-mentioned logic circuits, the features of the present invention After the disclosure, it can also be easily combined with a processing program by a microprocessor, or by PLD (Programmable Logic Devi ce), AS IC (Application Specific Integrated Circuit: special application integration) Road) and the like, the timing controller can be designed for specific functions or the like, can be combined method of the invention produced. To sum up, the power management control method for the external cache memory of the computer system of the present invention can only supply a small part of the maintenance current when the external cache memory is not normally used, and may be stored in the external cache memory. When it is taken, it is decided to give full power; in particular, before it can be copied, it should be put into working state without affecting the timing cycle of reading and writing and the system's execution processing function. In addition, although the present invention can be implemented in a simple way, it can be used in the same way. For the paper size, the Chinese National Standard (CNS) A4 specification (210 × 297) is applicable. (Centimeter) I mV m · nn ^ fn wn ^ i ml —HI II—nn ml * 1 ^ 1 — ^ n n- (please note the precautions on the back of Htt before filling out this page) A7 λ_5Z_ V. Description of the invention () OK A portable computer system to extend battery life or a desktop computer system to save energy and protect the environment is absolutely necessary. Therefore, the present invention not only produces excellent benefits, but also is a novel and progressive design, which has already met the requirements of the invention patent:
I 旁 裝 訂 •線 經濟部中央揉準局貝工消费合作杜印装 本紙張尺度逍用中國國家橾车（CNS〉Α4规格（210X297公釐）I Side Binding • Thread Printed by the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China. This paper size is used in China's national car (CNS> Α4 size (210X297 mm)