五、發明說明（1) 本發明係有關於自我對準之複式金 ^、 之新穎製程’其製程新穎、簡單、特別：多重内連線 而適用於一般生產線上常用設備 f一道光罩， 線之製程。 金屬鑲嵌多重内連 在超大型積體電路元件之製程中， 的積體電路的發展需求，在晶片上有限的日趨複雜 上之金屬層’I已成為半導體發展的_種趨勢。：兩層以 保金屬層間具有良好的通道，以形成—個完如何確 是超大型積體電路元件製程中之一重要課題。、、路，亦 傳統的複式金屬鑲嵌（dual damascene)多重内 製作中，是利用二次光阻微影來定義内連》 線的 (interconnect)區域和介層通道（via)區域；多次的 製程’有曝光聚焦上的困難’而影響微影像傳遞的精確^ 與解析度。況且，使用兩道光罩也會使所需製造成本增 加。 近年來’日本三菱公司的T UEDa，τ UEHARA和 M_ NISH 10 於 1 995 年 VMIC C〇nference 中，揭示一種僅需一 道光阻罩幕以形成内連線和介層通道之製程。其係利用一 次的微影成像和乾式蝕刻形成線較寬之介層通道區域、和 線寬較窄之内連線區域，在乾式蝕刻過程中，因再沈積 (redeposit)現象，而造成線寬較窄之内連線區蝕刻深 度’較介層通道區域蝕刻深度為漫，而對金屬鑲嵌製程有 不利之影響。雖然此一製程簡化相當多之程序，但是乾式 蝕刻再沈積之厚度並不容易控制，而具有内連線阻值上 C:\Program Files\Patent\0522-3958-E.ptd第 4 頁 五、發明說明（2) 揚之缺點。 «習知複式金屬鑲嵌多重内連線之製程，存在 :::微影圖像轉移精確度與解析 阻值會上揚等之缺點。 久門逋踝 對準思本發明人先前已於8 6年5月提出-種自我 統數程3 鑲嵌多重内連線之製造方法，以便改進傳 編號：331〇ί)上边缺點，並且已取得中華民國專利（公告 之製ϋΠΓ我對準之複式金屬鑲喪多重内連線 I S我用一道光阻罩幕、只有-次微影成 ί好式完成内連線和介層通道，並且維持 良好：内連線阻值’而改進習知技術之缺點。 更可廣為 再提出追 :蚩見發明人為使上述專利能夠更趨完善 !，特別再針對上述專利予以強化 〃、]，俾能達到更佳之製程效果和實用性„ 金屬述目60 ’本追加案提出-種自我對準之複式 線：製造方法，包括如下步驟:⑴依 一/幕層於具有線路元件之基材之 罩，對上述第Λ 和第二導線區圖案之光 么第厂導線區開口和第二導線區開口於上述=以， 二罩幕層’至露出上述第一罩幕層二層及⑷：：上述第 内四方形連接區中之上述介電第—導線區開口 述介電層，（5)去除四方形連接區 C:\PrograroFiles\Patent\0522-3958-E.ptd第 5 頁 五 發明說明（3) _ =層：Γ上述基材；以及，(6)選擇‘二 程以罩幕層；純，進行後續金屬連線製 I 我對準複式金屬鑲嵌多重内連線。 方形i接區上ί第二導線區包括：長條狀導線區、以及四 區之上.7 述四方形連接區係重疊於上述長條狀導線 和第一莲方形連接㊣之冑抓大於上述長條導線區 η線區之寬度di;而/ 2。 圖式之簡單說明： τ t ί 2本發明之上述目的、特徵和優點能更明顯易僅， ’ 較佳實施例’並配合所附圖式，作詳細說明如 下： 第1 1 F圖係顯示本發明方法之流程剖面圖； 第2Α〜2Β圖係顯示本發明方法中，導線區域和通道區 之可能佈局圖；以及 第3 A〜3B圖係顯示本發明後續連線製程之剖面圖。 標號說..明： 1〜基材；2〜介電層；3〜第一罩幕層；4〜第二罩幕層； 21〜第一導線區開口； 22〜第二導線區開口； 2〇~光罩；23~ 第一導線區；24〜第二導線區；24a〜長條狀導線區；24b〜 方形連接區；5〜導電層；25〜導電層；心〜第一導線區開口 之寬度；1〜第二導線區開口寬度；d3〜第二罩幕層沈積之 厚度。 實施例： 以下將配合第1A~1F圖所顯示之流程剖面圖，來詳細V. Description of the invention (1) The present invention relates to a novel process of self-aligned double-layered metal ^, which has a novel, simple, and special process: multiple internal interconnections, which are suitable for common equipment on general production lines. The process. Metal inlay multiple interconnects In the manufacturing process of ultra-large integrated circuit components, the development requirements of integrated circuits, the limited and increasingly complex metal layers on the wafer, have become a trend in the development of semiconductors. : Two layers to ensure that there is a good channel between the metal layers to form—how to finish it is indeed an important issue in the process of manufacturing ultra-large integrated circuit components. , Road, and traditional dual metal inlay (dual damascene) multiple internal production, the secondary photoresist lithography is used to define the interconnect area and the via area; multiple times The process 'has difficulty in exposure and focus' affects the precision ^ and resolution of micro-image transmission. Moreover, the use of two masks also increases the required manufacturing costs. In recent years, T UEDa, τ UEHARA, and M_NISH 10 of Mitsubishi Corporation in Japan revealed in 1995 VMIC Connference a process that requires only a photoresist mask to form interconnects and vias. It uses a single lithography imaging and dry etching to form a wide-line interlayer channel area and a narrower line-width interconnect area. During the dry-etching process, the line width is caused by the redeposition phenomenon. The etch depth of the narrower interconnect region is more diffuse than the etch depth of the via channel region, which adversely affects the metal damascene process. Although this process simplifies quite a lot of procedures, the thickness of dry-etching and redeposition is not easy to control, and it has C: \ Program Files \ Patent \ 0522-3958-E.ptd on the resistance of the interconnect. Description of the Invention (2) Disadvantages of Young. «The conventional multiple metal inlay multi-connection process has the disadvantages of ::: lithographic image transfer accuracy and analytical resistance will increase. Jiumen Jiu ankle alignment thinking The present inventor has previously proposed in May 1986-a method of manufacturing self-counting process 3 mosaic multiple interconnects to improve the serial number: 331〇ί), and has obtained Chinese Patent of the Republic of China (Announced system) ΠΓ I aligned multiple metal inlaid multiple interconnects IS I used a photoresist mask to complete the interconnects and interposer channels only with sub-photolithography, and maintained well: The shortcomings of the conventional technology are improved by the internal resistance value. It can be widely pursued again: see the inventor to make the above-mentioned patents more perfect! In particular, the above-mentioned patents will be strengthened. Good process effect and practicability „Metal Catalogue 60 'This additional proposal proposes a self-aligned duplex line: a manufacturing method, including the following steps: converting a layer / curtain layer to a cover of a substrate with circuit components, The light of the first Λ and the second wire area patterns is the opening of the first wire area and the second wire area openings are as described above, and the second cover layer is exposed to the first layer and the second cover layer: The introduction in the square connection area The first layer of the wire area describes the dielectric layer, (5) remove the square connection area C: \ PrograroFiles \ Patent \ 0522-3958-E.ptd page 5 of the invention description (3) _ = layer: Γ the above substrate; And, (6) select 'Second pass to cover the curtain layer; pure, for the subsequent metal wiring system I aligned with multiple metal inlay multiple interconnects. The second wire area on the square i junction area includes: long wire 7 and the above four areas. 7 The quadrangular connection area overlaps the strip-shaped wire and the first lotus-shaped square connection, and the grip is larger than the width di of the η-line area of the strip conductor area; and / 2. A brief description of the formula: τ t ί 2 The above-mentioned objects, features, and advantages of the present invention can be more obvious and easy. The "preferred embodiment" and the accompanying drawings are described in detail as follows: Figure 1 1 F shows this A cross-sectional view of the method of the invention; Figures 2A to 2B are diagrams showing possible layouts of the conductor area and channel area in the method of the invention; and Figures 3 A to 3B are sectional views showing subsequent connection processes of the invention. .. Ming: 1 ~ substrate; 2 ~ dielectric layer; 3 ~ first cover layer; 4 ~ second cover Layer; 21 ~ first wire area opening; 22 ~ second wire area opening; 20 ~ mask; 23 ~ first wire area; 24 ~ second wire area; 24a ~ long wire area; 24b ~ square connection 5 ~ conductive layer; 25 ~ conductive layer; core ~ width of the opening of the first wire region; 1 ~ width of the opening of the second wire region; d3 ~ thickness of the second mask layer. Example: The following will cooperate with the first 1A ~ 1F diagram of the process cross section, for details
C:\ProgramFiles\Patent\0522-3958-E.ptd第 6 頁 五、發明說明（4) 說明本發明之方法。 步驟一 依序形成一介電層2、一第一罩幕層3於具有線路元件 之基材1之上，如第1A圖所示。 其中’沈積上述介電層2(亦可稱為内層介電質，ILd) 之厚度約為0.5〜l//m。適合作介電層2的材料，可為一般 之介電質，例如：硼磷矽玻璃、硼矽玻璃、磷矽玻璃、氧 化矽（SiN)、四乙烷氧矽（TEOS，Si(OC2H5)4)、低介電常數 (low K)之介電質等❶沈積方式可以是傳統的氣相沈積 法0 又，於介電層2上之第一罩幕（hard mask)3可以是， 厚度約為2000~5000埃之金屬層或金屬化合物層，例如 鋁、鉻、鎳、AlCu/TiN等材質之中加以選擇，或是非導電 性物質例如氮化矽等；沈積方式可以分別是金屬濺鍍法、 亦或是氣相沈積法。 步驟二 使用定義有第-導線區23和第二導線區24圖案之光罩 Γ景如圖所示）’對上述第一罩幕層和上述介電層進行 微影蝕刻，《形成第-導線區開口21和第 於上述介電層2中，如第1B圖所示。 $ $ “ 參二第2A圖，上述第二導線區24包括：長條狀導線區 24a、以及四方形連接區24b。上述四方形連接區μ係重 疊於上述長條狀導線區24a之上。上诚阳士以± 、 度4最好大於第一導線區22寬度心之2倍以上為佳。C: \ ProgramFiles \ Patent \ 0522-3958-E.ptd page 6 5. Description of the invention (4) Describe the method of the present invention. Step 1 A dielectric layer 2 and a first cover layer 3 are sequentially formed on a substrate 1 having circuit elements, as shown in FIG. 1A. Among them, the thickness of the above-mentioned dielectric layer 2 (also referred to as an interlayer dielectric, ILd) is about 0.5 to 1 // m. Suitable materials for the dielectric layer 2 can be general dielectric materials, such as: borophosphosilicate glass, borosilicate glass, phosphosilicate glass, silicon oxide (SiN), tetraethane oxysilicon (TEOS, Si (OC2H5) 4), low dielectric constant (low K) dielectric and other plutonium deposition methods can be traditional vapor deposition method 0, the first hard mask 3 (dielectric layer 2) on the dielectric layer 2 can be, thickness Metal layer or metal compound layer of about 2000 ~ 5000 angstroms, such as aluminum, chromium, nickel, AlCu / TiN, etc., or non-conductive materials such as silicon nitride; the deposition methods can be metal sputtering Method, or vapor deposition method. Step 2: Use a mask Γ defined with the patterns of the first-conductor region 23 and the second-conductor region 24 as shown in the figure) to perform lithographic etching on the first mask layer and the dielectric layer, and form the first-conductor The region openings 21 and the second dielectric layer 2 are as shown in FIG. 1B. As shown in FIG. 2A, the second wire area 24 includes a long wire area 24a and a square connection area 24b. The square connection area μ overlaps the long wire area 24a. It is preferable that the upper and lower sides of the first honesty are ±, degree 4 is greater than two times the width center of the first lead region 22.
C:\Program Files\Patent\0522-3958-E_ ptd第 五、發明說明（5) 上述第一導線區22即代表一般定義内連線之區域，而 第二導線區24中之方形連接區24b即代表用以定義將透過 介層洞（via)，而和基材1上之導電層連接之區域，而長條 狀導線區24a代表定義另一内連線之區域。第2a圖和第2B 圖沿著A-A’和B-B’切線所見之剖面圖，即如第1B圖所示。 另外，方形連接區24b中虛線所圍之區域25即代表在後續 製程中，所將要形成介層洞之區域。 如第2A圖所示，四方形連接區2 4b，係左右對稱於上 述長條狀導線區24a延伸之方向，而重養於上述長條狀導 線區24a之上，此為一般之佈局圖案。 另外’如第2B圖所示’上述四方形連接區24b係以其 一邊平行於上述長條狀導線區24a延伸之方向，而重疊於 上述長條狀導線區24b之上，在此圖中，上述四方形連接 區24b未與上述長條狀導線區24a重疊之部分，均位於上述 長條狀導線區2 4 a相同之一側。 步驟三 移除光阻，並再次沈積一厚度t為1 〇 〇 〇〜5 0 0 0埃之非 導電性第一罩幕層4 ’沈積方式可為化學氣相沈積法。 上述第二罩幕層係選自SiN、Si〇N。又當上述介電廣 為具低介電常數之介電質時’上述第二罩幕層亦可以使用C: \ Program Files \ Patent \ 0522-3958-E_ ptd Fifth, the description of the invention (5) The above-mentioned first wire area 22 represents the area generally defining the interconnection, and the square connection area 24b in the second wire area 24 That is, it is used to define a region that will be connected to the conductive layer on the substrate 1 through a via, and the strip-shaped wire region 24a represents a region that defines another interconnect. Figures 2a and 2B are cross-sectional views taken along the A-A 'and B-B' tangent lines, as shown in Figure 1B. In addition, the area 25 surrounded by the dotted line in the square connection area 24b represents the area where a via hole is to be formed in the subsequent process. As shown in Fig. 2A, the square connection area 24b is symmetrical about the extending direction of the above-mentioned long wire area 24a, and is cultivated on the above-mentioned long wire area 24a. This is a general layout pattern. In addition, as shown in FIG. 2B, the above-mentioned rectangular connection region 24b is superimposed on the above-mentioned elongated wire region 24b with a side parallel to the extending direction of the above-mentioned elongated wire region 24a. In this figure, Portions of the rectangular connection area 24b that do not overlap the elongated wire area 24a are all located on the same side of the elongated wire area 24a. Step 3: The photoresist is removed, and a non-conductive first mask layer 4 ′ having a thickness t of 1000˜500 angstrom is deposited again by a chemical vapor deposition method. The second cover layer is selected from SiN and SiON. And when the above-mentioned dielectric is widely a dielectric with a low dielectric constant, the above-mentioned second cover layer may also be used.
Si〇2。 而此第一罩幕層4沈積之厚度(I3必須能夠將第一導線 區開口21填滿，但是不會將第二導電區開口 22填滿，也就 是說d〗、da、da間具有1 / 2d2>d3>l /2巾之關係，結果如第lcSiO2. The thickness of the first cover layer 4 (I3 must be able to fill the opening 21 of the first wire region, but not the opening 22 of the second conductive region, that is, d, da, da have 1 between / 2d2 > d3 > l / 2
C:\Program Files\Patent\0522-3958-E.ptd第 8 頁 五、發明說明（6) 圖所示。 步驟四 接著回蝕第二硬罩幕層4，回蝕之深度約為大於或等 於第二硬罩幕層4之厚度，也就是回蝕至同時露出第一罩 幕層3、以及第二導線區開口 22中之介電層2。由於是利用 非等向性（anisotropic)餘刻，所以在第二導線區開口 22 之側壁上會有襯墊（Spacer)形成，結果如第1D圖所示。 步驟五 以回蝕殘留之第一幕罩層3和第二罩幕層4之襯墊作為 姓刻罩幕’直接以選擇性式蝕刻方式蝕刻露出於第二導線 區開口 22之介電層2，直到露出基材1以形成介層洞 (via)，如第1E圖所示。 步驟六 若上述第一、第二罩幕層均為非導電性物質（例如 Si N)，則選擇性去除上述殘留之第一罩幕3和第二罩幕層 4，結果如第if圖所示。 爾後依需要進行其它之金屬連線製程，而完成以自我 對準方式成複式金屬鑲嵌多重内連線。 雖然本實施例中之第二罩幕層係由非導電性物質形 成，但是亦可使用導電性物質。所以若上述 非導電性物質（例如SlN)，而第二軍幕層為導電性物f (例 如AlCu/TiN)時，則可先沈積一導電層5於第一、 ： f3A ST ’再使用化學機械研磨* _或疋RIE回姓法’去除部分導電層5以露出上述第一C: \ Program Files \ Patent \ 0522-3958-E.ptd page 8 5. Description of the invention (6) Figure. Step 4 is to etch back the second hard cover layer 4 with a depth greater than or equal to the thickness of the second hard cover layer 4, that is, to etch back to expose the first cover layer 3 and the second wire at the same time. The dielectric layer 2 in the area opening 22. Because anisotropic relief is used, a spacer is formed on the side wall of the opening 22 of the second wire region, and the result is shown in FIG. 1D. Step 5: Use the liners of the first and second mask layers 3 and 4 as the last mask to etch back the dielectric layer 2 directly exposed through the opening 22 of the second wire region by selective etching. , Until the substrate 1 is exposed to form a via, as shown in FIG. 1E. Step 6: If the first and second cover layers are both non-conductive materials (such as Si N), the remaining first cover 3 and second cover layer 4 are selectively removed. The result is as shown in FIG. Show. After that, other metal connection processes are performed as required, and the multiple metal inlay multiple interconnections are completed in a self-aligned manner. Although the second cover layer in this embodiment is formed of a non-conductive material, a conductive material may be used. So if the above non-conductive material (such as SlN) and the second military curtain layer is conductive material f (such as AlCu / TiN), a conductive layer 5 can be deposited on the first, f3A ST ', and then use chemistry Mechanical grinding * _ or RIE method to remove the part of the conductive layer 5 to expose the first
五、發明說明（7) f幕層3，如此即完成以 重内連線之制| ** +方式成複式金屬鑲嵌多 逆竦之製作，如第36圖所示。 續敢夕 士政本發明雖以較佳實施例揭露如上，麩盆光非m 本發明，任何熟習此項技藝 …、其並非用以限定 範圍内，當可做' ，不脫離本發明之精神和 圍當視後附之巾請專利範圍所界定者為Ϊ本發明之保護範 C:\Program Files\Patent\0522-3958-E.ptd第 10 頁V. Description of the invention (7) f curtain layer 3, so that the production of the double interconnected system | ** + is completed into a multi-metal inlay, as shown in Figure 36. Although the present invention is disclosed in the preferred embodiment as above, the bran is not the invention. Anyone who is familiar with this technology ... is not intended to limit the scope, and can be used as it, without departing from the spirit of the invention. The towel attached to Hewei Dangde as the back, please define the scope of the patent as the protection scope of the present invention: C: \ Program Files \ Patent \ 0522-3958-E.ptd page 10