經濟部中央標隼局員工消費合作社印製 A7 B7_ 五、發明説明（I ) 詳細說明： 本發明主要係提供一種半導體之閘極的製造方法，尤 指一種避免金屬矽化物之尖峰效應的閘極結構製造方法 複晶砂（poly-crystalline silicon ; polysilicon)經 常作爲現今超大型積體電路（ultra large scale integration; ULSI)中場效電晶體的閘極（gate electrode)。但隨著元件積集密度的增加，線寬（line-width) 變小且疊層的厚度增加， 這要求閘極的電阻率 (resistivity)降低，並且具有高溶點以耐後續之高溫製 程。複晶矽化金屬（polycide)，亦即金屬矽化物 (si 1 icide)7複晶矽所組成的疊層結構正可以符合這樣的 要求，目前常用之金屬矽化物多爲過渡金屬之矽化物 (refractory metal silicide)，其中又以矽化鶴(tungsten silicide)最普遍，除了可以作爲場效電晶體之閘極外，還 可以作爲內連線（interconnect)和二極體的射極 (emitter)。習用之閘極結構如圖一所示，首先在矽基板11 上形成通道阻絕10A(channel stop)、場氧化層l〇B(field oxide)和一閘氧化層12 (gate oxide)，複晶矽13接著沉 積在閘氧化層之上，最後是金屬矽化物14的沉積，經過微 影製程（lithography)後，一閘極結構就形成了。再經過源 極/汲極的淡摻雜（lightly doping)、間隙壁(spacer)的形 成、和源極/汲極的重摻雜(heavily doping)後，一場效電 晶體的主體’包括閘極、汲極和源極於焉完成，其中圖一 的15爲輕摻雜區，16爲間繪壁，17爲重摻雜區。 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝- 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（>) 但是複晶矽和金屬矽化物間的反應將會造成其界面的 變化，這反應通常發生在金屬矽化物形成時，或是後續之 高溫製程，如間隙壁之形成、源極/汲極之摻雜或層間介電 層(interlevel dielectric)之平坦化等。請參閱圖二，金 屬砂化物在複晶砍中的突起(protrusion)或尖峰(spiking) 將會嚴重影響元件的電性。在J. P. ?ambino等人發表的 論文中（J. Electrochem. Soc. 136，1989，p2063)，提到 多種機制來解釋矽化物在複晶矽中之突起或尖峰發生的原 因，其中相當主要的一個機制便是因爲介於複晶矽和金屬 矽化物間的原始氧化層(native oxide)造成了一個不連續 的擴散阻障層；此不均勻的原始氧化層中厚度很薄之處也 正是複晶砍和金屬砍化物彼此擴散（interdiffusion)發生 的地方，也就是說金屬原子或矽會沿著晶粒界面(grain boundary)而移動。另一方面在後續氧化製程中，金屬矽化 物經高溫氧化而形成一層二氧化矽(Si02)於砍化物之上，此 時若是矽的供應不足也將造成金屬矽化物在複晶矽層中的 突起或是尖峰；矽的供應會不足，是因爲矽化鎢在褪火 (annealing)後會從多矽狀態（WSi2.6)轉化爲多鎢狀態 (WSi2.2)，所以矽必須從複晶矽層沿著晶粒界面擴散而上以 提供反應所需的矽原子；此時不均匀之氧化層會成爲擴散 之阻障層，使界面之複晶矽層形成局部的空洞(void)，經 矽化鎢之回填就形成如圖二的突起或尖峰21 ;此尖峰效應 將會隨著晶粒界面的增加而愈趨嚴重，但無疑地，後續仍 有多重高溫製程，因此當矽化鎢之突起或尖峰延伸而達到 3 'i--------广、—裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 •-:氣 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7_ 5. Description of the Invention (I) Detailed description: The present invention mainly provides a method for manufacturing a semiconductor gate, especially a gate that avoids the spike effect of metal silicide. Structure manufacturing method Poly-crystalline silicon (polysilicon) is often used as the gate electrode of field-effect transistors in ultra large scale integration (ULSI). However, as the component density increases, the line-width becomes smaller and the thickness of the stack increases. This requires that the gate electrode's resistivity be reduced and that it has a high melting point to withstand subsequent high-temperature processes. A polycide, a si 1icide, and a 7-layer polysilicon stack structure can meet such requirements. The most commonly used metal silicides are refractory transition metals. Metal silicide (tungsten silicide) is the most common. In addition to serving as the gate of a field effect transistor, it can also be used as an interconnect and an emitter of a diode. A conventional gate structure is shown in FIG. 1. First, a channel stop 10A (channel stop), a field oxide 10B (field oxide), and a gate oxide 12 (gate oxide) are formed on a silicon substrate 11. Polycrystalline silicon 13 is then deposited on the gate oxide layer, and finally the metal silicide 14 is deposited. After lithography, a gate structure is formed. After further lightly doping of the source / drain, formation of the spacer, and heavy doping of the source / drain, the body of the field effect transistor includes the gate The drain, drain, and source are completed in erbium. Among them, 15 in FIG. 1 is a lightly doped region, 16 is a partition wall, and 17 is a heavily doped region. 2 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (please read the notes on the back before filling out this page) • Binding-Order printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Invention Explanation (>) However, the reaction between the polycrystalline silicon and the metal silicide will cause the interface to change. This reaction usually occurs when the metal silicide is formed, or the subsequent high temperature processes, such as the formation of the barrier wall, the source Doping of the / drain or planarization of the interlevel dielectric. Please refer to Figure 2. The protrusion or spiking of the metal sand compound in the polycrystalline cleave will seriously affect the electrical properties of the device. In a paper published by JP? Ambino et al. (J. Electrochem. Soc. 136, 1989, p2063), various mechanisms are mentioned to explain the reason for the occurrence of the protrusions or spikes of silicides in polycrystalline silicon. The mechanism is because the native oxide layer between the polycrystalline silicon and the metal silicide creates a discontinuous diffusion barrier; the very thin thickness of this uneven original oxide layer is exactly the complex Where crystal cleavage and metal cleavage interdiffusion occur, that is, metal atoms or silicon will move along the grain boundary. On the other hand, in the subsequent oxidation process, the metal silicide is oxidized at high temperature to form a layer of silicon dioxide (Si02) on the cleavage. At this time, if the silicon supply is insufficient, the metal silicide in the polycrystalline silicon layer will be caused. Protrusions or spikes; the supply of silicon will be insufficient because tungsten silicide will transition from a polysilicon state (WSi2.6) to a polytungsten state (WSi2.2) after annealing, so the silicon must be changed from polycrystalline silicon The layer diffuses up along the grain interface to provide the silicon atoms required for the reaction; at this time, an uneven oxide layer will become a barrier to diffusion, and the interface polycrystalline silicon layer will form a local void, which is silicified The backfilling of tungsten will form a protrusion or spike 21 as shown in Figure 2. This spike effect will become more serious as the grain interface increases. However, there is no doubt that there are still multiple high-temperature processes. Therefore, when the tungsten silicide protrusion or spike Extend to reach 3'i -------- Canton, ----- (Please read the notes on the back before filling this page) Order •-: The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm)
I 經濟部中夬標率局員工消費合作社印製 A7 B7 五、發明説明（3 ) 閘氧化層時，平帶電壓(flat band voltage)會發生改變而 嚴重影響元件的電性和良率(yield)。 本發明之目的： 因此，本發明之主要目的在於提供一種改進半導體元 件之閘極電性的方法。 本發明之另一目的乃是提供一種避免複晶矽擴散至矽 化鶴的方法。 本發明之另一目的乃是提供一種避免矽化鎢擴散至複 晶矽而形成突起或尖峰的方法。 本發明之另一目的乃是提供一緩衝層(buffer layer) 以提供後續氧化製程中所需的矽原子。 本發明之再一目的在於提供一種維持閘極之低電阻的 方法。 (1)圖示簡要說明 圖一爲習知的閘極結構剖面圖。 圖二爲習知閘極結構中矽化物的突起和尖峰之剖面 圖。 圖三爲本發明之矽基板於閘氧化層和複晶矽形成後 的剖面圖。 圖四爲本發明之矽基板接續圖三於非晶矽和矽化鎢 成後的剖面圖。 圖五爲本發明接續圖四而經由微影製程形成閘極後 的剖面圖。 y 4 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 1 OB-場氧化層 12-閘氧化層 14-矽化鎢 16-間隙壁 21-矽化鎢之突起和尖峰 Λ7 B7 五、發明説明（4 ) 圖六爲本發明接續圖五，經由源極/汲極之摻雜和形 成間隙壁之後的剖面圖β (2)圖號標示： 10A-通道阻絕 11-矽基板 13-複晶矽 15-淡摻雜區 Π-重摻雜區 41-非晶矽 以下提出此本發明之最佳實施例，但本發明之金屬矽 化物並不限於矽化鎢，而是涵蓋過渡金屬（transition metal)之金屬砂化物。 如圖三所示，矽基板爲缺陷密度(defect density)較低 之結晶面爲<100>的?型矽晶片，以硼(Boron)爲離子源進 行硼原子的植入而形成通道阻絕10A(channel stop)，並由 區域氧化法（local oxidation)進行隔離製程以形成場氧化 層 10B(field oxide)。接著由熱氧化法(thermal oxidation) 生長一閘氧化層12於主動區域之矽基板上，其中反應的溫 度約在90G°C左右，閘氧化層的厚度介於4GA到4G0A之間。 煩請繼續參閱圖三，複晶矽13接著由低壓化學氣相沈積 法（low pressure chemical vapor deposit ion)沈積於蘭 氧化層之上，沈積的壓力介於0. 3到G. 6Torr之間，溫度介 於575°C到650°C之間，複晶矽的厚度介於1300到17GGA之 間。接著以離子植入法（ion implantation)將鱗 L. 111------"衣----1-I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 經濟部中央樣準局員工消費合作社印製 A? B7 五、發明説明（/ ) (phosphorous)摻雜到複晶矽中以降低其電阻率 (resistivity)，摻雜後複晶矽中之磷的濃度介於1.0X1019 到 1. 0xl022/cm3之間。 接著進行預清(pre-cleaning)的步驟，將整個晶片於氫 氟酸(HF)之溶液中短時間浸洗(dip)，以去除晶片表面之原 始氧化層。但是原始氧化層很難被去除乾淨，於是殘留於 複晶矽上之不均勻的氧化層就會在後續製程中造成矽化鎢 之突起或尖峰。爲改善這種弊端，本發明特在預清步驟後 沈積一層非晶矽。 如圖四所示，一薄層的非晶砂(amorphous silicon)由 濺鑛法(sputtering)形成於複晶砍之上，其厚度約1〇〇到 300A。這裡使用濺鍍法有多重的好處，包括它能沈積許多 不同種類的金屬或介電質，能夠忠實地複製靶(target)的 成分於沈積的薄膜上，並且相當重要的，濺鍍法也是成本 較低的一種薄膜沈積法。 接著砂化鶴(WSix)同步地濺鍍（in-situ deposition) 於非晶矽上方，所使用的靶是砍鎢合金板，生長厚度約800 到1200A的矽化鎢。非晶矽和矽化鎢由同步濺鍍法沈積，能 夠簡化真空處理的製程，因爲同步濺鍍即是使非晶矽和矽 化鎢由同一個機台沈積，因此不需額外的破真空(vacuum breaking)步驟；此外，由於晶片不會外露於空氣中，將可 避免原始氧化層生長於非晶矽和矽化鎢之間。經過微影製 程後’依序蝕刻金屬矽化物、非晶矽層、複晶矽層和閘氧 化層’定義好的閘極結構如圖五所示。最後再經過高溫褪 6 本紙張尺度適用中國國家槔準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) J___ i L ml f^m In— HI -VI mB · 、?τI . . -a · -- • n nnI Printed A7 B7 by the Consumer Cooperatives of the Bureau of Standards and Standards of the Ministry of Economic Affairs. 5. Description of the Invention (3) When the gate oxide layer is changed, the flat band voltage will change, which will seriously affect the electrical properties and yield of the components. . OBJECTS OF THE INVENTION: Therefore, the main object of the present invention is to provide a method for improving the gate property of a semiconductor device. Another object of the present invention is to provide a method for preventing the diffusion of polycrystalline silicon into silicified cranes. Another object of the present invention is to provide a method for preventing tungsten silicide from diffusing into the polycrystalline silicon to form protrusions or spikes. Another object of the present invention is to provide a buffer layer to provide silicon atoms required in subsequent oxidation processes. Another object of the present invention is to provide a method for maintaining a low resistance of a gate electrode. (1) Brief description of the diagram Figure 1 is a sectional view of a conventional gate structure. Figure 2 is a cross-sectional view of the silicide protrusions and spikes in the conventional gate structure. Figure 3 is a cross-sectional view of the silicon substrate of the present invention after the gate oxide layer and the polycrystalline silicon are formed. Figure 4 is a cross-sectional view of the silicon substrate of the present invention following Figure 3 after the amorphous silicon and tungsten silicide are formed. FIG. 5 is a cross-sectional view of the present invention following FIG. 4 and forming a gate electrode through a lithography process. y 4 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) Order 1 OB-field oxide layer 12-gate oxide layer 14-tungsten silicide 16 -Gap wall 21-Protrusions and spikes of tungsten silicide Λ7 B7 V. Description of the invention (4) Fig. 6 is a continuation of Fig. 5 of the present invention. After doping and forming the barrier wall through source / drain doping β (2) Figure numbers indicate: 10A-channel block 11-silicon substrate 13-polycrystalline silicon 15-lightly doped region Π-heavily doped region 41-amorphous silicon The best embodiment of the present invention is proposed below, but the metal Silicides are not limited to tungsten silicides, but metal sands that cover transition metals. As shown in Fig. 3, the silicon substrate is a? -Type silicon wafer with a low defect density and a crystal surface of < 100 >. Boron is used as an ion source to implant boron atoms to form a channel barrier of 10A (channel stop), and an isolation process is performed by local oxidation to form a field oxide layer 10B (field oxide). Next, a gate oxide layer 12 is grown on the silicon substrate in the active region by thermal oxidation. The reaction temperature is about 90G ° C. The thickness of the gate oxide layer is between 4GA and 4G0A. Please continue to refer to Figure 3. The polycrystalline silicon 13 is then deposited on the blue oxide layer by low pressure chemical vapor deposition ion, and the deposition pressure is between 0.3 and G. 6 Torr, temperature. Between 575 ° C and 650 ° C, the thickness of the polycrystalline silicon is between 1300 and 17GGA. Then use ion implantation to remove the scale L. 111 ------ " clothing ---- 1-I (please read the precautions on the back before filling this page). The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm). Printed by the consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. A? B7 V. Description of the invention (/) (phosphorous) Doped to 0xl022 / cm3 之间。 To reduce the resistivity of the polycrystalline silicon (resistivity), the concentration of phosphorus in the doped polycrystalline silicon is between 1.0X1019 to 1.0xl022 / cm3. Then, a pre-cleaning step is performed, the entire wafer is dip in a solution of hydrofluoric acid (HF) for a short time to remove the original oxide layer on the surface of the wafer. However, the original oxide layer is difficult to remove, so the uneven oxide layer remaining on the polycrystalline silicon will cause protrusions or spikes of tungsten silicide in subsequent processes. To alleviate this disadvantage, the present invention specifically deposits a layer of amorphous silicon after the pre-cleaning step. As shown in Fig. 4, a thin layer of amorphous silicon is formed on the polycrystalline chip by sputtering and has a thickness of about 100 to 300A. There are multiple benefits of using the sputtering method, including its ability to deposit many different types of metals or dielectrics, the ability to faithfully replicate the target's composition on the deposited film, and the importance of sputtering. A lower film deposition method. Next, WSix was synchronously in-situ deposited on the amorphous silicon. The target used was to cut a tungsten alloy plate and grow tungsten silicide with a thickness of about 800 to 1200A. Amorphous silicon and tungsten silicide are deposited by simultaneous sputtering, which can simplify the process of vacuum processing, because synchronous sputtering is to deposit amorphous silicon and tungsten silicide from the same machine, so no additional vacuum breaking is required. ) Step; In addition, since the wafer is not exposed to the air, the original oxide layer can be prevented from growing between amorphous silicon and tungsten silicide. After the lithography process, the gate structure defined by 'sequence etching of metal silicide, amorphous silicon layer, polycrystalline silicon layer, and gate oxide layer' is shown in Figure 5. Finally, it is subjected to high-temperature fading. 6 This paper size is applicable to China National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page) J___ i L ml f ^ m In— HI -VI mB ·,? ΤI.. -A ·-• n nn
五、發明説明（G) 經濟部中夬標率局員工消費合作社印製 火的步驟，一面使矽化鎢由多矽(silicon rich)轉化爲多 鎢(tungsten rich)的狀態；一面使非晶矽轉化爲複晶矽’ 以降低整個閛極的阻值，使場效電晶體的開關速度提昇； 其中褪火的溫度介於800°C到1000°C之間。 最後當源極/汲極之淡摻雜區15、間隙壁16和源極/汲極 之重摻雜區17完成後，一具有閘極、源極和汲極之電晶體 (圖六)於焉完成。 習用技術中矽化鎢在複晶矽層中形成的突起和尖峰，其 機制如前文所述，乃是因爲複晶矽層和矽化鎢間所存在之 不均勻的原始氧化層通常不容易被完全去除，因而造成種 種效應，此問題能夠在本發明中得到有效的改善，其原因 乃是因爲非晶矽不存在任何晶粒界面，因此非晶矽層在本 閘極結構中擔任了許多重要的角色：（1)矽原子從複晶砂擴 散至非晶矽的阻障層，（2)矽化鎢擴散至複晶矽的阻障層， (3)作爲一緩衝層供應後續氧化製程中所需之矽原子；最 後，沒有被作用完之非晶矽將在回火(annealing)後轉化爲 複晶矽，因此整個閘極的阻值將不被影響，而可以維持在 理想的範圍中。 綜而言之，本發明最大的特點在於加入一薄層的非晶矽 於複晶矽和矽化鎢之間，其優點如下所述：首先，非晶矽 層作爲擴散阻障層能阻止矽原子和矽化鎢的彼此擴散；其 次，非晶矽層也是提供後續氧化製程所需之矽原子的緩衝 層’因此矽原子將不再需要由複晶矽來提供；所以矽化鎢 的突起或尖峰可以被避免，電晶體的電性和良率也就大爲 7 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） —I L--I - - 1— . - - n - - I (請先閲讀背面之注意事項再填寫本頁) A 7 B _ 五、發明説明H ) 提高。此外，非晶矽和矽化鎢以同步濺鍍法沈積也簡化了 真空處理的步驟。 綜上所述，當知本發明已具備了進步性及新穎性，極具 產業上之利用價值，既凡依本發明之申請專利範圍所作之 均等變化與修飾皆爲本發明專利範圍所涵蓋，謹請貴審 查委員明鑑，並祈惠准，是所至禱。 (請先閱讀背面之注意事項再填寫本頁 裝丨 -I n T -'5 經濟部中央標隼局員工消費合作社印製 8V. Description of the invention (G) The steps of printing fire by the Consumer Cooperatives of the Bureau of Standards and Standards in the Ministry of Economic Affairs, while transforming tungsten silicide from silicon rich to tungsten rich; while making amorphous silicon Transformed into polycrystalline silicon 'to reduce the resistance of the entire cathode, so that the switching speed of the field effect transistor is increased; the temperature at which the flame is extinguished is between 800 ° C and 1000 ° C. Finally, after the lightly doped region 15 of the source / drain, the spacer 16 and the heavily doped region 17 of the source / drain are completed, a transistor having a gate, a source, and a drain (Figure 6) is焉 Done. The mechanism and protrusions of tungsten silicide in the polycrystalline silicon layer in conventional technology are as described above, because the uneven original oxide layer between the polycrystalline silicon layer and the tungsten silicide layer is usually not easily removed. Therefore, various effects are caused. This problem can be effectively improved in the present invention. The reason is that amorphous silicon does not have any grain interface, so the amorphous silicon layer plays many important roles in the gate structure. : (1) the diffusion of silicon atoms from the polycrystalline sand to the barrier layer of amorphous silicon, (2) the diffusion of tungsten silicide to the barrier layer of polycrystalline silicon, (3) as a buffer layer to supply the required in the subsequent oxidation process Silicon atoms; finally, the amorphous silicon that has not been used will be transformed into complex silicon after annealing, so the resistance of the entire gate will not be affected and can be maintained in the ideal range. To sum up, the biggest feature of the present invention is that a thin layer of amorphous silicon is added between the polycrystalline silicon and tungsten silicide. The advantages are as follows: First, the amorphous silicon layer can prevent silicon atoms as a diffusion barrier layer. Diffusion with tungsten silicide; Secondly, the amorphous silicon layer is also a buffer layer that provides the silicon atoms needed for subsequent oxidation processes. Therefore, the silicon atoms will no longer need to be provided by polycrystalline silicon; so the protrusions or spikes of tungsten silicide can be To avoid, the electrical property and yield of the transistor will be as large as 7. This paper size applies to the Chinese national standard (CNS > A4 specification (210X297 mm) —I L--I--1—.--N--I ( Please read the notes on the back before filling out this page) A 7 B _ 5. Description of the invention H) Improve. In addition, the simultaneous deposition of amorphous silicon and tungsten silicide also simplifies the vacuum process. In summary, when it is known that the present invention has the progressiveness and novelty, and has great industrial use value, all equal changes and modifications made in accordance with the scope of the patent application of the invention are covered by the scope of the invention patent. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. (Please read the precautions on the back before filling out this page. 丨 -I n T -'5 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 8
本紙張尺度適[用中國國家標準（CNS ) A4規格（210x 29T^i~TThe size of this paper is suitable for the use of Chinese National Standard (CNS) A4 (210x 29T ^ i ~ T