TW395094B - Fully digitized clock holdover method and device - Google Patents

Abstract

A fully digitized clock holdover method and device are disclosed, which use the method of fully digitization for producing the required output clock without analogue-to-digital and digital-to-analogue conversion, and also without the requirement of expensive voltage control oscillator. The information of frequency adjustment is recorded on time so that the recorded information can replace the output of phase-locked loop when losing the input reference clock. Since all the signals in the fully digitized phase-locked loop are digital signals, it can easily transmit such information using digital logic or microprocessor. A long time stable clock is also provided to conform to the international standard.

Description

3037twf / 005 A7 B7 V. Description of the invention (ί)-The present invention relates to a frequency generating device and method, and in particular to a fully digital clock retaining function with a clock retaining function applied to a phase locked loop. Method and device. Phase Locked Loop (PLL) is an electronic circuit used to lock the frequency and phase of the input clock. In other words, the phase-locked loop must generate another frequency and phase that are related to the reference clock of the input signal. Reference to the clock-synchronized output signal; therefore, we can also consider the phase-locked loop as a demodulator to demodulate the carrier frequency to track the frequency and phase changes of the input clock. That is, the conventional PLL circuit is used to receive a reference input signal and complete a feedback control operation to lock the phase of the output signal and the reference input signal. Most importantly, the PLL circuit will continuously test the output signal through a feedback loop. When the output signal is in phase with the input signal, the PLL circuit will drive the output signal to change and synchronize with the input signal. PLL circuits are widely used in many fields, such as communication systems, computers, and television engineering. Generally speaking, according to the production method of the phase-locked loop, it can be divided into two categories: analog, analog, digital, and all digital. As shown in Figure 1, it is a traditional analog PLL circuit. The PLL circuit includes a Phase Detector (PD) 10, a low-pass filter 12, and a Voltage Control Oscillator (VCO) 14. In addition to the basic three components, it also includes A divide-by-N divider for feedback operation (/ N Frequency) This paper size is applicable to China National Standard (CNS) Α4 size (210X297 mm). Please read it before you order it. Cooperative Press 11 3037twf / 005 A7 B7 V. Description of Invention (>)

Divider) 16 The phase difference detector 10 detects the phase difference between the input reference signal and the signal UN fed back from the output signal of the voltage controlled oscillator 14, and outputs a signal proportional to the phase difference to the low-pass filter 12. The low-pass filter 12 will be used to remove the voltage from the AC section and provide a DC voltage to drive the voltage-controlled oscillator 14. This DC voltage will be used to change the frequency of the output signal of the voltage-controlled oscillator 14. Through this continuous feedback control operation, the low-pass filter 12 and the phase difference detector 10 will minimize the output error of the voltage-controlled oscillator η. In this way, in theory, the entire loop will reduce the frequency error to zero . Once the phase difference detector 10 knows that the frequencies of the two input signals are equal, the output frequency of the voltage-controlled oscillator locks the frequency of the reference clock, and the phase difference between the two signals is also controlled. In addition, please refer to Fig. 2, which shows a conventional digital Pll circuit. The digital PLL circuit replaces the voltage controlled oscillator (VC0) with a digitally controlled oscillator (Digital Control Oscillator, DCO). This DC0 circuit is used to generate digital control signals and can be synchronized with the input reference signal. The advantage of using this digital PLL circuit is that it can avoid the use of expensive voltage controlled oscillator circuits (VCO) and has high reliability. However, when the input reference input signal is stopped or interrupted, the conventional PLL circuit that is being used to read the incoming signal stream synchronously will cause problems. When the input reference input signal is missing, the output frequency of this VCO or DC0 will drift (Drift), resulting in the receiver used to receive information from the transmitted data stream cannot receive synchronously, and a data error will occur. Therefore, in order to solve this problem, a paper size that can be produced when the input reference signal is interrupted is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) (please read the note on the back before filling this page) II Ί = I 、 tT1-] JII-! II— I ^) I— m Printed by the Shell Consumer Cooperative of the Central Slope Bureau of the Ministry of Economic Affairs • Hi in 3037twf / 005 A7 B7 5. Description of the Invention (Today) " ~~ ~ The problematic PLL circuit technology has been continuously developed. One of the techniques to solve this problem is to provide an in-phase local clock signal when the input reference signal disappears or is interrupted. In U.S. Patent No. 4,972,422 issued by Steierman, approved on November 20, 1990, a PLL circuit using multiple input reference signals is disclosed. This conventional circuit can detect the input reference signal and switch directly to other reference signals when the signal is broken. This technique cannot be applied to communication systems, because communication systems generally have only a single reference signal. Another conventional technique is to increase the use of a crystal in a PLL circuit with a voltage-controlled oscillator and keep it at a certain temperature to provide a phase-locked timing signal (PhaSe_locked clock signal with the lowest possible drift). ). The disadvantage of this conventional technique is that it takes considerable energy to maintain the spar at a certain temperature. Another conventional technique is a PLL circuit with a Holdover mode. Please refer to FIG. 3, which shows a conventional PLL circuit with a retention mode 00, which uses two PLL circuit units: PLL I and PLL II. The meaning of so-called retention in communication systems is to hope that when all the input reference clocks of the system lose function, the circuit can use the information calculated or counted during normal operation of the system to continue to provide stability. The system clock to maintain the normal function of the system 'in many systems' uses a phase-locked loop to provide the clock required by the system. Therefore, the circuit design with a reserve mode is also closely related to the design of the phase locked loop. This paper size applies Chinese National Standard (CNS) A4 scale (210X297 mm) (please read the notes on the back before filling out this page) Printed by the shelling consumer cooperation of the Central Ramp Bureau of the Ministry of Economic Affairs ----- -1T ------ line --------- Γ --- r____ 3037twf / 005 A7 B7 Printed by the Shell Consumer Cooperative of the Central Ladder Bureau of the Ministry of Economic Affairs 5. Description of the invention (f) As shown in the figure, in addition to a set of PLLI circuits used in general PLL circuits, including a phase difference detector 310, a loop filter 320, a voltage controlled crystal oscillator (VCxO) 330, and analog components other than the N divider 340 , And add another set of PLL 11 circuits that operate in the leave mode, including a phase difference detector 310 ′, a loop filter 320 ′, a voltage controlled crystal oscillator (VCxO) 33〇 | and a divide-by-N divider 34 (T and other analog components, in addition, a digital-to-Analog (D / A) converter 360, an analog-to-digital (A / D) converter , A LOS indicator 390, and a microcontroller 380. This circuit with a reserved mode often deals with analog-to-digital (A / D) or digital-to-analog (D / A) ) Conversions between signals. However, these conversions must not only cost considerable cost, but also result in errors in the output clock frequency due to quantization errors between analog to digital signal conversions. At the same time, in order to reduce such errors High-resolution analog-to-digital or digital-to-analog conversion elements are often required. At the same time, in order to ensure clock stability, expensive voltage-controlled crystal oscillators must often be selected, which increases manufacturing costs. Therefore, the present invention The purpose is to provide a phase-locked loop device, which can keep outputting a locked signal even when the input reference clock signal disappears or is interrupted. The object of the present invention is to provide a fully digital phase-locked loop device, Abandoning the analog-to-digital or digital-to-analog conversion elements required by the conventional practice greatly reduces the production cost. Another object of the present invention is to provide an all-digital phase-locked loop

Jl 'tn —J— alt ——. ^ 1 ___. «I ^ n I (Please read the precautions on the back before filling out this page) This paper is applicable to the China National Standard (CNS) A4 (2 丨〇x297 公 楚) 3〇37twf / 〇〇5 μ------ Β7 ____ * V. Description of the invention (ς) — 'Ί (device, replace expensive voltage controlled oscillator with digitally controlled oscillator,

High output frequency stability and accuracy. .J In order to achieve the above and other objectives, the present invention provides a phase-locked loop device for generating a synchronous output signal. The device includes a main phase-locked loop (Phase-locked loop, PLL) circuit. To receive an input reference signal, | {output a loop signal, detect an I f phase difference between the input reference signal and one of the loop signals, generate a first control signal based on the phase difference, and according to the g [first The control signal adjusts the phase of the loop signal; and a microcontroller, 3 j I fills ^ to calculate an average number of phase fk bit adjustments performed by the main phase-locked loop circuit within a given time, And according to the average number, a first | second control signal is generated, wherein the second control signal is used to generate the synchronous output signal when the phase-locked loop device is placed in a retention mode. j In order to achieve the above and other objectives, the above-mentioned phase-locked subscription provided by the present invention

Circuit device, wherein the main phase-locked loop includes an oscillator for receiving an I-area clock signal, one of the first control signal and one of the second control signal |, and generating the loop through phase adjustment Signal as the synchronous output | output signal; a phase detector to receive the loop signal and the input production test signal, and detect a phase difference between the loop signal and the input reference signal 'ί Central Ministry of Economics rate Printed by ΛBayong Consumer Cooperatives *.

And outputting an error signal based on the detected phase difference; and a digital I-loop filter for receiving the error signal from the phase detector and inputting J.

The first control signal is output. J In order to achieve the above and other objectives, the above-mentioned phase-locked loopback circuit device provided by the present invention, wherein the main phase-locked loop includes a first oscillator for receiving a regional clock signal and the first control. Signal, and in accordance with the first control '1 paper size, the Chinese National Kneading Car (CNS) A4 size (2! 0 × 297 mm) 3037twf / 〇〇5 A7 B7 Μ printed by the Central Samples Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (&); the generated signal generates a phase-adjusted loop signal; a phase detector is used to receive the loop signal and the input reference signal, and detect a phase between the loop signal and the input reference signal Difference 'and output an error signal according to the phase difference; and a digital loop filter' for receiving the error signal output from the phase detector, generating the first control signal based on the error signal, and outputting the first control signal The first control signal, and wherein the phase-locked loop device further includes: a second oscillator for receiving the regional clock signal and the second control signal, and generating the same according to the second control signal. output signal. In order to achieve the above and other objectives, the present invention provides a method for synchronizing output signals, including 'first' generating a phase-adjusted loop signal according to a first control signal; and then, within a predetermined time, calculating the The average number of phase adjustments made by the control signals; secondly, a second control signal is generated based on the result of the calculation step; and a synchronous output signal is generated through synchronization in a retention mode according to the second control signal. The above calculation step further includes' calculating the average number of phase adjustments made by the first control signal within a predetermined time zone to generate an accumulation 累 for each of the predetermined time zones; secondly, in a normal operation mode Next, a predetermined number of the accumulated 値 is stored; and the predetermined number of the accumulated 値 is averaged. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings' as follows: Brief description of the drawings: Standards Standards (CNS) A4 (210X297 mm)

«The Ministry of Economic Affairs, China's Standards Rate, Employee Consumer Cooperative Print A7, B7, Five 'Invention Description (7) ^^' Figure 1 shows a traditional analog PLL circuit; Figure 2 shows a traditional digital PLL Circuit; Figure 3 shows another traditional analog PLL circuit; and Figures 4A-4C are clock operation diagrams of the reference input signal L and feedback signal Un; Figure 5 is a digital diagram An embodiment for controlling an oscillator; FIG. 6 is a diagram showing an operation example of a BO signal and a CA signal; FIG. 7 is an ADPLL device showing one of the preferred embodiments of the fully digital clock retention device according to the present invention; FIG. 8 shows an FIFO buffer embodiment of the all-digital clock retention device in FIG. 7; FIG. 9 shows the all-digital clock retention device according to another embodiment of the present invention; and FIG. Figure 0 is a flowchart illustrating the operation of the full-digital clock retention method according to one of the preferred embodiments of the present invention. Description of the symbols in the drawings: Phase difference detector 10 Voltage controlled oscillator 14 Phase difference detector 310, Voltage controlled crystal oscillator 330 Phase difference detector 310 'Voltage controlled crystal oscillator 330 Digital to analog converter 360 micro Controller 380 3037twf / 005; | '! 1 J · ΙΓ-I-...... I ^ II (please read the precautions on the back before filling this page) Order low-pass filter 12 Divide by N 16 loop filter 320 divides N divider 340 loop filter 320 'divides N divider 340' analog to digital converter 370 LOS indicator 390 this paper from the application according to the national standard rate (CNS) from the secret ( 2ωχ297) (3037twf / 005 A7 B7) Printed by the Ministry of Finance and Economics of the Central Government and the Zhuhai Bureau of Beihai Consumer Cooperatives 5. Description of the invention (again) Delay line 524 Multiplexer 522 Phase difference detector Π6 Digitally controlled oscillator H2a Accumulator 142 Averager 146 Preferred embodiment The method and device for all-digital clock retention in the present invention. The device and method for retention mode are particularly applied to A1 digital phase-locked loop (hereinafter referred to as ADPLL). The ADPLL previously described in FIG. 2 includes four components: a digitally controlled oscillator (DCO) 24, a digital loop filter 22, a phase difference detector (PD) 20, and a divide-by-N counter 26. This phase difference detector 20 is used to receive two input signals fin and fout / N, which respectively represent the input reference signal and the output signal of DC0 24 feedback, and compare fin and UN to detect any term bit difference. After detection, the phase difference detector 20 outputs two signals UP and DN, which represent the phase difference between 1 and f ^ / N, respectively. As shown in FIG. 4A, when the positive rising edges of the two signals fin and UN occur simultaneously, the phase difference between the two signals is zero, so a zero-potential output is generated from the phase difference detector 20. As shown in FIG. 4b, when the positive rising edge of the input reference signal fin is ahead of the positive rising edge of the feedback signal tu / N, the phases of the two signals are different. Therefore, the phase difference detection device 20 will A UP pulse signal is generated, indicating a positive phase error. And as shown in Figure 4c, when the input up / down counter 526 digital loop filter 114 divides the N counter 118 priority input priority output 144 switch H8

Ju r— ΙΊ ff II s III ^ II w (Please read the precautions on the back before filling in this tile) Order 10 This paper size applies to the Central Solid State Standards (CNS) from the specifications (210X297 mm) Zhongji Ministry Central橾 Rate Bureau Shellfish Consumer Cooperative " installed 3037twf / 0O5 A 7 ------ B7_____ V. Description of the invention (?) The positive rising edge of the reference signal fin is behind the positive rising edge of the feedback signal f ^ / N At this time, the phases of the two signals are different. Therefore, the phase difference detection device 20 will generate a DN pulse signal, which indicates that it has a negative phase error. The signals UP and DN output from the phase difference detection device 20 will be transmitted to the digital filter 22 and operated together with DC024 to adjust the output of the ADPLL circuit. When the pulse width of the UP signal output from the phase difference detection device 20 is greater than the pulse width of the DN signal, the output frequency of this loop will increase (ie, accelerate), and when the pulse width of the UP signal is smaller than the pulse of the DN signal With wave width, the output frequency will decrease (ie, decelerate). The digital filter 22 includes, for example, a K-counter 'may be an up-down counter, or it may have both an up counter and a down counter, which function as the same digital low-pass filter. The UP signal triggers the up counter count, and the DN signal triggers the down counter count. When the up counter overflows, the K-counter will generate a carry (Carry, CA) output signal, and when the down counter overflows, the κ_counter will generate a borrow (Borrow, B0) output signal. The two signals CA and B0 will be transmitted to the DCO 24. The "borrowing" signal will cause the DCO 24 to select a phase-leading clock as the output, so that the output phase of the loop will lead to achieve the purpose of increasing the frequency. " The signal will make DC0 24 choose a clock with a backward phase as the output, so that the output phase of the loop is delayed to achieve the purpose of reducing the frequency. The DCO 24 is used to receive the CA and BO signals from the digital filter 22, It is also used to receive a regional clock signal fc. This DC0 24-pack paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). (Please read the notes on the ^ side before filling out this page) * 1T * Line • H— 3037twf / 005 Printed by the Ministry of Economic Affairs of the Central Bureau of Standards and Consumer Affairs Co., Ltd. Printed A7 B7 V. Description of the Invention (π) ~ Including the three main components' For example, as shown in Figure 5, a delay line 524 , Which has L delay stages; UP / DN counter 526 and a multiplexer 522. This delay line 524 is used to receive regional clock signals fc and, such as In the example in Figure 5, there are 16 extensions Delay stages DW D6 (that is, L is equal to 16), and all of them generate sixteen phase difference clock signals C | ~ CI6. Sixteen phase difference clock signal hearts ~ (: 16 then It is sent to the multiplexer 522. Such a sequence of phase difference clock signals allows the DCO 24 to perform a phase frequency modulation operation, and it can compensate for phase errors detected by the phase difference detector 20. As shown in Figure 6, in the "B0" (borrowing) clock of the B0 signal, DC0 24 will select the phase difference clock signal (^ ~ 0: 16 to delay the output signal f. ^ Of this loop). On the other hand, the "CA" (carry) pulse in the CA signal will cause DC0 24 to select an area clock signal from the phase difference clock signal to lead the circuit to output the signal. Here is a specific example in Fig. 6 In the process, a BO pulse initially instructs the multiplexer 522 to select a phase-lagging signal Ci + 1 to slow down the output signal. When a subsequent phase error is detected, it is detected as positive In the forward direction, a CA pulse will instruct the multiplexer 522 to select the phase leading signal q so as to output the signal f. Fast. In this method, each time the B0 signal will force the multiplexer to select a regional clock with a backward phase, the output of this loop will be delayed by 1 / L cycles. A similar method 'Every time the CA signal will force The multiplexer selects a regional clock with a leading phase 'The output of this loop will lead 1 / L cycles. Therefore,' For example, the paper size in Figure 6 is based on the China National Standard (CNS) Α4 specification (21 〇 χ 297 mm) 1, " Order μ, ------------; ___-· (Please read the notes on the back before filling this page) · · • — ^ 1 · 11 3037twf / 005 The central government of the Ministry of Economic Affairs is the I-industrial consumer cooperation Du Yin. A7 B7 V. The 16 delay steps shown in the invention, the 16 phase hopping times in the phase leading direction will cause this time The loop output is 1Hz ahead. Similarly, 16 phase hopping times in the phase backward direction will cause this loop output to be 1Hz behind. The DCO 24 up / down counter 526 shown in FIG. 5 receives the CA and B0 signals from the digital loop filter 22 and outputs an address signal to the multiplexer 522, thereby delaying the line 524. Choose a corresponding phase difference clock signal from the phase difference clock signal. FIG. 7 shows an ADPLL device 100, which is one of the preferred embodiments of the all-digital clock retention device according to the present invention, for maintaining an in-phase output regardless of the input reference signal fin cancellation. Display or interrupt. The ADPLL device 100 includes a main ADPLL circuit 110. The main components of the ADPLL device 100 are as shown in FIG. 7. Furthermore, the ADPLL device 100 further includes an output signal for maintaining phase stability when the input reference signal is displayed or interrupted. element. Therefore, the device can operate normally under normal conditions or in Holdover mode. The main ADPLL circuit 110 that can generate a phase-adjusted loop output signal tut includes a phase difference detector (PD) 116, a digital loop filter (LF) 114, a digitally controlled oscillator (DCO) U2a, and a division N counter 118. This connection and operation on the structure of the ADPLL circuit 110 has been clearly illustrated in FIG. 2, so it will not be repeated here. The signal Lut output by the digitally controlled oscillator 112a in the main ADPLL circuit 110 is not used as the system clock, but instead is used only as a source for providing the phase difference detector 116-the feedback signal. In this embodiment, as shown in FIG. 7, another DCO is in a normal operation mode or a DCO.

Winter paper ruler and universal gauze net_Home standard (CNS > A4 size (210X297mm) Printed by Zhengong Consumer Cooperative, Central Standard Bureau of the Ministry of Economic Affairs 3037twf / 005 μ ___________B7_ V. Description of the invention (/ >) Retention mode Generate system signals. In order to provide an output signal in phase when in the normal operation mode or the reserved mode, the ADPLL device 100 in FIG. 7 includes three components in addition to the main ADPLL circuit described above. lOS (Loss of signal) indicator 120, a microcontroller 140 and a digitally controlled oscillator (DC0) 112b. The LOS indicator 120 is used to receive an input reference signal fin and output a LOS signal to the microcontroller 140 , Used to indicate that the input reference signal fin has been interrupted. The microcontroller 140 is used to receive the control signals CA and BO transmitted by the digital loop filter U4, in addition to the L0S indicator L0S signal output from 120. This microcontroller 140 outputs control signals CA 'and BO1, which can be used to control the phase frequency hopping operation of digitally controlled oscillator 112b. This DCO 112b is used to receive the control output from microcontroller 140 The signals CA 'and B0' receive the same regional clock signal fc as the DCO 112a and output a synchronized system output signal. The operation principle of the ADPLL device illustrated in FIG. 7 will be described below. By receiving the input reference signal fin, the L0S indicator 120 can determine when the input of the reference signal f, n is interrupted, and then start the operation in the retention mode. In either the normal operation mode or the retention mode, the microcontroller 140 is Control signals CA 'and BCV will be generated, just like the control signals CA and B0 received by the DCO U2a as described above, and used to control the phase-hopping operation generated by another DCO 1b In order to choose whether to delay the phase difference clock signal or lead the phase difference clock signal, depending on the signal tut to be output at this end, whether to extend the paper size is applicable to the Chinese National Standard (CNS) M. (210x297 mm) ) (Please read the notes on the back before filling this page) • (m --_ k ------ IT ------______ I .____: ___ ^ ___ 3037twf / 005 Insignia A7 B7, Co-operative Consumer Cooperative (M) Late or leading. A composition for the preferred embodiment of the microcontroller 140 may include four components as shown in FIG. 8: an accumulator 142, a priority input priority output (First-iii first -out (hereinafter abbreviated as FIFO) buffer 144 '— an average calculator (Average calculator) 146 and a switcher 148. In the normal operation mode of the ADPLL device 100, the accumulator 142 is used to receive the frequency hopping times controlled by the control signals CA and B0 within a predetermined time (for example, 0.1 second). Each accumulated chirp is output by the accumulator M2. 'And the FIFO buffer 144 is used to receive the accumulation chirp output by the accumulator 142 via the switcher 148. The L0S signal output by the L0S indicator 120 can keep the switcher 148 closed in the normal operation mode, so that the accumulated 値 can be continuously moved into the FIFO buffer 144. On the other hand, the L0S signal can also cause the switcher 148 to turn on in the retention mode, and stop the accumulated 値 from being moved to the FIFO buffer 144. The FIFO buffer 144 can store a certain amount of accumulation 値 from the accumulator 142. As shown in the example of FIG. 8, the FIFO buffer 144 has 10 stages, so it can be used to store the accumulator 142. There were 10 puppets. This accumulation 储存 stored in the FIFO buffer 144 thus represents the number of phase frequency hops performed in the complete one second by the DCO 112a. Of course, the FIFO buffer 144 can store more or less accumulated 値 by adjusting the order. This end can be adjusted as needed, for example, it can be adjusted to 100 steps to store in a longer time or a shorter time ( (Eg 10 seconds). This FIFO buffer 144 outputs the stored accumulated volume to the averager 146. This averager 146 is used to receive a plurality of FIFO buffers 144. This paper is suitable for Chinese home elevator standards (CNS》 A4 ^ _ (training x297iiJ_ by)

The central government of the Ministry of Economic Affairs of the Ministry of Justice of the People's Republic of China, Du Yin, «3037twf / 005. ^ A7 j____ ______B7 _ V. Description of the invention (//) The cumulative 値 from 値 and calculate the average 値. This average signal is used to generate the control signals CA 'and BO', which is the calculation output by the microcontroller 140 to control the direction (such as the phase delay direction or phase leading direction) and another DCO 112b frequency hopping operation ( That is, the number of frequency hopping times in a certain period of time). Two chirps can be generated in the averager 146: x and d, where X represents the average number of frequency hopping times in a given time (e.g., 0.1 second), and d represents the direction of phase hopping. For example, when d = 0, this DCO 112b will increase the output signal f. ^ Output frequency X times in each 0.1 second interval. On the other hand, when d = 1, the DCO 112b will reduce the output signal. The output frequency will be X times in every 0.1 second interval. As shown in Fig. 8, the control signals CA 'and B0 · can be obtained from (d, x) and outputted from the microcontroller 140 to the DCO 112b. During the normal operation mode in the embodiment illustrated in FIG. 7, the control signals CA 'and BO' generated by the microcontroller 140 are based on the average number of frequency hopping times 値 guided by the control signals CA and BO. In the following, a description will be given with regard to the remaining mode operation of the embodiment of the ADPLL device 100 in FIG. 7 and FIG. 8. When the LOS indicator 120 senses the disappearance of the input reference signal fin, an operation in a leave mode will be started, and the FIFO buffer 144 will stop receiving the additional accumulating frame from the accumulator 142. The chirp stored in the FIFO buffer 144 at this moment, and the mean chirp calculated by the averager 146, will be used as the basis for generating the control signals CA 'and B0' during the entire retention mode, and then output. output signal.. Therefore, it can be seen that during the retention mode, the control signals CA ′ and B0 ′ output by the microcontroller H0 are based on the input of the reference letter 16 Ϊ The paper standard applies the Chinese National Standard (CNS) Eighty Four Secrets (2ωχ297).

3037twf / 005 Central Standards Bureau of the Ministry of Economic Affairs Ml: Industrial and consumer cooperation Du Yinli A7 B7 V. Description of the invention (the time when the / 0 fin disappears is stored in the FIFO buffer 144. Because the LOS indicator 120 took less than The disappearance of the input reference signal fin can be detected in 0.1 seconds. Therefore, the 値 in the input FIFO buffer 144 will be very useful, and the 値 can be accumulated in a short accumulation time to ensure the output of the DCO 112b. The quality of the signal. When the L0S indicator 120 detects the occurrence of the input reference signal fin, the accumulator 142 will reset and accumulate the number of phase frequency modulations represented by the control signals CA and B0 again. ≫ As shown in the figure, like DCO U2a, this DC0 112b can also include a delay line 524 to receive the regional clock signal fc and generate a certain number of phase difference clock signals C, ~ C16. Please refer to section FIG. 9 illustrates another embodiment of the present invention for maintaining an in-phase output 'regardless of whether the input reference signal fin is dismissed or interrupted. In this embodiment, Main PLL circuit 110 (packet A phase difference detector 116 '-a digital loop filter 114', a digitally controlled oscillator 112 and a divide-by-N counter 118) and the L0S indicator 120 are the same as above, so similar operations will not be repeated here. In the embodiment shown in FIG. 9, the difference is DC0 120 and a multiplexer 150 for the control signals CA · and B0 · output by the microcontroller 140. This multiplexer 150 is located in the digital position. The loop filter 114 and the digital control oscillator 112 are used to receive the control signals CA and B0 output from the digital loop filter 114. This multiplexer 15 is further located between the microcontroller 140 and the DCO Π2, and In order to receive another control signal CA 'and B0' output by the controller 140. This multiplexer 15 is further connected ----- ^ ----- / k-- (Please read the note on the back first $ Entry on this page), π This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm) m · ϋ 3037twf / 005 The Ministry of Economic Affairs of the Bureau of Loss of Bid Rates belongs to Industrial and Consumer Cooperatives. 2. Description of the invention (〆) ~ Receives the switching signal SW from the controller 140, which is used to instruct the multiplexer 150 The control signals CA and BO in the normal operation mode or the control signals CA1 and BO 'in the retention mode are shown. The operation of another embodiment in FIG. 9 is described below. When the LOS senses the input reference When the signal fin disappears or is interrupted, the ADPLL device 100 will operate in the retention mode. When operating in the retention mode, the FIFO buffer 144 in the controller 140 will stop receiving the accumulation from the accumulator 142. The switcher 148 will also open. At this moment, the average 値 calculated by the averager 146 will be applied to the operation of the entire retention mode. When the retention mode is activated, the controller 140 outputs a signal SW to the multiplexer 150 to instruct the multiplexer 150 to output the control signals CA · and B0 'in the retention mode. As a result, the DCO 112 will perform a frequency hopping operation under the control of the control signals CA · and B0 '. When the LOS indicator 120 detects the occurrence of the input reference signal fin again, the accumulator 142 will reset and accumulate the number of phase frequency modulations represented by the control signals CA and B0 again, and the microprocessor 140 will simultaneously request more The worker 150 outputs the control signals CA and BO in the normal operation mode. Therefore, in this embodiment, the output of the DCO 112 will be used as the system clock output, and is controlled based on the control signals CA and B0 in the normal operation mode, and in the remaining mode by the control signal CA 'and BCT to control. Please refer to FIG. 0, which illustrates a method according to the present invention for calculating the control signals CA 'and B0'. In particular, as shown in step S202, the accumulator 142 and the reset mode are immediately reset immediately after the retention mode. Following step S204, the accumulator 142 accumulates 1-1 under the control of the control signals CA and B0 1- 1 ^ ----- vk ------ order ------ Γ ------__ I______ ( Please read the notes on the back before filling in this page) This paper is suitable for Chinese households (CNS) A4 inspection (2 丨 GX297 public «) 3037twf / 005 A7 B7 V. Description of the invention (,)) ~~~ The number of frequency hops generated at a given time (for example, 0.1 seconds). Then, in step S206, it is determined whether the LOS indicator 120 indicates that the input reference signal fin disappears. If it is " No, " the accumulation frame generated by the accumulator 142 will be transferred to the FIFO buffer 144 in step S208. On the one hand, if it is "YES", it will return to step S204 as described above. After step S208, the calculation of the new average 値 used in the retention mode is started. The entire ADPLL device including the remaining mode elements in Figs. 7-9 correctly generates a synchronized output signal even when the input reference signal fin disappears. For example, according to the embodiment shown in FIG. 7, when the accumulated sampling time is 0 ″ seconds, the average output generated by the FIFO buffer 144 includes a frequency hopping frequency of one second (that is, an accumulation section of 0.1 second). Time multiplied by 10 FIFO steps). This average error will be between plus / minus 1/16 clock signal errors per second. If the output clock frequency is 50MHz, the correctness of the clock will be 1 / 16x1 / 50 = 1.25xl0 · 3 ppm. In addition to the correctness in the retention mode, this fully-digitized clock retention device according to the present invention The embodiment of the ADPLL device can complete the embodiment shown in Figures 7-9 at a lower level of circuit complexity. Using a single ADPLL circuit does not require analog components, AD / DA converters, or expensive Voltage-controlled oscillation circuit (VC0). In addition, this circuit can be completed using a simple Digital Cell Library (FPGA) or Field Programmable Gate Array (FPGA). Although the present invention uses a specific main ADPLL circuit with a digital loop filter that can generate the control signals CA and BO, it is clear that the cooked paper New Zealand 14 wealth «home scale (c called A4 ^ (2 丨 Gx297) (Chu) (Please read the note ^^ on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives C --------. Lamp ------ line, ----- .: ------------ 3037twf / 005 A7 B7 V. Description of the Invention (f8) Those skilled in the art can expand the scope of the present invention. For example, by using insert or The ADPLL circuit that deletes the pulse wave, instead of the CA and BO control signals used in this embodiment, is also used to adjust the frequency output by the DCO. Using the above-mentioned concept to such a circuit, the insertion / deletion of the pulse wave can be accumulated by The accumulator can accumulate in a given time, and the accumulated chirp can also be used in functions similar to the other control signals CA 'and B0' described in this embodiment. Similarly, by using a programmable frequency divider (Programmable Frequency Divider) ADPLL circuit, instead of the CA and B0 control signals used in this embodiment, is also used to adjust the DCO The output frequency. Using the circuit described above, when the DCO output frequency must increase, a smaller frequency divisor will be used. On the other hand, when the DCO output frequency must decrease At this time, a larger frequency divisor will be used. Therefore, with such an ADPLL circuit, the accumulator of the present invention can record the number of times of use of the larger / smaller divisor within a predetermined time, and use In this way, the control signals CA and B0 are generated by counting. The above description is only a preferred embodiment of the present invention, but it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. In addition, various modifications and retouching can be made, so the protection of the present invention! G is subject to the definition of the scope of the attached patent application, please apply for equal changes and modifications in the scope of the patent, which should belong to the invention patent The scope of coverage. This paper size is applicable to China Standard (CNS) Α4 size (2 丨 0X297 mm) (Please read the precautions on the back before filling this page) '袈 ·

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Claims (1)

3037twf / 〇〇5 A8 BS C8 D8 Central Standards Bureau of the Ministry of Economic Affairs, 工 Industrial Cooperative, India Ben Ben VI. Patent application scope 1. A fully digital clock retention device for generating a synchronous output signal, the device includes a master Phase-locked loop (PLL) circuit for receiving an input reference signal and outputting a loop signal, detecting a phase difference between the input reference signal and the loop signal, and generating a first control based on the phase difference Signal and adjust the phase of the loop signal according to the first control signal; and a microcontroller 'is used to calculate an average number of one of the number of phase adjustments performed by the main phase-locked loop circuit within a predetermined time, and according to The average number generates a second control signal, wherein the second control signal is used for the synchronous output signal generated by the full-digitized clock retention device in a retention mode. 2. The device according to item 1 of the scope of patent application, wherein the main phase-locked loop comprises: an oscillator for receiving an area clock signal, one of the first control signal and one of the second control signal And generate the loop signal through phase adjustment as the synchronous output signal; a phase detector for receiving the loop signal and the input reference signal, detecting a phase difference between the loop signal and the input reference signal 'and Outputting an error signal based on the detected phase difference; and a digital loop filter for receiving the error signal from the phase detector and outputting the first control signal. 3. The device described in item 1 of the scope of the patent application, wherein the main phase-locked loop circuit includes: (Please read the precautions on the back before filling out this page) The size of the paper is applicable to China National Standards (CNS) A4 specifications (210X297 mm) 3037twf / 〇〇5 A8 B8 C8 D8 Printed by the Central Gradient Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives 6. Application for a patent scope a first oscillator to receive a regional clock signal and the first A control signal 'and generate a phase-adjusted loop signal according to the first control signal; a phase detector for receiving the loop signal and the input reference signal, and detecting a phase between the loop signal and the input reference signal And output an error signal according to the phase difference; and a digital loop filter for receiving the error signal output from the Berbit detector, and generating the first control signal based on the error signal, and The first control signal is output, and the all-digital clock retention device further includes: a second oscillator for receiving the regional clock signal and the second control signal And generate the synchronous output signal according to the second control signal. 4. The device according to item 3 of the scope of patent application, wherein the second oscillator generates the synchronous output signal in one of a normal operation mode and the retained mode. 5. The device according to item 1 of the scope of patent application, further comprising: an indicator for detecting when the input reference signal is interrupted, and outputting a consistent energy signal to the microcontroller, which can instruct the microcontroller The controller switches from a normal operation mode to the leave mode. 6. The device according to item 1 of the scope of patent application, wherein the controller includes: an accumulator for calculating an average number of phase adjustments performed by the main phase-locked loop circuit within a predetermined time, And according to the average number, a cumulative 値 corresponding to each of the given times is generated, and the n ΙΓΙ II nnnn 1 n I-, 11 i (please read the precautions on the back before filling this page) This paper is not used Zhongguo Country Fengfeng (CNS > A4 Specification (210 > &297; 297mm) 3037twf / 005 The Ministry of Economic Affairs of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China, including the official seal of the Social Security Bureau. 6. The patent application scope accumulates accumulators; a memory device for reading the accumulative accumulators from the accumulator in a normal operation mode, and storing one The cumulative sum of the series; and an average # §F, which is used to calculate the cumulative sum of the series stored in the memory device. 7. The device according to item 6 of the scope of patent application, wherein the memory device is a first-in first-out (FIFO) buffer. 8. The device described in item 1 of the scope of patent application, wherein the all-digital clock retention device is an all-digital phase-locked loop device. 9. The device according to item 1 of the patent application scope, wherein the oscillator is a digitally controlled oscillator. 10 The device according to item 3 of the scope of patent application, wherein the first oscillator and the second oscillator are both digitally controlled oscillators. 11. The device according to item 8 of the scope of patent application, wherein the all-digital phase-locked loop device is completed by a field-programmable gate array (FPGA). 12. · A method for all-digital clock retention, including the following steps: generating a phase-adjusted loop signal according to a first control signal; calculating the average of the phase adjustment made by the first control signal within a predetermined time The number; based on the result of the calculation step, a second control signal is generated; and a second mode is generated based on the second control signal in a retention mode (please read the note on the back before filling this page) The size of the paper used for this edition is China National Standard (CNS) A4 (210X297 mm) 3037twf / 005 A8 B8 C8 D8 Printed by the Ministry of Economic Affairs * Standard Rate Consumer Cooperatives 6. This synchronous output signal follows the scope of patent application. 13. The method according to item 12 of the scope of patent application, wherein the calculating step further comprises: within a predetermined time zone, calculating an average number of phase adjustments made by the first control signal to generate each of the predetermined An accumulation frame in a time zone; in a normal operation mode, storing a predetermined number of accumulation frames; and 'averaging the predetermined number of accumulation frames. 14. The method according to item 13 of the scope of patent application, wherein the storing step has moved the accumulations to a first-in first-out (FIFO) buffer. 15. The method according to item 14 of the scope of patent application, further comprising: detecting when the input reference signal is interrupted to enable the retention mode; and stopping moving the accumulation to a priority input priority output ( First-in first-out (FIFO) steps. 16. The method as described in item 12 of the scope of patent application, wherein generating the fully digital clock retention method outputs the signal in one of the normal operation mode and the retention mode. 17. The method according to item 12 of the scope of patent application, wherein the adjusted loop signal is generated by a first oscillator; and the synchronization output signal is generated by a second oscillator. (Please read the note on the back of the page before filling in this page.) This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 3037twf / 005 A8 B8 C8 D8 6. Application for patent scope 18. If the scope of patent application The method according to item 12, wherein the synchronous output signal and the adjusted loop signal are generated based on the second control signal under a single oscillator in one of a normal operation mode and the retained mode. 19. The method according to item 17 of the patent application, wherein the first oscillator and the second oscillator are both digitally controlled oscillators. 20 The method according to item 18 of the scope of patent application, wherein the oscillator is a digitally controlled oscillator. 1!, Strike-* (Please read the notes on the back before filling out this page) Order printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, and the paper is printed in accordance with China National Standards (CNS > A4 specifications (210X297 Mm)