TW395087B - Output buffer with high speed and low noise level - Google Patents

Abstract

The invention provides an output buffer with high speed and low noise level. It is applicable in slew controlling the gunning transceiver logic (GTL+) signals. The last output element is driven simultaneously by both the normal and rapid driven elements. The normal and rapid driven elements will act synchronously when the input signal is changing from one state to another. The rapidly driven element will pull up the control voltage of the output element to a potential level with one potential difference less than the last potential. The potential level will then be pulled up to the last potential level by the normal driven element. The output element's operation will be rapid at first. Then, the output operation will be slow down when it is close to the last potential level. By reducing the delaying time of output buffer without causing any large echoes in output signals, high speed and low noise level can be accomplished.

Description

:, ^ Τ'Γ ▼ Six ,, > Interpret whether to change the original substance or not The original substance is printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative 3232twf1 / 002 No. 87111577 Instruction Sheet A7 B7 Amend the date 8 V. DESCRIPTION OF THE INVENTION (1) At this time, the potential of the node 350 will be raised to a high potential. When the input signal A is in another state, for example, when the potential is high, the driving elements 32 丨 and 322 are turned on. At this time, the potential of the node 350 is lowered to the ground potential. The potential change of the node 350 will control whether the output element 330 is turned on or not. The four driving elements 311, 312, 321, and 322 can be divided into two groups according to their driving capabilities. One of the driving elements 311 and 321 is an ordinary driving element. The other driving element 312 and 322 has a large driving capability. The driving element has a faster switching speed and can quickly change the potential of the node 350. And when the driving element 311 is turned on, the potential of the node 350 can be increased to be close to the positive power source VCC, and when the driving element 312 is turned on, a fixed voltage drop is maintained between the node 350 and the positive power source VCC, for example, at a voltage less than IV Pressure drop. Similarly, when the driving element 321 is turned on, the potential of the node 350 can be pulled down to be close to the ground potential, and when the driving element 322 is turned on, a fixed voltage drop is maintained between the node 350 and the ground potential, for example, less than IV Pressure drop. The output buffer 300 'shown in the block diagram above can be explained by using the equivalent circuit of FIG. The FET 411 functions as the driving element 311, the FET 412 and the diode 413 function as the driving element 312, and the FET 411 and 412 are in the form of PMOS. The FET 421 functions as the driving element 321, FET 422, and diode 423. The function is the same as driving element 322, while FETs 421 and 422 are in the form of NMOS. In order to achieve the purpose of the above block diagram, the driving capability of FETs 412 and 422 is much larger than FETs 411 and 421, and diodes 413 and 423 are conducting. When there is a fixed voltage drop at both ends, about 0.7V. (Please read the notes on the back before filling this page)

This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm). Λιτ5ΐ-ΛΚ in the warp section. Consumption of bamboo, shirt 5, 3224twf / 005 A7 ___ B7. V. INTRODUCTION TO THE INVENTION (I) This invention is about An output buffer, and more particularly, it relates to an output buffer suitable for high-speed, low-noise slew control of GTL + signal specifications. In a typical digital circuit, 0V and 5V are usually used to represent different logic states of the digital signal. The components that make up a digital circuit can be divided into TTL and CMOS devices. Among them, digital circuits made up of TTL devices have faster speeds but consume higher DC power, while circuits made up of CMOS devices do not consume DC power. Slow and noisy. On the other hand, when the operating frequency of the logic circuit is increased to tens of MHz, if the parts are not properly arranged or properly isolated, electromagnetic interference (EMI) will occur. Due to the progress of the semiconductor manufacturing process, the operating voltage of CMOS digital circuits is getting lower and lower. If the operating voltage of the integrated circuit (1C) at both ends of the transmission line is not the same, it will cause the two 1Cs to have different output high potentials. Level. Therefore, another electronic signal specification called GTL (Gunning Transceiver Logic) output buffer has recently been proposed, and GTL + signal specifications have been further proposed later. The amplitude of the GTL + signal is between 0V and 1.5V, and a terminal resistor is connected to the terminal of the signal transmission line to 1.5V. In this way, when the transmission line is transmitting in two directions, its high potential will not be different because of the two 1C operating voltages. A circuit diagram of an output buffer of a conventional GTL + circuit is shown in FIG. The output buffer 100 can accept the input signal A and then output the output signal Vo. The input signal A generally has two states of high potential and low potential, and the output signal Vo changes with the input signal A. Then output signal Vo The paper size is suitable for Chinese National Standard (CNS) Α4 size (210X297mm) (Please read the precautions on the back before filling this page) .0. Ordering line 3224twf1 / 002 A7 B7

Printed by the Central Government of the Ministry of Economic Affairs and the Consumers 'Cooperatives I. V. Invention Description (丨 &); L—' 一 " The driving current is proportional to the driving current, that is, the larger the driving capacity, the faster the speed. The driving capacity is proportional to the gate width of the FET and inversely proportional to the gate length of the FET. Therefore, adjusting the gate width / length ratio of the FET can control the driving capability of each FET. For example, the The gate width / length ratio 値 is set approximately as follows. The ratio of FET 611 to FET 612 is 1: 7, and the ratio of FET 621 to FET 622 is 1:25. Because the mobility of general PMOS FETs is worse than that of NMOSFETs, in general transmission gates, PMOSFETs must have the same driving capabilities as NMOSFETs. The width / length ratio of PMOS FETs is about _〇S FETs. double. According to the above conditions, it can be concluded that the driving capability of the FET 612 is greater than that of the FET 611, and the driving capability of the FET 622 is greater than that of the FET 621. The driving capabilities of the FETs 612 and 622 are much larger than those of the FETs 611 and 621. Therefore, the basic idea of the present invention is different from the general transmission gate. In addition, the FET 630 provides the external output current, so its driving capacity is the largest. Through the above-mentioned high-speed and low-noise output buffer of the present invention, when the input signal is changed from one state to another state, the ordinary and fast driving elements act simultaneously, and the fast driving element quickly pulls the control voltage of the output element to A potential with a small gap from the final potential, and then the ordinary driving element will pull the control voltage to the final potential ', so that the output of the output element changes quickly at the beginning, and near the final state,' slows the speed of change, In this way, the change time of the entire state can be shortened, that is, the delay time of the output buffer is reduced, but it does not cause an excessively large echo of the output signal, thus achieving the purpose of high speed and low noise. From the above discussion, it can be seen that the high-speed and low-noise output buffer of the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) ir line 3224tWf / 〇〇S A7 -----_____ B7 V. Description of the invention (" " Send to other device's input / output terminal via transmission line 160, such as device 171, because Field Effect Transistor (surface FET) 130 adopts Open drain (〇Pen drain) connection, so the transmission line 160 can transmit signals in both directions. When the FET 13 is turned off, the input buffer 18 can receive signals from other devices, such as device 172. In order to make When the transmission line is transmitting in both directions, its high potential is the same voltage 値, so the terminal of the transmission line 160 is connected to the power supply vtt with a terminal resistance 165, and the power supply Vtt can generally be 1'5V. The output buffer 100 has two FETs 110 and 120. The driving transistor and the output transistor of the FET 130. The input signal a is passed through the driving transistor FETs 110 and 120 to provide sufficient driving current to drive the output transistor FET 130 'and the output transistor FET 130. It can provide greater driving capability to drive other circuit elements externally connected to the transmission line 160. When the input signal A is at a low potential, the FET 110 is turned on, and the blue potential of the FET 130 is pulled up to a high potential, which makes the FET 130 Turn on, pull down the output signal Vo to near ground potential, make the resistance of the terminal resistance 165 Rtt, and the on-resistance FET when the FET 130 is turned on is Rm, then the voltage of the output signal Vo at low potential is as follows Formula V〇 = Vtt * — ^

Rm + Rtt When the input signal A is high, the FET 120 is turned on. At this time, the gate potential of the FET 130 is pulled down to the ground potential, and the FET 130 is turned off. Because the FET 130 is connected to the transmission line 160 in an open-drain mode, when the FET 130 is turned off, the output signal Vo can be pulled up to the power supply Vtt by the terminating resistor 165, and can be regarded as a high potential. In addition, it can also change from output to input. Paper size suitable / 1] Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling out this page), / f installed · line 3224twf / 〇〇5 A7 3224twf / 〇〇5 A7 Haobu Department Zhongrong ir ^-^ d ·; /) Goods-taken Bamboo Woman Yindong I -------------- -B7 ___ V. Description of the Invention (4) ~-Input Buffer 180 Accept signals from other devices. Please refer to FIG. 2 for the waveforms of the input and output signals of the output buffer 100. The waveform (A) is that the input signal A changes from ^ potential to high potential at time u. Because the focus of the discussion here is on the change of the output buffer ', the time delay of the input signal A is ignored. At low frequencies, its output signal Vo is like waveform (B). After the delay time dl, the output signal Vo completely changes from low potential to high potential β. In order to increase the operating frequency of the system, it is important to shorten the delay time dl. Problem, but the general specifications of the output buffer have a minimum driving capacity for the output transistor, so the driving current capability of the driving transistor of the output buffer 100 can only be improved to make the switching speed of the transistor ^ Add. However, if the driving capacity of the driving transistors (110 and 120) is simply improved to shorten the delay time, the signal will be deteriorated, as shown in the waveform (C). After the delay time d2, the output signal Vo is completely changed from a low potential. &Amp; to a high potential, but because the FET 130 turns off quickly, the output signal changes too quickly 'will cause a ring back phenomenon, as shown by point P, the signal generates a ring back phenomenon, making it difficult for the receiving end to distinguish between “〇” and "The logic signal of Γ causes the system to be unstable. From the above discussion, we can see that the output buffer of the GTL + signal in Figure 1 has the following disadvantages: 1. In order to reduce noise, reduce the drive transistor of the output buffer. The driving ability makes the output transistor turn on or off slowly. Although it improves the noise problem, it will increase the delay time and increase the operating frequency. 2. In order to increase the operating frequency, increase the driving transistor of the output buffer 5 L- --1 ------% ------- 玎 ------ ^ f Jing first read the meaning of "a" on the back and then m'ic this page "This paper standard is deducted from the Chinese national standard (CNS) A4 specification (210 × 297 mm) 3224twf / 00 5 A7 B7 5. The driving ability of the invention description (丨) 'will make the output transistor turn on or off quickly and increase the switching speed'. Although it can increase the operating frequency, it is easy to cause the phenomenon of echo, noise, and the system. Work is unstable. Therefore, the main object of the present invention is to provide a high-speed low-noise slope control (slew cone) output buffer, which can effectively improve the working frequency of the output buffer, and can avoid the problem of causing backlash and noise . In order to achieve the above and other objectives of the present invention, the present invention provides a high-speed and low-noise output buffer for receiving an input signal including a first state and a second state, and outputting an output signal. The output buffer The device includes a first ordinary driving element, a first fast driving element, a second ordinary driving element, a second fast driving element, and an output element. The first common driving element has three terminals, a first terminal, a second terminal, and a third terminal. The first terminal receives the input signal, and the second terminal is coupled to a positive power source. In a state, the second terminal and the third terminal of the first ordinary driving element are conducted. The driving capability of the first fast driving element is much larger than that of the first ordinary driving element. The first fast driving element also has three ends: a first end, a second end, and a third end. The first end accepts the input. Signal, the second terminal is coupled to the positive power source, and when the input signal is in the first state, the second terminal and the third terminal of the first fast driving element are turned on 'after it is turned on' between the second terminal and the third terminal The terminal has a first potential difference. The second ordinary driving element has three ends of a first end, a second end, and a third end. 'The first end accepts the input signal.' The second table is connected to one 6 ^ ------- --- ^ '------ 1T ------ ^ (Please read the precautions on the back before filling in this page) Lightly hit the middle of the hit 4,-^ h This paper scale is suitable for China National Standard (CNS) A4 specification (210X297) 3224twf / 005 A7 B7 V. Description of the invention (f) Ground wire. When the input signal is in the second state, the second ordinary drive element The second terminal and the third terminal are conducted. The driving capability of the second fast driving element is much larger than that of the second ordinary driving element. The second fast driving element also has three end points: a first end, a second end, and a third end. The first end receives the input. Signal, the third terminal is coupled to the ground. When the input signal is in the second state, the second terminal of the second fast driving element is connected to the third terminal. After it is turned on, the second terminal is connected to the third terminal. The terminal has a second potential difference. The output element has three ends: a first end, a second end, and a third end. The first end is coupled to the third end of the first ordinary driving element, the third end of the first fast driving element, The second terminal of the second ordinary driving element and the second terminal of the second fast driving element. The third terminal of the output element is coupled to the ground. The second terminal of the output element outputs the output signal. When the first ordinary driving element and the first fast driving element are on, the second end and the third terminal of the output element are conducting. When the second ordinary driving element and the second fast driving element are on, the output element The second terminal and the third terminal are not conductive. According to a preferred embodiment of the present invention, the first potential difference is between 0 and IV, and the second potential difference is also between 0 and IV. According to another embodiment of the present invention, the present invention provides a high-speed and low-noise output buffer for receiving an input signal including a first state and a second state and a complementary input signal complementary to the input signal. And output an output signal, the output buffer includes a first ordinary transistor, a first fast transistor, a second ordinary transistor, a second fast ---: --------- batch of clothes ------ 1T ------ 0 (Read the precautions on the back before filling in this page) This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm) 3224twf / 005 A7 B7 In the Ministry of Foreign Affairs, i? -4, ^,-i! -T eliminates the need to combine bamboo printing ^ Five 'invention description (i) transistor, and an output transistor. The gate of the first ordinary transistor receives the input signal, and its source is coupled to a positive power source. When the input signal is in the first state, the drain and source of the first ordinary transistor are turned on. The driving capability of the first fast transistor is much larger than that of the first ordinary transistor. The gate of the first fast transistor receives the complementary input signal, and the source is coupled to the positive power source. When the input signal is the first In one state, the drain and source of the first fast transistor are turned on, and after it is turned on, there is a first potential difference between the drain and source. The gate of the second ordinary transistor receives the input signal, and its source is coupled to a ground. When the input signal is in the second state, the drain and source of the second ordinary transistor are turned on. The driving capability of the second fast transistor is much greater than that of the second ordinary transistor. Its gate accepts the complementary input signal, and its source is coupled to the ground. When the input signal is in the second state, the first The drain and source of the two fast transistors are turned on, and after they are turned on, there is a second potential difference between the drain and the source. The gate of the output transistor is coupled to the drain of the first ordinary transistor, the drain of the first fast transistor, the drain of the second ordinary transistor, and the drain of the second fast transistor. A source of the output transistor is coupled to the ground, a drain of the output transistor outputs the output signal, and when the first ordinary transistor and the first fast transistor conduct, the drain of the output transistor and The source is turned on, and when the second ordinary transistor and the second fast transistor are turned on, the drain and the source of the output transistor are not turned on. (Please read the notes on the back before filling out this page).

.1T line paper size applies Chinese National Standard (CNS) A4 specification (21 ×: 297 mm) A7 3224twf / 005 B7 Five 'invention description (^) According to a preferred embodiment of the present invention, wherein the first The state is to have a potential close to the positive power source, and the second state is to have a potential close to the ground line. The first ordinary transistor and the second fast transistor of the transistors are PMOS FETs, the first fast transistor, the second ordinary transistor, and the output transistor are MOS OS FETs, and the first transistor A potential difference is a threshold voltage of the Li OS FET, and the second potential difference is a threshold voltage of the PMOS FET. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings = FIG. 1 It is a circuit diagram of a conventional output buffer. Fig. 2 is a waveform of input and output signals of a conventional output buffer. FIG. 3 is a block diagram of the high-speed low-noise output buffer of the present invention. Fig. 4 is an equivalent circuit representing the block diagram of Fig. 3. FIG. 5 is a waveform of the equivalent circuit of FIG. 4. Fig. 6 is an actual circuit of Fig. 3. Brief description marked in the figure: 100 output buffer

110, 120, and 130 FET 160 transmission line 165 termination resistor 171 and 172 other devices 180 input buffer 300 output buffer ^ binding II line (read the precautions on the back before filling this page) ¥ ^ Μ-τ "φ; 合 竹 α 卬 The size of this paper is suitable for Chinese National Standards (CNS) A4 specifications (210X297 mm) A7 3224twf / 005 B7 V. Description of the invention (8) 311, 312, 321, and 322 Drive element 330 output element 350 node 400 output buffer

41, 412, 42, 422, and 430 FETs 413 and 423 diodes 450 nodes 600 output buffers 61 612, 621, 622, and 630 FET 650 nodes For a preferred embodiment, please refer to FIG. 3, which is shown in accordance with FIG. A block diagram of a high-speed and low-noise output buffer 300 according to a preferred embodiment of the present invention. The output buffer 300 can accept an input signal A and then output an output signal Vo. The input signal A generally has two states of high potential and low potential, and the output signal Vo changes with the input signal A. The output buffer 300 includes driving elements 311, 312, 321, and 322, and an output element 330. The input signal A passes the driving elements 311, 312, 321, and 322 to provide sufficient driving current to drive the output element 330, and the output element can provide greater driving capability to drive other external circuit elements. The driving elements 311, 312, 321, and 322 are three-terminal elements. The terminal receiving the input signal A is a control terminal, and can control the conduction of the other two terminals. When the input signal A is in one of two states, for example, when the potential is low, the driving elements 311 and 312 are turned on,---f. --- ^ ------- f ----- -IT ------ (锖 Please read the notes on the back before filling in this page) The Ministry of Finance and Economics lrif ^ hT, eliminated in the combination of the bamboo and y seals. This paper applies the Chinese National Standard (CNS) A4 specifications. (210X297mm) :, ^ Τ'Γ ▼ ,, > Interpretation of whether the change of the original type of content has been changed. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed 3224twf1 / 002, instruction sheet A11 B7 Amendment B7 Date 8 V. Description of the invention (1) At this time, the potential of the node 350 will be raised to a high potential. When the input signal A is in another state, for example, when the potential is high, the driving elements 32 丨 and 322 are turned on. At this time, the potential of the node 350 is lowered to the ground potential. The potential change of the node 350 will control whether the output element 330 is turned on or not. The four driving elements 311, 312, 321, and 322 can be divided into two groups according to their driving capabilities. One of the driving elements 311 and 321 is an ordinary driving element. The other driving element 312 and 322 has a large driving capability. The driving element has a faster switching speed and can quickly change the potential of the node 350. And when the driving element 311 is turned on, the potential of the node 350 can be increased to be close to the positive power source VCC, and when the driving element 312 is turned on, a fixed voltage drop is maintained between the node 350 and the positive power source VCC, for example, at a voltage less than IV Pressure drop. Similarly, when the driving element 321 is turned on, the potential of the node 350 can be pulled down to be close to the ground potential, and when the driving element 322 is turned on, a fixed voltage drop is maintained between the node 350 and the ground potential, for example, less than IV Pressure drop. The output buffer 300 'shown in the block diagram above can be explained by using the equivalent circuit of FIG. The FET 411 functions as the driving element 311, the FET 412 and the diode 413 function as the driving element 312, and the FET 411 and 412 are in the form of PMOS. The FET 421 functions as the driving element 321, FET 422, and diode 423. The function is the same as driving element 322, while FETs 421 and 422 are in the form of NMOS. In order to achieve the purpose of the above block diagram, the driving capability of FETs 412 and 422 is much larger than FETs 411 and 421, and diodes 413 and 423 are conducting. When there is a fixed voltage drop at both ends, about 0.7V. (Please read the notes on the back before filling this page)

This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 3224twf / 005 A7 3224twf / 005 A7 Warp 屮 Air4'- and m-Ti7i in Hezhu. ¾. Print to _____ B7 V. Invention Explanation (/.) The operation method of the above-mentioned high-speed and low-noise output buffer can be described with the waveform in Fig. 5. For convenience, only the actual circuit in Fig. 4 is used for explanation. The waveform (A) shows a state where the state of the input signal A changes from a high potential to a low potential at time t, and as described above, the delay time is ignored. The waveform (B) is assuming that Fet 411 is not connected, and the FET 412 and the diode 413 are considered separately. When the input signal a changes from a high potential to a low potential, the FET 412 is completely turned on after a delay time dl, and the node 450 is turned on. The potential of V is increased to the potential of the differential voltage drop Vx from the positive power source VCC, and the voltage drop Vx is equal to the forward voltage drop of the diode 413 by 0.7V. The waveform (C) is assuming that the FET 412 and the diode 413 are not connected, and the FET 411 is turned on separately. When the input signal a changes from a high potential to a low potential, the FET 411 is fully turned on after a delay time d2, and the node is turned on. The potential of 450 is increased to be close to the positive power source VCC, and since the driving capability of the FET 411 is smaller than that of the FET 412, the delay time d2> dl. The waveform (D) is to consider the conduction situation when FET 411, FET 412, and diode 413 are connected at the same time. When the input signal A changes from high potential to low potential, FET 411 and FET 412 start conducting at the same time. The driving power of 412 is large, so the potential of node 450 can be quickly raised to the potential of the differential voltage drop Vx from the positive power supply VCC, and then the potential of node 450 can no longer be raised, and FET 411 continues to increase the potential of node 450. The potential rises to a level close to the positive power source VCC, the delay time at which the potential of the node 450 changes from a low potential to a high potential is d3, and the comparison of the delay times of the three waveforms is d2 > d3 > dl. The waveform (E) is the change of the output signal Vo. When the node 450 (谙 read the precautions on the back before filling in this page) 5 ·

， 1T-The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 3224twf / 005 A7 B7 V. Description of the invention (/ ί) The potential is raised to a high potential, and the FET 430 is turned on, and the output signal Vo is pulled As low as close to the ground potential, when the output signal Vo starts to change, the falling speed is faster due to the action of the FET 412. When the FET 412 stops functioning, the FET 411 acts alone, so the change rate slows down, so the overall fall time can be shortened , And can reduce the phenomenon of signal oscillation, and achieve the goal of high speed and low noise. The fast driving element in the output buffer circuit of FIG. 4 is composed of FETs and diodes. In actual production, the effect is limited. Therefore, the circuit shown in FIG. 6 can be used to implement it. Please also refer to the block diagram in FIG. 3, where FET 611 functions as the driving element 311, FET 612 functions as the driving element 312, and FET611 is in the form of PM0S, FET612 is in the form of NMOS, and FET 621 functions as the driving element 321. The function of FET 622 is similar to that of driving element 322. FET 621 is in the form of NMOS, and FET 622 is in the form of PM0S. To achieve the above block diagram, the driving capabilities of FETs 612 and 622 need to be much larger than those of FETs 611 and 621. Because the control methods of NM0S and PM0S are different ', FETs 611 and 621 are controlled by input signal A, and FETs 612 and 622 are controlled by complementary input signal X. Please refer to the waveform in Figure 5 at the same time. When it becomes low, the complementary input signal X changes from low to high. First consider the FET 612. After the complementary input signal X goes high, the FET 612 'will start to conduct.' Because the FET has a threshold voltage, so the connection of the FET 612 is shown in the figure. When the FET 612 is fully turned on, It is not possible to raise the potential of node 650 to be close to a positive power supply. /.1. ^; ------- install-- (诮 Read the precautions on the back before filling this page) The center of the 軤 浐 part of the wire «. ^-^^^ Industrial, consumer, and industrial resources ^ The printed rice paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 gong) 3224twf / 005 A7 B7: 'Ministry of China Rongda iv-/: Jh τ_ Disappeared in combination " Ink 5 、 Invention (/ ^) vcc 'and there is a fixed voltage drop between the positive voltage and VCC equal to the threshold voltage. At this time, the threshold voltage is critical because it is affected by the body effect. The voltage is larger than normal, so the waveform of node 65 is as shown in the waveform (B) in Figure 5. Although the driving capability of FET 612 is large, the potential of node 650 can only be raised to a level different from the positive power supply VCC. The potential of the voltage drop Vx, which is the threshold voltage of the FET 612. Considering the situation of FET 611 again, FET 611 starts conducting after the input signal A goes low. As shown in the waveform (C) in Figure 5, although the speed of FET 611 is slower, the potential of node 650 can be increased. To a potential very close to the positive supply VCC. Therefore, when the FETs 611 and 612 function at the same time, their waveforms are as shown in the waveform (D) in Figure 5. When the FET 612 starts to conduct, the potential of the node 650 is quickly raised to the potential of the voltage drop Vx from the positive power supply VCC. After the FET 612 stops functioning, the FET 611 continues to function, and the potential of the node 650 is further increased to be closer to the positive power source VCC. On the other hand, the functions of FET 621 and FET 622 are the same. When input signal A changes from low potential to high potential, FET 622 is turned on by complementary input signal X from high potential to low potential. The potential is pulled down to a potential that is different from the ground potential by a voltage drop Vx, where the voltage drop Vx is the critical voltage of the FET 622, and after the FET 622 stops functioning, the FET 621 continues to function, pulling the node 650 potential closer to ground Potential. As discussed above, the output buffer circuit of Fig. 6 functions just like the circuit of Fig. 4, but it can reduce the output delay time and noise. When actually manufacturing a semiconductor circuit, the switching speed of MOS FET is not the same as that (诮 Please read the precautions on the back before filling in this page)

'J, 11 This paper is suitable for standard month] China National Standards (CNS) Α4 size (210 × 297 male thin) 3224twf1 / 002 A7 B7

Printed by the Central Government of the Ministry of Economic Affairs and the Consumers 'Cooperatives I. V. Invention Description (丨 &); L—' 一 " The driving current is proportional to the driving current, that is, the larger the driving capacity, the faster the speed. The driving capacity is proportional to the gate width of the FET and inversely proportional to the gate length of the FET. Therefore, adjusting the gate width / length ratio of the FET can control the driving capability of each FET. For example, the The gate width / length ratio 値 is set approximately as follows. The ratio of FET 611 to FET 612 is 1: 7, and the ratio of FET 621 to FET 622 is 1:25. Because the mobility of general PMOS FETs is worse than that of NMOSFETs, in general transmission gates, PMOSFETs must have the same driving capabilities as NMOSFETs. The width / length ratio of PMOS FETs is about _〇S FETs. double. According to the above conditions, it can be concluded that the driving capability of the FET 612 is greater than that of the FET 611, and the driving capability of the FET 622 is greater than that of the FET 621. The driving capabilities of the FETs 612 and 622 are much larger than those of the FETs 611 and 621. Therefore, the basic idea of the present invention is different from the general transmission gate. In addition, the FET 630 provides the external output current, so its driving capacity is the largest. Through the above-mentioned high-speed and low-noise output buffer of the present invention, when the input signal is changed from one state to another state, the ordinary and fast driving elements act simultaneously, and the fast driving element quickly pulls the control voltage of the output element to A potential with a small gap from the final potential, and then the ordinary driving element will pull the control voltage to the final potential ', so that the output of the output element changes quickly at the beginning, and near the final state,' slows the speed of change, In this way, the change time of the entire state can be shortened, that is, the delay time of the output buffer is reduced, but it does not cause an excessively large echo of the output signal, thus achieving the purpose of high speed and low noise. From the above discussion, it can be known that the high-speed and low-noise output buffer of the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) ir line 3224twf / 005 A7 B7 V. Inventor (丨 +) has the following advantages compared with the conventional method: 1. With ordinary and fast driving elements at the same time, when the output transistor is turned on or off, it changes quickly first and then slowly changes to The final state can increase the switching speed, effectively reduce the delay time, and increase the operating frequency. 2. Because the output signal changes quickly first, and then slowly changes to the final potential, this can effectively avoid the phenomenon of excessive signal oscillation and reduce the problem of noise. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make a few changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. I —: ------- qi ------ 1T ------ mr (Please read the precautions on the back before filling in this page) Blow in the warp section " ^ " Jh- T " Cargo Bamboo Private Print 5: This paper is suitable for Chinese National Standard (CNS) Α4 size (210X297 mm)

Claims (1)

3224twf / 005 Μ B8 C8 D8 6. Application scope 1. A high-speed low-noise output buffer for receiving an input signal including a first state and a second state, and outputting an output signal, the output The buffer includes: a first common driving element having a first terminal, a second terminal, and a third terminal. The first terminal receives the input signal, and the second terminal is coupled to a positive power source. When the input signal is in the first state, the second terminal of the first ordinary driving element is in conduction with the third terminal; a first fast driving element having a driving capacity greater than that of the first ordinary driving element, the first fast driving The device has a first terminal, a second terminal, and a third terminal. The first terminal receives the input signal, the second terminal is coupled to the positive power source, and when the input signal is in the first state, the The second terminal of the first fast driving element is electrically connected to the third terminal, and when it is turned on, there is a first potential difference between the second terminal and the second terminal; a second ordinary driving element having a first End, a second end, and The third terminal, the first terminal accepts the input signal, the third terminal is coupled to a ground wire, and when the input signal is in the second state, the second terminal of the second ordinary driving element and the third terminal A terminal is turned on; a second fast driving element having a driving capacity greater than the second ordinary driving element, having a first terminal, a second terminal, and a second terminal, the first terminal receiving the input signal, the The third terminal is coupled to the ground. When the input signal is in the second state, the second terminal of the second fast driving element is conductive with the third terminal, and after it is turned on, at the second terminal Has a second potential difference from the third terminal; and an output element with a first terminal, a second terminal, and a third terminal, (please read the precautions on the back before filling this page) Standards Bureau employees' consumer cooperatives printed the paper size to apply Chinese National Standard (CNS) A4 specifications (210X297 mm), Central Standards Bureau of the Ministry of Economy, Shellfish Consumer Cooperatives, printed 32 2 4twf / 005 gg CS D8 A first end is coupled to the first The third end of the drive element, the third end of the first fast drive element, the second end of the second ordinary drive element, and the second end of the second fast drive element, the output element The third terminal is coupled to the ground, and the second terminal of the output element outputs the output signal. When the first ordinary driving element and the first fast driving element are turned on, the second terminal of the output element is connected to the first terminal. Three terminals are turned on. When the second ordinary driving element and the second fast driving element are turned on, the second end and the third end of the output element are turned off. 2. As for the high-speed and low-noise output buffer described in item 1 of the scope of patent application, the first potential difference is between 0 and IV. 3. As for the high-speed and low-noise output buffer described in item 1 of the patent application scope, the second potential difference is between 0 and IV. 4. A high-speed and low-noise output buffer for receiving an input signal including a first state and a second state and a complementary input signal complementary to the input signal, and outputting an output signal, the output buffer The device includes: a first ordinary transistor whose gate receives the input signal, and whose source is coupled to a positive power source; when the input signal is in the first state, the drain and source of the first ordinary transistor The pole is turned on; a first fast transistor whose driving capacity is much larger than that of the first ordinary transistor; the gate of the first fast transistor receives the complementary input signal, and its source is coupled to the positive power source, and when the input When the signal is in the first state, the drain and source of the -fast transistor are turned on, and after it is turned on, there is a first potential difference between the drain and source; (Please read the precautions on the back first (Fill in this page again.) Installation, 1T-绛 · This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 3224twf / 005 395087 B8 CS D8范围 The scope of the patent application is a second ordinary transistor whose gate receives the input signal and whose source is coupled to a ground. When the input signal is in the second state, the drain of the second ordinary transistor Connected to the source; a second fast transistor whose driving capacity is much greater than the second ordinary transistor, whose gate accepts the complementary input signal, and whose source is coupled to the ground line, when the input signal is the first In the two states, the drain and source of the second fast transistor are turned on, and after it is turned on, there is a second potential difference between the drain and source; and an output transistor whose gate is coupled to The drain of the first common transistor, the drain of the first fast transistor, the drain of the second ordinary transistor, and the drain of the second fast transistor, and the source of the output transistor is coupled Connected to the ground, its drain electrode outputs the output signal. When the first ordinary transistor and the first fast transistor are on, the drain and source of the output transistor are on. When the second ordinary transistor is on, And when the second fast transistor is turned on, the output The drain and source of the transistor are not conductive. 5. The high-speed, low-noise output buffer described in item 4 of the scope of the patent application, the first state is a potential close to the ground. 6. The high-speed and low-noise output buffer as described in item 4 of the scope of the patent application, the second state has a potential close to the positive power source. 7. According to the high-speed, low-noise output buffer described in item 4 of the patent application scope, the first ordinary transistor is a PMOS FET. 8. According to the high-speed, low-noise output buffer described in item 4 of the patent application scope, the first fast transistor is an NMOS FET. 9. The output of high-speed and low-noise output is slow as described in item 8 of the scope of patent application (please read the precautions on the back before filling this page). The paper size applies to Chinese national standards (CNS > A4 specifications (210X297) (Centi) 3224twf / 005 395087 B8 C8 D8 6. The patent application range punch, the first potential difference is the threshold voltage of the NMOS FET. 10. The output buffer with high speed and low noise as described in item 4 of the patent application range, The second ordinary transistor is an NMOS FET. 11. As the high-speed and low-noise output buffer described in item 4 of the scope of patent application, the second fast transistor is a PMOS FET. The output buffer of high speed and low noise according to item 11, the second potential difference is the threshold voltage of the PMOS FET. 13. The output buffer of high speed and low noise as described in item 4 of the scope of patent application, the output voltage The crystal is an NMOS FET. (Please read the precautions on the back before filling in this page.) Order embroidery 'Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Paiger Consumer Cooperatives. 297 mm)