2988twf.doc/006 A7 B7 五、發明説明（/ ) 本發明是有關於一種嵌入式動態隨機存取記憶體 (Embedded Dynamic Random Access Memory; Embedded DRAM)的製造方法，且特別是有關於一種將自行對準金屬 矽化物（5_e」—f-Aligned Siliaiii©·; Salicd/i)製程應用 至嵌入式DRAM的製造方法。 習知邏輯電路元件和記憶體元件是分別位於不同的 晶片上，然在目前速度要求愈來愈快的時代，已經漸漸趨 向於將兩種不同的元件同時製造於同一晶片上，以增加資 料處理的速度，此種將邏輯電路元件和記憶體元件佈局於 一晶片上的半導體元件是爲嵌入式J3RAM。 然而，邏輯電路元件和記憶體元件在製程上的要求不 同，由於邏輯電路元件主要是做邏輯運算之用，需要求其 資料傳送的速度，所以需降低源極/汲極的片電阻（Sheet Resistance)，於是會在源極/汲極的表面利用自行對準 金屬矽化物形成一層金屬矽化物，比如矽化鈦。然而在記 憶體元件方面，由於記憶體元件是做爲資料儲存之用，因 爲需避免有漏電流的情形發生，以維持儲存資料的正確 性，所以在源極/汲極的表面不會形成金屬矽化物層》 習知嵌入式DRAM的製造方法之流程頂視圖或剖面 圖，如第1A圖至第1H圖所示。 首先請參照第1A圖，提供一基底100,比如是矽基底， 接著進行隔離製程，以形成元件隔離結構101，比如是場 氧化層（LOCOS)或淺溝渠隔離（STI)結構。其中包括邏 輯電路區103和DRAM記憶體區105。之後於基底1〇〇表面 3 本紙张尺度適州中闽囤家榇準（CNS > Α4規格（210Χ297公釐} —r--------^ —— * \ (請先閱讀背面之注^^15^!^寫本頁) 訂 線 2988twf.doc/006 A 72988twf.doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing an Embedded Dynamic Random Access Memory (Embedded DRAM), and in particular to a method for The aligned metal silicide (5_e "—f-Aligned Siliaiii © ·; Salicd / i) process is applied to the manufacturing method of embedded DRAM. It is known that logic circuit elements and memory elements are located on different chips. However, in the current era of faster and faster requirements, it has gradually become more and more common to manufacture two different components on the same chip to increase data processing The speed, this type of semiconductor components that arrange logic circuit elements and memory elements on a chip is embedded J3RAM. However, the requirements of the logic circuit element and the memory element are different in the manufacturing process. Since the logic circuit element is mainly used for logic operations, the data transmission speed is required, so the sheet resistance of the source / drain electrode should be reduced. ), A self-aligned metal silicide is used to form a layer of metal silicide on the source / drain surface, such as titanium silicide. However, in terms of memory components, since the memory components are used for data storage, because leakage situations need to be avoided to maintain the accuracy of the stored data, no metal is formed on the source / drain surface. "Silicon layer" The top view or cross-sectional view of the process of the conventional manufacturing method of embedded DRAM, as shown in Figures 1A to 1H. First, referring to FIG. 1A, a substrate 100, such as a silicon substrate, is provided, and then an isolation process is performed to form an element isolation structure 101, such as a field oxide (LOCOS) or shallow trench isolation (STI) structure. These include a logic circuit area 103 and a DRAM memory area 105. Then on the substrate 100 surface 3 This paper size is suitable for Zhongzhou, Fujian, China (CNS > Α4 size (210 × 297 mm) —r -------- ^ —— * \ (Please read the back first Note ^^ 15 ^! ^ Write this page) Booking line 2988twf.doc / 006 A 7
五、發明説明（上） 依序形成一層氧化層102和一層未摻雜的多晶矽層104。 之後進彳了互補式金氧半導體（ComplementaryV. Description of the Invention (above) An oxide layer 102 and an undoped polycrystalline silicon layer 104 are sequentially formed. 2. Complementary metal oxide semiconductor
Metal-Oxide Semiconductor; CMOS)製程，於基底 100 上形成PM0S和NM0S兩種電晶體。於是，首先進行雙重閘 極（Dual Gate)的製程。 請參照第1B圖’比如先進行用於NM0S電晶體部份的 多晶矽層104之摻雜。於多晶矽層1〇4上覆蓋一層罩幕層 108’ ’此罩幕層108’暴露出欲形成NM0S電晶體的區域，然 後進行N+型離子107’的摻雜，使所暴露出的多晶矽層1〇4 形成N+型摻雜的多晶矽層1〇4,。 請參照第1C圖’之後比如再進行用於PM0S電晶體部 份的多晶矽層104之摻雜。於剝除掉罩幕層1〇8’後，再形 成另一層罩幕層108”覆蓋住N+型摻雜的多晶矽層104’，暴 露出的區域是爲欲形成PM0S電晶體的區域，然後進行P+ 型離子107”的摻雜，使所暴露出的多晶矽層104形成P+ 型摻雜的多晶矽層104”。 於第1B圖和第1C圖中，所分別形成的N+型摻雜的多 晶矽層104’和P+型摻雜的多晶矽層104”，即爲雙重的閘 極。 接著請參照第1D圖，爲了增加傳輸的速度，因此通 常會在N+型摻雜的多晶矽層104’和P+型摻雜的多晶矽層 104”上面再加一層導電性較佳的多晶矽化物（Poly Silicide)，比如矽化鎢（WSh)層 114。 接著請參照第1E圖，定義氧化層102、N+型摻雜的多 4 本紙張尺度通州中國國家標準（CNS > A4规格（210X297公釐） (讀先聞讀背面之注意事項Vs；寫本萸) •裝. 訂 線 2988twf.doc/006 A7 B7 五、發明説明（多） '~一 (讳先閱讀背面之注意事項寫本筲) 晶矽層104,、P+型摻雜的多晶矽層104”和矽化鎢層U4， 以於邏輯電路區103形成閘極氧化層l〇2a、N+型摻雜的多 晶矽層l〇4’a、P+型摻雜的多晶矽碍l〇4，’a和矽化鎢層 114a;且同時於跗翊記憶體區1〇5形成閘極氧化層102b、 N+型摻雜的多晶矽層104’b、P+型摻雜的多晶矽層i〇4”b和 矽化鎢層114b。其中邏輯電路區103的閘極氧化層i〇2a、 N+型摻雜的多晶矽層1〇4’a和矽化鎢層ii4a組成N+型閘極 電極’閘極氧化層l〇2a、P+型摻雜的多晶矽層l〇4，，a和矽 化鎢層114a組成P+型閘極電極。DRAM記憶體區105亦同， 在此不多贅^。 然而，多晶矽化物層，比如矽化鎢層114，有不易蝕 刻的缺點。 接著請參照第1F圖，然後使用離子佈植法植入低濃 度的離子，以閘極電極爲罩幕，自行對準基底100，而在 基底100上形成淡摻雜源/汲極區109。接著，形成一層 氧化物質，並且使用非等向性回蝕刻法蝕刻此層氧化物 質，而在閘極電極的兩側形成間隙壁（Spacer) 106。然 後’同樣使用離子佈植法植入高濃度的離子，以閘極電極 與間隙壁106爲罩幕，自行對準基底1〇〇，而在基底1〇〇 上形成濃摻雜源/汲極區119。接著，進行快速高溫製程 (RTP)，使所摻雜的離子可以均勻分佈。其中閘極氧化 層102b下方及淡摻雜源/汲極區109之間會形成一通道區 (Channel Region)。然而在此快速禹溫製程期間，N型 摻雜的多晶矽層104’a和P+型摻雜的多晶矽層104”a的界 5 本紙張尺度適用中囷國家揉準（CNS ) A4規格（210X297公釐） 2988twf.doc/006 A7 B7 五、發明説明（y) 面處，或者N+型摻雜的多晶矽層l〇4’b和P+型摻雜的多晶 矽層104”b的界面處，會分別藉由其上方的矽化鎢層114a 和114b而有互相擴散的情形發生。而且矽化鎢層114a和 114b，在經快速高溫製程時，因其材質的熱穩定性 (Thermal St abi 1 i ty )不佳，會有晶粒聚集 (Agglomerate)的現象發生，因此容易造成斷裂，而影 響其導電性。 接著請參照第1G圖，於DRAM記憶體元件區105覆蓋 一層氧化層112b，用以保護DRAM記憶體元件區105的M0S 電晶體。’ 接著請參照第1H圖，於邏輯電路區103之源極/汲極 區219的表面形成一層自行對準金屬矽化物，常用的是矽 化鈦。 然而此後續製程爲熟習此技藝者所熟知，故此處不再 贅述。 由於在DRAM記億體元仵區105之源極/汲極區不能形 成金屬矽化物，在此習知的方法中，爲了降低DRAM記憶 體元仵區105之閘極電極的阻値，所以利用多晶矽化物來 降低其阻値。而爲了在邏輯電路區103之源極/汲極區形 成自行對準的矽化物，因此需用罩幕層覆蓋其他區域，如 此增加了製程的複雜性。另外，多晶矽化物有不易進行蝕 刻的缺點，且會有熱穩定性不佳的問題，以及藉由多晶矽 化物層使N+型摻雜的多晶矽層和P+型摻雜的多晶矽層的界 面有內擴散的現象發生。 6 本紙張尺A適州中國國家標準（CNS ) A4規格（210X297公釐） ----------- »· (销先閱讀背面之注意事^寫本页) 、-β •L--—線 經7¾•部中央榀工消贽合作妇卬犁 2988twf.doc/006 A7 B7 五、發明説明（r) 因此本發明的主要目的，就是在提供一種將自行對準 金屬矽化物製程應用至嵌入式DRAM的製造方法，避 免多晶矽化物層所引起之熱穩定性不佳的問題。 本發明的另一目的’就是在提供一種將自行對準金屬 矽化物製程應用至嵌入式DRAM的製造方法，可以避免在 雙重閘極的製程中，有內擴散的情形發生。 爲達成本發明之上述和其他目的，一種將自行對準金 屬矽化物製程應用至嵌入式DRAM的製造方法，適用於已 形成有第一和第二MOS電晶體的基底，其中第一 M〇s電晶 體位於基底乏邏輯電路區，第二MOS電晶體位於基底之記 憶體區。第一和第二MOS電晶體分別包括第一和第二閘極 電極、第一和第二源極/汲極區以及第一和第二間隙壁， 第一和第二閘極電極分別包括第一和第二多晶矽層，此製 造方法包括下列步驟：形成絕緣層覆蓋第一和第二MOS電 晶體，接著去除部份絕緣層，直至裸露出第一和第二摻雜 的多晶矽層之表面，以及裸露出部份第一和第二間隙壁， 再定義絕緣層，以完全暴露出邏輯電路區之第一MOS電晶 體。以此絕緣層爲罩幕，進行自行對準金屬矽化物製程， 以形成金屬矽化物層，於第一的多晶矽層、第一源極/汲 極區和第二多晶矽層的表面。 所以，本發明不需要多晶矽化物的製程’僅利用自行 對準矽化物製程，一倂於邏輯電路區和DRAM記憶體區的 閘極電極和邏輯電路區的源極/汲極區上，形成自行對準 的矽化物，且可以避開對多晶矽化物層進行蝕刻之製程， 7 本紙乐尺度通州中國囷家標準（CNS ) A4規格（210X297公釐） ] I I I i I I I I I 訂— 11 I 線 I· (誚先閲讀背面之注意事寫本頁) 2988twf.doc/006 A7 B7 五、發明説明（έ ) (讀先閱讀背面之注意事寫本頁) 因此可以簡化製程。且N+型或P+型摻雜的多晶矽層上的砍 化金屬層，係於源極/汲極區快速熱製程後才形成，因此 所以沒有熱穩定性和內擴散方面的問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1H圖係繪示一種習知嵌入式DRAM的製 造方法之流程頂視圖或剖面圖；以及 第2 A i至第2H圖係繪示根據本發明較佳實施例之 一種嵌入式DRAM的製造方法之流程頂視圖或剖面圖。 其中，各圖標號與構件名稱之關係如下： 100、 200 基底 101、 201 元件隔離結構 102、 202 氧化層 104、204 未摻雜的多晶矽層 108’、108”、208’、208” 罩幕層 107’、207’ N+型離子 104’、104’a、104’b、204’、204’a、204’b N+型摻雜 的多晶砂層 107”、207” P+型離子 104”、104，’a、104”b、204”、204”a、204，，b P+型摻 雜的多晶矽層 114' 114a' 114b 砂化鶴層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經Μ部中央榀枣而於.Τ消处合作私印製 2988twf.doc/006 A 7 _B7_ 五、發明説明（7) 103、203 邏輯電路區 105 ' 205 DRAM記憶體區 102a、102b、202a、202b 閘楫氧化層 109、209 淡摻雜源/汲極區 106、206 間隙壁 119、219 濃摻雜源/汲極區 229 源極/汲極區 212、212a、212b 絕緣層 224 矽化金屬層 實施例 第2 A圖至第2H圖所示，爲根據本發明較佳實施例 之一種嵌入式DRAM的製造方法之流程頂視圖或剖面圖。 首先請參照第2A圖，提供一基底200,比如是矽基底， 接著進行隔離製程，以形成元件隔離結構201，比如是場 氧化層、淺溝渠隔離結構或其他類似此結構者。其中包括 邏輯電路區203和DRAM記憶體區205。之後於基底200表 面依序形成一層氧化層202和一層未摻雜的多晶矽層 204。 之後進行CMOS製程，於基底200上形成PMOS和NMOS 兩種電晶體。在此以具有雙重閘極的CMOS製程爲例，於 是，首先進行雙重閘極的製程。 請參照第2B圖，比如先進行用於NM0S電晶體部份的 多晶矽層204之摻雜。於多晶矽層204上覆蓋一層罩幕層 208’，此罩幕層208’暴露出欲形成NM0S電晶體的區域’然 9 本紙張尺度適扣肀闽國家栋準（CNS > Α4規格（210X297公廣） —r--------批衣------1T---------1^ *- (請先閱讀背面之注f項寫本頁) ί 2988twf.doc/006 A7 B7 五、發明説明（？） 後進行N+型離子207’的掺雜，使所暴露出的多晶矽層2〇4 形成N+型摻雜的多晶矽層2〇4,。 請參照第2C圖，之後比如再進$用於PMOS電晶體部 份的多晶砂層204之摻雜。於剝除掉罩幕層208’後，再形 成另一層罩幕層208”覆棻住N+型摻雜的多晶矽層2〇4，，暴 露出的區域是爲欲形成PM〇s電晶體的區域，然後進行 型離子207”的摻雜，使所暴露出的多晶矽層2〇4形成p+ 型摻雜的多晶矽層204”。 於第2B圖和第2C圖中分別所形成的N+型摻雜的多晶 矽層204’和>+型摻雜的多晶矽層2〇4”，即爲雙重的閘極。 然亦可先進行P+型離子的摻雜，再進行N+型離子的摻雜。 接著請參照第2D圖’定義氧化層202、N+型摻雜的多 晶砂層204’和Γ型摻雜的多晶矽層2〇4”，以於邏輯電路 區203形成聞極氧化層2〇2a、N+型摻雜的多晶矽層204，a 和P+型摻雜的多晶矽層2〇4，’a ;且同時於DRAM記憶體區 205形成閘極氧化層202b、N+型摻雜的多晶矽層204，b和 P+型摻雜的多晶矽層2〇4”b。其中邏輯電路區203的閘極 氧化層202a、N+型摻雜的多晶矽層2〇4，a組成N+型閘極電 極’閘極氧化層202a和P+型摻雜的多晶矽層2〇4，，a組成p+ 型閘極電極。DRAM記憶體區205亦同。 本發明與習知不同之處，在於習知會於N+型摻雜的多 晶砍層104’和P+型摻雜的多晶砂層1〇4”上方沈積一層砂 化金屬層114(如第1D圖所示），再進行定義閘極電極； 而本發明於形成N+型摻雜的多晶砂層204’和P+型摻雜的多 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 i * (讀先閲讀背面之注意事本頁) 、-'° 經浐部中次榀4,·Λ只-τ消费合作沿印^ 麪碘部中次^準而只工消贽合作拉卬y 2988twf.doc/006 A 7 B7 I I . ll H -i — ·,··^ __. 五、發明説明（？） 晶矽層204”之後’未再沈積矽化金屬層即進行定義閘極電 極。 接著請參照第2E圖，取第2D圖中之一剖面做以下詳 細的說明。然後使用離子佈植法植入低濃度的離子，以閘 極電極爲罩幕，自行對準基底200，而在基底200上形成 淡摻雜源/汲極區209。接著，形成一層氧化物質，並且 使用非等向性回蝕刻法蝕刻此層氧化物質，而在閘極電極 的兩側形成間隙壁206 »然後，同樣使用離子佈植法植入 高濃度的離子，以閘極電極與間隙壁206爲罩幕，自行對 準基底200，插在基底200上形成濃摻雜源/汲極區219。 其中閘極氧化層202b下方及淡摻雜源/汲極區209之間會 形成一通道區。接著，利用快速高溫製程或火爐進行回 火，使所所摻雜的離子可以均勻分佈，以標號229來表示 由淡摻雜源/汲極區209和濃摻雜源/汲極區219所組成 的源極/汲極區229。 由於N+型摻雜的多晶矽層204’a和P+型摻雜的多晶矽 層204”a，或N+型摻雜的多晶矽層204’b和P+型摻雜的多 晶矽層204”b，上方均未有沈積矽化金屬層，因此不會有 習知因矽化金屬材質的熱穩定性不佳，而在經快速熱回火 製程期間所引發的一些問題產生》 接著請參照第2F圖’形成一層毯覆式的絕緣層212 覆蓋邏輯電路區203和DRAM記憶體區205的閘極電極’ 絕緣層212的材質比如是氧化物，其形成方法比如是化學 氣相沈積法。其中此絕緣層212已經過平坦化製程。 ----------^------ΐτ--------„--ΙΦ. 二- (許先閱讀背面之注意事項寫本頁) 本紙張尺度適州中國國家榇準（CNS > A4規格（210X297公釐） 2988twf.doc/006 A 7 五、發明説明（/〇 ) 接著請參照第2G圖，進行回蝕刻製程，使氧化層212 形成氧化層212a，以暴露出N+型摻雜的多晶矽層204’a和 204’b以及P+型摻雜的多晶矽層204”a和204”b的表面， 且暴露出部份間隙壁206的表面。 接著請參照第2H圖，定義氧化層212a，使其形成只 覆蓋DRAM記憶體區205的氧化層212b，此氧化層212b可 以保護DRAM記憶體區205的源極/汲極區229。之後，爲 了增加傳輸的速度，因此會在N+型摻雜的多晶矽層204’a 和204’b、P+型摻雜的多晶矽層204”a和204”b、以及邏輯 電路區103 ή源極/汲極區219表面，形成一層導電性較 佳的矽化金屬層224,其方法係爲自行對準矽化金屬製 程，形成矽化鈷（CoSiO、矽化鈦（TiSh)或其他類似 此性質者。 由於所形成的矽化金屬層224係於源極/汲極區229 的快速熱製程後才形成，所以沒有熱穩定性和內擴散方面 的問題。 然而此後續製程爲熟習此技藝者所熟知，故此處不再 贅述。 本發明的特徵如下： (1)本發明不需要多晶矽化物的製程，僅利用自行對 準矽化物製程，一倂於邏輯電路區和DRAM記憶體區的閛 極電極和邏輯電路區的源極/汲極區上，形成自行對準的 矽化物，且可以避開對多晶矽化物層進行蝕刻之製程，因 此可以簡化製程。 本紙張尺度適/1】中國國家標準（CNS ) Α4况格（210Χ297公釐） L---------------ΐτ-----—.^ -- (誚先閲讀背面之注意事寫本頁) 2988twf.doc/006 A7 B7 五、發明説明（Μ ) (2)本發明的N+型或P+型摻雜的多晶矽層上的矽化金 屬層，係於源極/汲極區快速熱製程後才形成，因此所以 沒有熱穩定性和內擴散方面的問題。； 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----------装------ΐτ-------- J- (請先閱讀背面之注意事iS?填寫本页) 經Μ部中头榀卑而只工消贫合作妇印掣 13 本紙張尺度適《】中國國家標隼（〇?«)八4規格（210/297公釐）Metal-Oxide Semiconductor (CMOS) process, forming two transistors, PMOS and NMOS, on the substrate 100. Therefore, a dual gate process is first performed. Please refer to FIG. 1B ', for example, first doping the polycrystalline silicon layer 104 for the NMOS transistor portion. A polycrystalline silicon layer 104 is covered with a masking layer 108 '' This masking layer 108 'exposes a region where an NMOS transistor is to be formed, and then N + type ions 107' are doped to make the exposed polycrystalline silicon layer 1 〇4 Forming an N + doped polycrystalline silicon layer 104. Please refer to FIG. 1C for the doping of the polycrystalline silicon layer 104 for the PMOS transistor portion. After stripping the mask layer 108 ′, another mask layer 108 ″ is formed to cover the N + -type doped polycrystalline silicon layer 104 ′. The exposed area is the area where the PMOS transistor is to be formed. The doping of P + type ions 107 "causes the exposed polycrystalline silicon layer 104 to form a P + type doped polycrystalline silicon layer 104". In Figures 1B and 1C, the N + type doped polycrystalline silicon layer 104 is formed respectively. The 'and P + -type doped polycrystalline silicon layer 104' is a double gate. Next, please refer to FIG. 1D. In order to increase the transmission speed, an N + -type doped polycrystalline silicon layer 104 'and a P + -type doped polycrystalline silicon layer 104 "are usually added with a layer of polysilicide with better conductivity. ), Such as tungsten silicide (WSh) layer 114. Next, please refer to Figure 1E to define the oxide layer 102, N + type doped 4 paper size Tongzhou Chinese National Standard (CNS > A4 specification (210X297 mm)) (read First read the precautions on the back Vs; writings 萸) • binding. Binding line 2988twf.doc / 006 A7 B7 V. Description of the invention (multiple) '~ 1 (Forbidden to read the precautions on the back first 筲) crystalline silicon layer 104, P + doped polycrystalline silicon layer 104 "and tungsten silicide layer U4 to form gate oxide layer 102a, N + type doped polycrystalline silicon layer 104'a, P + type doped polycrystalline silicon in logic circuit region 103 Obstruct 104, 'a and the tungsten silicide layer 114a; and simultaneously form a gate oxide layer 102b, an N + -type doped polycrystalline silicon layer 104'b, and a P + -type doped polycrystalline silicon layer i in the 跗 翊 memory region 105. 〇4 ″ b and tungsten silicide layer 114b. Gate oxide layer 103 of logic circuit region 103 is doped with N + type. The polycrystalline silicon layer 104′a and the tungsten silicide layer ii4a constitute an N + gate electrode, the gate oxide layer 102a, the P + doped polycrystalline silicon layer 104, a, and the tungsten silicide layer 114a constitute a P + gate. Electrode. The same is true for the DRAM memory region 105, which is not necessary here. However, the polysilicide layer, such as the tungsten silicide layer 114, has the disadvantage of being difficult to etch. Then refer to FIG. 1F, and then use the ion implantation method to implant Into a low concentration of ions, the gate electrode is used as a mask, and the substrate 100 is aligned with itself, and a lightly doped source / drain region 109 is formed on the substrate 100. Next, a layer of oxide is formed, and an anisotropic return is used. The etching method etches this layer of oxide material, and forms a spacer (Spacer) 106 on both sides of the gate electrode. Then, the ion implantation method is also used to implant a high concentration of ions, with the gate electrode and the spacer 106 as a cover. , Aligning the substrate 100 by itself, and forming a heavily doped source / drain region 119 on the substrate 100. Next, a rapid high temperature process (RTP) is performed to uniformly distribute the doped ions. Among them, the gate electrode Below the oxide layer 102b and between the lightly doped source / drain regions 109 A channel region is formed. However, during this rapid Yu-Wan process, the boundary between the N-type doped polycrystalline silicon layer 104'a and the P + -type doped polycrystalline silicon layer 104 "a 5 Standard (CNS) A4 specification (210X297 mm) 2988twf.doc / 006 A7 B7 V. Description of the invention (y) At the plane, or N + type doped polycrystalline silicon layer 104′b and P + type doped polycrystalline silicon layer 104 At the interface of "b", mutual diffusion occurs through the tungsten silicide layers 114a and 114b above it, respectively. Moreover, the tungsten silicide layers 114a and 114b are easily broken due to the poor thermal stability of the material (Thermal St abi 1 i ty) during the rapid high-temperature process. And affect its conductivity. Next, referring to FIG. 1G, the DRAM memory element region 105 is covered with an oxide layer 112b to protect the MOS transistor of the DRAM memory element region 105. ′ Next, referring to FIG. 1H, a layer of self-aligned metal silicide is formed on the surface of the source / drain region 219 of the logic circuit region 103, and titanium silicide is commonly used. However, this subsequent process is well known to those skilled in the art, so it will not be repeated here. Since metal silicide cannot be formed in the source / drain region of the DRAM memory cell region 105, in the conventional method, in order to reduce the resistance of the gate electrode of the DRAM memory cell region 105, it is used Polycrystalline silicide to reduce its resistance. In order to form a self-aligned silicide in the source / drain region of the logic circuit region 103, it is necessary to cover other regions with a mask layer, which increases the complexity of the process. In addition, polycrystalline silicides have the disadvantages that they are not easy to etch, and they have the problem of poor thermal stability, and the interface between the N + -type doped polycrystalline silicon layer and the P + -type doped polycrystalline silicon layer has internal diffusion through the polysilicide layer. The phenomenon occurs. 6 This paper ruler A Shizhou Chinese National Standard (CNS) A4 specification (210X297 mm) ----------- »· (Read the precautions on the back of the pin first, write this page), -β • L ---- Wire warp 7¾ • Ministry Central Laboratories and Consumers Cooperation Cooperative Women and Children Plow 2988twf.doc / 006 A7 B7 V. Description of the Invention (r) Therefore, the main purpose of the present invention is to provide a self-aligned metal silicide The process is applied to the manufacturing method of the embedded DRAM to avoid the problem of poor thermal stability caused by the polycrystalline silicide layer. Another object of the present invention is to provide a manufacturing method for applying a self-aligned metal silicide process to an embedded DRAM, which can avoid the occurrence of internal diffusion in a dual gate process. In order to achieve the above and other objectives of the present invention, a manufacturing method for applying a self-aligned metal silicide process to embedded DRAM is applicable to a substrate on which first and second MOS transistors have been formed, where the first M0s The transistor is located in the region lacking logic circuits, and the second MOS transistor is located in the memory region of the substrate. The first and second MOS transistors include first and second gate electrodes, first and second source / drain regions, and first and second spacers, respectively. The first and second gate electrodes include first and second gate electrodes, respectively. A first and a second polycrystalline silicon layer. The manufacturing method includes the following steps: forming an insulating layer to cover the first and second MOS transistors, and then removing a portion of the insulating layer until the first and second doped polycrystalline silicon layers are exposed. The surface and the first and second gap walls are exposed, and then an insulating layer is defined to completely expose the first MOS transistor in the logic circuit area. Using the insulating layer as a mask, a self-aligned metal silicide process is performed to form a metal silicide layer on the surface of the first polycrystalline silicon layer, the first source / drain region, and the second polycrystalline silicon layer. Therefore, the present invention does not require a polycrystalline silicide process. Only the self-aligned silicide process is used, and the gate electrode of the logic circuit region and the DRAM memory region and the source / drain region of the logic circuit region are formed by themselves. Aligned silicide, and can avoid the process of etching the polycrystalline silicide layer. 7 paper scale Tongzhou China Standard (CNS) A4 specification (210X297 mm)] III i IIIII Order — 11 I line I · ( (阅读 Read the notes on the back first and write this page) 2988twf.doc / 006 A7 B7 5. Description of the invention (Hand) (Read the notes on the back first and write this page) Therefore, the process can be simplified. In addition, the cleaved metal layer on the N + -type or P + -type doped polycrystalline silicon layer is formed after the rapid thermal process of the source / drain region, so there are no problems with thermal stability and internal diffusion. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1 to FIG. 1H are top views or cross-sectional views of a conventional embedded DRAM manufacturing method; and FIGS. 2A to 2H are illustrations of an embedded DRAM according to a preferred embodiment of the present invention Method flow top view or section view. The relationship between each icon number and component name is as follows: 100, 200 substrate 101, 201 element isolation structure 102, 202 oxide layer 104, 204 undoped polycrystalline silicon layer 108 ', 108 ", 208', 208" mask layer 107 ', 207' N + type ions 104 ', 104'a, 104'b, 204', 204'a, 204'b N + type doped polycrystalline sand layers 107 ", 207" P + type ions 104 ", 104, 'a, 104 ”b, 204”, 204 ”a, 204 ,, b P + -doped polycrystalline silicon layer 114' 114a '114b Sanding crane layer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ） Printed in cooperation with the Ministry of Commerce of the Central Ministry of Civil Affairs and printed 2988twf.doc / 006 A 7 _B7_ V. Description of the invention (7) 103, 203 logic circuit area 105 '205 DRAM memory area 102a, 102b, 202a , 202b Gate oxide 109, 209 Lightly doped source / drain region 106, 206 Spacer 119, 219 Heavyly doped source / drain region 229 Source / drain region 212, 212a, 212b Insulating layer 224 Metal silicide Figure 2A to 2H of the multi-layer embodiment, which is a method for manufacturing an embedded DRAM according to a preferred embodiment of the present invention Process sectional top view or FIG. First, please refer to FIG. 2A, provide a substrate 200, such as a silicon substrate, and then perform an isolation process to form an element isolation structure 201, such as a field oxide layer, a shallow trench isolation structure, or other similar structures. These include a logic circuit area 203 and a DRAM memory area 205. An oxide layer 202 and an undoped polycrystalline silicon layer 204 are sequentially formed on the surface of the substrate 200. Thereafter, a CMOS process is performed to form two transistors, PMOS and NMOS, on the substrate 200. Here, a CMOS process with a double gate is taken as an example. Therefore, a process of a double gate is first performed. Please refer to FIG. 2B, for example, doping the polycrystalline silicon layer 204 for the NMOS transistor part first. The polycrystalline silicon layer 204 is covered with a masking layer 208 ', and the masking layer 208' exposes the area where the NM0S transistor is to be formed. However, the paper size is suitable for the National Fujian Standard (CNS > Α4 size (210X297) Guang) —r -------- batch clothes ------ 1T --------- 1 ^ *-(please read the note f on the back to write this page) ί 2988twf. doc / 006 A7 B7 V. Description of the invention (?) After the doping of N + type ions 207 ', the exposed polycrystalline silicon layer 204 is formed into an N + type doped polycrystalline silicon layer 204. Please refer to 2C Then, for example, the polycrystalline sand layer 204 for the PMOS transistor is doped. After the mask layer 208 'is stripped off, another mask layer 208 "is formed to cover the N + type doping. The polycrystalline silicon layer 204 is exposed, and the exposed area is a region where a PMOS transistor is to be formed, and then doped with a type ion 207 ", so that the exposed polycrystalline silicon layer 204 is doped with a p + type. Polycrystalline silicon layer 204 ". The N + type doped polycrystalline silicon layer 204 'and the + type doped polycrystalline silicon layer 204" formed in Figs. 2B and 2C, respectively, are double gates. You can also do P + first Doping of N + type ions, and then doping of N + type ions. Next, please refer to FIG. 2D 'define oxide layer 202, N + type doped polycrystalline sand layer 204', and Γ type doped polycrystalline silicon layer 204 ', A gate oxide layer 202a, an N + type doped polycrystalline silicon layer 204, a, and a P + type doped polycrystalline silicon layer 204, 'a are formed in the logic circuit region 203; and a gate is formed in the DRAM memory region 205 at the same time Polar oxide layer 202b, N + doped polycrystalline silicon layer 204, b, and P + doped polycrystalline silicon layer 204 "b. The gate oxide layer 202a of logic circuit region 203, and N + doped polycrystalline silicon layer 2b. 4, a constitutes an N + type gate electrode 'gate oxide layer 202a and P + type doped polycrystalline silicon layer 204, and a constitutes a p + type gate electrode. The same is true for the DRAM memory region 205. The present invention is different from the conventional one The point is that it is customary to deposit a sanded metal layer 114 (as shown in FIG. 1D) on the N + -doped polycrystalline cutting layer 104 'and the P + -doped polycrystalline sand layer 104 ". The gate electrode is defined; and the present invention is applicable to the formation of N + -type doped polycrystalline sand layer 204 'and P + -type doped multiple paper sizes applicable to Chinese national standards (CN S) A4 specification (210X297 mm) i * (read the caution page on the back of the page first),-'° The middle section of the warp section 榀 4, · Λ only -τ Consumption cooperation along the print ^ The middle section of the iodine section ^ Collaborative cooperation and cooperation only 2988twf.doc / 006 A 7 B7 II. Ll H -i — ·, · ^ __. V. Description of the invention (? ） After the crystalline silicon layer 204 ”, the gate electrode is defined without further depositing a silicided metal layer. Next, please refer to FIG. 2E and take a section in FIG. 2D for the following detailed description. Then use ion implantation to implant A low-concentration ion, using the gate electrode as a mask, self-aligns the substrate 200, and a lightly doped source / drain region 209 is formed on the substrate 200. Next, a layer of oxide is formed, and anisotropic etchback is used. Etching this layer of oxidizing material, and forming the spacer 206 on both sides of the gate electrode »Then, using the ion implantation method to implant a high concentration of ions, using the gate electrode and the spacer 206 as a cover, self-alignment The substrate 200 is inserted on the substrate 200 to form a heavily doped source / drain region 219. A channel region is formed under the gate oxide layer 202b and between the lightly doped source / drain region 209. Next, a rapid high temperature process is used. Or the furnace is tempered so that the doped ions can be evenly distributed. The source / drain composed of the lightly doped source / drain region 209 and the heavily doped source / drain region 219 is denoted by reference numeral 229. Region 229. Polycrystalline silicon layer 20 due to N + type doping 4'a and P + type doped polycrystalline silicon layer 204 "a, or N + type doped polycrystalline silicon layer 204" b and P + type doped polycrystalline silicon layer 204 "b, there is no silicide metal layer deposited on top, so it will not It is known that some problems caused by the rapid thermal tempering process due to the poor thermal stability of the silicided metal material. Then refer to FIG. 2F 'form a blanket-type insulation layer 212 to cover the logic circuit area. 203 and the gate electrode of the DRAM memory region 205. The material of the insulating layer 212 is, for example, an oxide, and the method of forming the insulating layer 212 is, for example, a chemical vapor deposition method. The insulating layer 212 has undergone a planarization process. ---- ^ ------ ΐτ -------- „-IΦ. II-(Xu Xian read the precautions on the back and write this page) This paper is suitable for China State Standards (CNS) > A4 specification (210X297 mm) 2988twf.doc / 006 A 7 V. Description of the invention (/ 〇) Next, referring to Figure 2G, perform an etch-back process to form the oxide layer 212 into an oxide layer 212a to expose the N + type The surfaces of the doped polycrystalline silicon layers 204'a and 204'b and the P + type doped polycrystalline silicon layers 204 "a and 204" b are exposed Part of the surface of the spacer 206. Next, referring to FIG. 2H, define the oxide layer 212a so that it forms an oxide layer 212b that only covers the DRAM memory region 205. This oxide layer 212b can protect the source / Drain region 229. Thereafter, in order to increase the transmission speed, N + type doped polycrystalline silicon layers 204'a and 204'b, P + type doped polycrystalline silicon layers 204 "a and 204" b, and logic circuit regions 103. The surface of the source / drain region 219 forms a silicidated metal layer 224 with better conductivity. The method is to align the silicided metal process to form cobalt silicide (CoSiO, titanium silicide (TiSh) or other similar properties). By. Since the formed silicided metal layer 224 is formed after the rapid thermal process of the source / drain region 229, there are no problems with thermal stability and internal diffusion. However, this subsequent process is well known to those skilled in the art, so it will not be repeated here. The features of the present invention are as follows: (1) The present invention does not require a polycrystalline silicide process, and only uses a self-aligned silicide process. The source electrode of the logic circuit region and the DRAM memory region and the source / On the drain region, a self-aligned silicide is formed, and the process of etching the polycrystalline silicide layer can be avoided, so the process can be simplified. The size of this paper is / 1] Chinese National Standard (CNS) Α4 condition (210 × 297 mm) L --------------- ΐτ -----—. ^-(诮First read the note on the back to write this page) 2988twf.doc / 006 A7 B7 V. Description of the invention (M) (2) The silicided metal layer on the N + or P + doped polycrystalline silicon layer of the present invention is tied to the source The / drain region is formed after a rapid thermal process, so there are no problems with thermal stability and internal diffusion. ; Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. ---------- Install ------ ΐτ -------- J- (Please read the iS on the back first? Fill out this page) Only the work of poverty alleviation and cooperation, women's seals 13 This paper is suitable for "] Chinese National Standard (0?«) 8 4 specifications (210/297 mm)