TW392255B - Insulated gate semiconductor device with gate bus channel - Google Patents

Abstract

The invention relates to an insulated gate semiconductor device that has gate bus channel. In this device an epitaxy layer for being used as the drain region is first deposited on a heavily doped silicon substrate. An insulated gate layer of silicon oxide and a conductive gate layer are formed sequentially on the epitaxy layer. A p-type well is then implanted and formed in the epitaxy layer followed by the p-type heavily doped area formation in the p-type well. Under the gate bus channel, heavy n-type doping is implanted on the edge of the gate electrode. The metal layer of source electrode and the metal gate bus channel are then formed after the formation of boron phosphor silicon glass dielectric layer, so as to obtain an insulated gate semiconductor device with gate bus channel is obtained.

Description

Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 5. Description of the Invention (1) Field of the Invention: The present invention relates to an insulated gate semiconductor device, and more particularly, an insulated gate semiconductor with a gate connection channel. element. 5-2 Background of the Invention: Bipolar Junction Transistor (BJT) is one of the most important semiconductor components in modern times. Although it can be used for high-power components and high-speed logic circuits, it consumes a large amount of energy. The ills. Now, fast-growing metal-oxygen half field effect transistors (^ {431-Oxide-Semiconductor Field Effect Transistor-MOSFET) have gradually replaced BJT applications. Generally known as Insulated Gate Semiconductor Device, the most famous one is the metal-oxide-semiconductor (M0S) structure described above. The insulation layer used in this MOSFET is silicon dioxide ' Crystal silicon replaces metal as the gate, which consumes less power and is suitable for high accumulation. Silicon is more resistant to high temperatures and increases component stability, but the disadvantages are higher sheet resistance and larger RC constant (wire resistance Multiplied by the dielectric capacitor in series), the breakdown voltage is lower. Therefore, the general M0SFET is not suitable for high-power applications. "'The new structure of the power M0SFET transistor has a short channel and a high breakdown voltage. The most common is a vertical type called double-di f fused. DM0S transistor. As shown in the second figure, it is a traditional 2 paper size applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) (Please read the precautions on the back before filling this page). Packing. Order V. Invention Description ( A7 B7 A cross-sectional view of a vertical MOSFET power transistor printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. This figure is a view taken along the BB section of the first figure. ) The substrate 10 is used as a drain. On top, a lightly doped n_ epitaxial layer is deposited, and then a continuous diffusion is performed, one forming a p-type body region 12 ′ and the other forming an n-type source region. 13. The epitaxial layer} i is doped with an insulating gate compound a, a silicon layer 14 and a dielectric layer material such as filled silica glass (PSG) or borophosphosilicate glass, and a layer 15 is formed. It is the metal conductive layer of the source 16. The channel of this power transistor is-active, parallel short channel area controlled by the gate, and the current flows through the parallel short induced in the body (b〇dy) S 12 during operation. The channel then flows vertically downward to the pole. If the channel is shorter, it is easier to make electricity. The above switch can be applied to, for example, the control circuit of a motor; if the channel width is larger, the component's ability to carry current is increased, that is, its on-resistance (0I1 resistance, 1 ?. 0) is reduced. The second figure It is a view along the AA cross section of the first figure, which is exemplified by the formation of the previous technology-the gate bus of the power transistor (Gate Bus) where the bottom is a heavily doped n-type (or p-type) The substrate for the drain electrode 10 is the worm crystal layer 11 and the epitaxial layer u forms a body region 12 and an epitaxial layer! J is doped with a polycrystalline silicon layer 14 on which a borophosphosilicate glass is deposited. Layer 15 and finally a gate connection 17 is formed. This gate connection only serves as a gate connection to reduce the gate resistance and enhance the frequency response. The channel structure of the traditional power M0SFET transistor is It is formed by arranging an array of multiple unit cells as shown in Fig. I. '. When conducting, its on-resistance (Ron) is related to the resistance of the metal wire and the resistance of the channel. The reduction of n) has been a goal that the previous technology has been trying to achieve, and today Private paper scales apply Chinese national standards —_ (_. CNS) Α4 size (2 丨 0X297 mm) (Please read the precautions on the back before filling this page). ， Νβ Μ Γ

I A7 B7 V. Description of the Invention (The development of power MOSFET transistors is still committed to the reduction of the conduction nozzle and the increase of the breakdown voltage in order to improve the performance of the device.-However, in traditional power transistors, they can only rely on multiple Channels formed by individual unit cell arrays to reduce resistance, or to study the method of reducing the resistance of metal wires to improve the effectiveness of power transistors, without using closed-pole connections that already exist in the element. This invention is to use The Gate Bus Channel increases the channel width during conduction, thereby reducing the on-resistance (Ron). — 5-3 Purpose and Summary of the Invention: In view of the above background of the invention, the on-resistance of the power MOSFET transistor The reduction of (R ..) has always been a goal that those skilled in the art want to achieve. Therefore, one purpose of the present invention is to increase the channel of component conduction by using the gate connection "discuss BUS" to reduce the component. The on-resistance of the power transistor of the present invention 'firstly uses a heavily doped N-type (or P-type) substrate as the sink, and then sinks on this substrate An epitaxial layer, and then a silicon oxide layer is formed on the substrate and the epitaxial layer as a gate insulating layer, and then a doped polycrystalline silicon layer is formed on the gate insulating layer as a gate conductive layer, and traditional ions are used. Implantation and diffusion steps to form a first type well), and then perform a second ion implantation and diffusion step in the first type: and in the formation of a doped region (P-type heavily doped region) as an ohmic contact region Then, a third ion implantation and diffusion step is used to form a second doped region (N-type heavily doped region) in the first well. This is the ohmic source region of the power transistor, and then this paper is applicable to China National Standard .. (CNS) M Grid (210X297 mm) Please read the "Notes-" on the reverse side and fill out this page.

The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs prints this graphic to make the first unit of the second formation of the third technical institute, the formation of the fourth invention, the fifth invention; the fifth formation of a more detailed vertical column The vertical power diagram shown in the gate diagram is shown in the figure. The vertical power diagram is half-power electricity. V. INTRODUCTION () The fourth ion implantation and diffusion steps are performed in the gate region. At the gate edge, the gate channel A third doped region α-type heavily doped region is formed in the first type well below, as another ohmic source region of this power transistor, and then a borophosphosilicate glass (BpSG) is formed on the oxide layer and the gate electrode layer. ) Material of the dielectric layer, and then a metal layer is formed on the first doped region and the second doped region as an electrical connection of the source electrode of the power transistor, and finally in the gate region between the unit cell array A metal layer for the gate connection channel is formed thereon, and then a wire layer required for these metal layers is made by etching to complete the invention. 5-4 Schematic illustration: The preferred embodiment will be supplemented by the following description in the following explanatory text: is a top view of a power transistor unit cell array, where the poles are connected by a gate channel; is the first figure The view of the BB load plane 'wherein is the vertical power transistor according to the first insulation gate; is a view of the AA cross section in the first figure, where the vertical power transistor is connected according to the first gate; A cross section view of an epitaxial layer, a silicon oxide layer, and a sluice. Chi layer conductor wafer according to the present example of the transistor, and the steps of the sluice layer and the P-well of the crystal according to the present invention; The scale is applicable to the Chinese National Standard (CNS). Λ4 grid (210X297 mm) -------------------------------- Order (please read the note on the back first) (Fill in this page again)

V. Description of the invention (printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, the photo is a cross-sectional view of a semiconductor wafer, exemplifying the source, gate dielectric layer and source of a vertical power transistor formed in accordance with the present invention Steps of the metal layer; FIG. 7 shows a view of the AA cross section in the first figure, exemplifying the steps of forming a heavily doped n + region and a gate connection channel of a vertical power transistor according to the present invention; A schematic circuit diagram of a vertical power transistor with a gate connection channel according to the present invention. 5-5 Detailed description of the invention: The power disclosed by the present invention is a power transistor with a gate connection channel. Characteristics, the previous technology has been committed to reducing the on-resistance (Ron), but in addition to channel resistance (channel resistance), most people still research on reducing the resistance of the source metal conductor; and the present invention uses the traditional The gate connection of the power transistor (Gate Bus) adds an N-type doped region to increase the source region, and forms a parallel short channel region at the gate edge under the gate connection channel. Contributing to the current, that is, reducing the on-resistance (Ron). In the drawings of the present invention, for the sake of consistency, the same numbers: all represent the same components, and the proportions in the figure are only for convenience It is understood that the basket is not shown according to the actual size. Please refer to the first figure, which shows the top view of the power transistor unit cell array, in which the square area 12 is a p + doped ohmic contact area, this paper scale Applicable to Chinese National Standard (.CNS) A4 specification (210X297mm) Please read the back — item on page B. Binding line B7 V. Description of the invention (and area 13 is N-type. 17 is the gate connection area; ^ pole &, region 14 is a gate conductive layer, and region is a source metal layer. °° 20 is an N-type re-doped region. And region 21 is shown in the cross-sectional view of the transistor. The invention forms a work-heavily doped N-type or? -Type = BB cross section in the figure. First, a body material is provided, and a semiconductor and a semiconductor material layer u: are formed thereon. 11 is-epitaxial layer, and the substrate is 10 domains. This vertical power The drain region of the body: = an electrical layer is formed on the + conductor material layer u. 8 is the gate electrode s. For the S. edge, it must be uniform in thickness and good in structure. &, The silicon dioxide emulsified silicon layer or other high-quality electrical insulation layers, the thickness of the silicon oxide dielectric layer 18 is about 100,000 angstroms in a practical example. Yu Fang, .. < j then formed the conductive layer 14 by the conventional chemical vapor deposition (CVD) method, which is generally doped with a polycrystalline silicon layer, and then used a lithography process. A photoresist pattern 19 is formed on the conductive layer 14. Then refer to the fifth figure, which shows the steps for forming the gate conductive layer and the 'well' according to the present invention. As described above, when the photoresist pattern 19 is formed on the conductive layer 14, the photoresist pattern 19 is used as a mask, and the polar conductive layer 14 is etched until the oxide layer i 8 is exposed, and then The Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed the order of ion implantation and diffusion in the semiconductor material layer u to form the valence of ions—P-type well 12, this P-type well 12 is also called the body (b. dy) area. Refer to Figure 26, which shows that the paper size of the power transistor production paper according to the present invention is applicable to the Chinese National Winter Standard (CNS) A4 specification (210X 297 cm) Γτ _ ^ ___ 1M Printed by the Central Standards Bureau of the Ministry of Economic Affairs Description (the subsequent steps of the process. After the p-type well 12 is opened, and the resistance (not shown in the figure) 'is followed, the first impurity is performed on the appropriate light; # The cloth of the electric layer 14 and the dielectric layer 18-ions Implantation and diffusion-doped regions (not shown in the figure), and the first and second functional regions are formed in the P-type well 12, which is a P-type heavily doped region (P +) photoresist (The unobtrusive heliocentric contact region is not used. Then use the appropriate m not shown in the figure.) It is formed on the first doped region fw,,; of the electric layer 18 of Lixiatian, and is covered by the P-type well- Ion implantation and diffusion steps and a second doped region 13 is formed in step 2, which is implanted with a pentavalent impurity; the ions of this first doped region 13 are thus 'N' This type of cabin is 狭 r 丄, and this region is approximate! Heavily doped £ (n + region), and is used as the source region of the power transistor. The cloth is worthy of the "Master," and this sixth figure is the first one in the figure—the section along the ββ section, and the source region 13 is the surrounding area in the car train of each unit cell ': The formation of the unit cell array will form multiple conductive channels in the power transistor, that is, the formation of the unit cell array will increase the channel width. 'On-resistance is inversely proportional to the channel width of the element, so the conduction can be reduced. The resistance (r.η) 'increases the operating rate of the power transistor. However, as also shown in the first figure, a conventional source N-type heavily doped region is formed in each unit cell, and an array of connected unit cells is connected There are no channels formed in the region where the pole electrodes are connected to 17. Therefore, referring now to the seventh figure, this figure is a view along the AA cross section in the first figure. After the second doped source: region 1 3 is formed 'Then perform the steps of the fourth ion implantation and diffusion; and in'; in the P-type well 12, the gate edge under the gate connection region 17 forms a third doped region 20, and this third doped region 20 is also It is an N-type heavily doped region (n +). Next, the gate conductive layer 14 of the power transistor array is shaped. This paper boron phosphorous silica scale applicable standard rate home ( 'CNS) Λ4 size (210X297 mm) -------- - loaded - t - (Please read the Notes on the back to fill out this page)

TT I I.

Hi 凌 声 # 'Shiye Han's yeast 丨 A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Bei Gong Xiao Cooperative Co., Ltd. 5. Description of the invention () Glass (BPSG) or Phosphor-Silicon Glass (PSG) insulation layer I5' and then reused The photoresist performs a separate step on this insulating layer 15 to form a contact window to expose the P-type well 12 shown in the sixth figure, the second doped region I3, and the gate connection region shown in the seventh figure. Then, a source metal layer 21 is formed on the exposed p ^ i well 12 and the second doped region 13 in the sixth figure, and a gate connection channel 17 is formed on the gate connection region shown in the seventh figure. Then, the power layer of the present invention is completed by making a wire layer. The original gate bus connection can reduce the gate resistance and thus reduce the tiine de 1 ay constant of the RC product (line resistance multiplied by the series capacitor) and increase the frequency response, but the invention Since the gate connection is also doped with the n + region 20 in the P-type well 12 surrounding the gate connection, it can also be used as a component to increase the width of the channel and thereby reduce the on-resistance (Ron). Refer to the eighth figure, which is a schematic diagram of the circuit of the power transistor with an interrogating electrode connection channel of the present invention. As mentioned above, since the region 17 connected to the gate electrode has an n + region 20, the gate electrode controls The parallel channel section has also been increased. The gate connection channel also functions as a component. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. ， ·· This paper size applies to China National Standard (_ CNS) A4 size (210 X 297 public completion (please read the precautions on the back before filling this page) 、-口 Γ

Claims (1)

Scope of patent application Patent scope: 1. An insulated gate semiconductor element including at least: a doped semiconductor substrate; a semiconductor material layer formed on the semiconductor substrate > and the pole region on the semiconductor substrate; and A first type well with second electrical properties, and a first type well and a third type well; a first dielectric layer formed on the semiconductor substrate and the layer A conductive layer, which is located on the first dielectric layer, and provides an insulating gate layer of a conductive element; a second dielectric layer, which is formed on the semiconductor material, and an exposed portion of the semiconductor material layer and The use of the protective layer; the material layer and the conductive layer are a first metal layer, which is formed on the second consumer layer of the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives with the second dielectric being the conductive layer, and is connected to the conductive layer as For external electrical connection; and a second metal layer, which forms a layer of -t, and is connected to the semiconductor material for electrical connection of the insulating gate semiconductor. The source layer of the first body element and the gate connecting layer and the well are connected to the second dielectric layer, and the second semiconductor material is electrically conductive, the second semiconductor material is electrically insulating, and the insulating gate is semi-conductive. Layer, and as a barrier layer on top of the conductive layer and to the semiconductor: the material should be the second; the type well is also bound as the external j ^, 4 (Please read the precautions on the back before filling out this page} 1, 10 copies Paper size applies Chinese national standard. (CNS) A4 size (210X297 mm) A8 B8 C8 D8 Patent application scope 2. If the patent application scope, the first layer is an insect crystal dream layer. The above-mentioned semiconductor material wherein the above-mentioned first electrical property is a silicon oxide layer. Among them, the above-mentioned first dielectric layer wherein the above-mentioned conductive layer is a doped polycrystalline silicon layer% 6. For example, the first item in the scope of the patent application is borophosphosilicate glass (BPSG) or phosphosilicate glass (Wherein the above-mentioned second dielectric layer PSG). The first type well mentioned above and 7. If the second type well of item 1 of the scope of patent application is located under the second metal layer and connected to the second metal layer, it is used as a channel for conduction. . ^ ^. Binding · ^ (Please read the notes on the back side before filling in this tile). "Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives" The first type: the well and the third type well are located under the first metal layer and the 'edge' edge of the conductive layer as a channel for conduction. • A method for forming an insulated gate semiconductor element, the method includes at least: 11 paper sizes, using Chinese National Standard (CNS) A4 (210X297 mm) A8 B8 C8 D8 patent application scope forming a semiconductor chair material layer on a On the semiconductor substrate, the semiconductor layer is the drain region of the insulated gate semiconductor element and has the first electrical property; / the first; | the electrical layer on the semiconductor substrate and the semiconductor material layer--C-., Forming a The conductive layer is on the first dielectric layer; the electrical layer is provided with an insulating gate layer of the insulating gate semiconductor element; and the guard is formed: a first-type well in the semiconductor material layer, and the second Negative death / forming a first-type well in the ancient female flute «,] ji I first-electricity; opening ...- type well, and the second-type well has the formation of a third-type well between A and the- Electrical properties; and the third type well has the formation-second dielectric layer between the semiconductor material layer and the conductive layer, and the semiconductor material delamination protection layer in the bypass portion; And the conductive layer, and forming a first metal layer as a spacer Connect the second dielectric with the conductive layer for electrical connection between the conductive layer and the second layer; and a layer of idler connection channels and form a second metal layer externally to the second dielectric. The electrical layer is printed on the consumer cooperative of the Central Standard Bureau of the Ministry of Semiconductor Economy, and the first type well and the second type well are connected with the source of the semiconductor element, and serve as a gate for the opposite side. The electrical connection is useless. 10. The method according to item 9 of the scope of patent application, wherein the hair layer is a worm crystal layer. ', The above-mentioned semi-conductor materials 12 This paper size applies to Chinese national standards. (CNS) A4 specification (210X297 mm) ------- A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Patent application scope 11. The method according to item 9 of the patent application scope, wherein the first electrical property is N-type and the second electrical property is P-type. 12. The method according to item 9 of the application, wherein the first dielectric layer is a silicon oxide layer. 13. The method of claim 9 in which the above-mentioned conductive layer is a doped polycrystalline silicon layer. 14. The method according to item 9 of the application, wherein the second dielectric layer is borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG). 15. For the method of claim 9 in the scope of patent application, wherein the above-mentioned first type well and the second type well are located below the second metal layer and connected to the second metal layer as a transmission Channel. 16. The method according to item 9 of the scope of patent application, wherein the above-mentioned first type well and the third type well are located under the first metal layer and the edge of the conductive layer as a channel during conduction. 1 7. — An insulated gate semiconductor element array including at least: a doped semiconductor substrate; a semiconductor material layer formed on the semiconductor substrate, which is the insulation (please read the precautions on the back first) Soul write this page); Binding. Order, ii This paper wave scale adopts Chinese national standard .. (CNS) A4 specification (21 × 297 mm) Scope of patent application Gate semiconductor element array in the drain region of the first type of the second type well and the third type of well still have the second electrical conductivity; the well, and the bottom of the conductor, have the first semiconductor-electric body A first dielectric layer formed on the half layer; a conductive layer on the first dielectric layer; an insulating gate layer of a conductive element array; a second dielectric layer formed on the semiconductor The semiconductor material layer and the protective layer on the bare part; a first metal layer formed on the second dielectric and connected to the conductive layer as the insulating gate half-pole connection channel and For external electrical connection; and a second metal layer formed on the second dielectric layer and connected to the first of the semiconductor material layer as the external electrical property of the insulating gate semiconductor element array For connection. Material and the semiconductor material and provide the insulating layer and the conductive layer of the conductive layer, and as a barrier layer and a gate layer of the array of conductor elements on the conductive layer and the semiconductor material type well and the second type well Source connection, m㈣ 1 ^:, / ^-f quack first read back rain ^-Note ^-items and then fill in the book! ·}-Order _ Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives Insulation gate semiconductors in the scope of application for patent No. 17; approved & π aa element array, the above semiconductor material layer is an epitaxial silicon layer. 〃 :: 1 9. The insulated gate semiconductor according to item 17 of the scope of patent application; # 成 γ sa 7L element array, the first electrical property mentioned in 1 above is N-type, and the second electrical property is p-type. ， 14 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 cm) • Therefore. Α8 Β8 C8 D8 六 、 Applicable patent scope 2 0 · If the patent application scope of the 17th insulation gate The semiconductor device array, wherein the first dielectric layer is a oxidized oxide layer. 2 1. The insulated gate semiconductor element array according to item 17 of the scope of patent application, wherein the above conductive layer is a doped polycrystalline silicon layer. 2 2. The insulated gate semiconductor device array according to item 17 of the application, wherein the second dielectric layer is borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG). 2 3 · If the insulated gate semiconductor element array according to item 17 of the scope of patent application, wherein the above-mentioned first type well and the second type well are located within the unit cell of the insulated gate semiconductor element array and the second metal layer And is connected with the second metal layer as a channel during conduction. 24. The insulated gate semiconductor element array according to item 17 of the scope of the patent application, wherein the first type well and the third type well are located at the edge and the first of the conductive layer outside the unit cell of the insulated gate semiconductor element array. A metal layer is used as a channel for conduction. --------- I-/ .. n I w (Please read the notes on the back before filling out this page), and the paper printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs adopts Chinese national standards (CNS) A4 specification (210X297 mm)