TW390098B - Memory manager for MPEG decoder - Google Patents

Description

Printed by the Consumers' Cooperatives of the Bureau of Decision and Standards of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (1) The field of invention of the present invention relates to video decompression. The present invention relates to a video decoder, and particularly to memory hip management of video frame frames used for video decoding in a video decoder of a video decoder. A variety of video compression standards such as JPEG, MPEG, and H.261 are known in US Patent No. 5,212,742. An important compression ladder is the Moving Picture Expert Convention ('MPEG "), especially MPEG-2 (ISO-IEC 13818). For example, a circuit in a decoder for MPEG-2 encoded video data is described in European Patent Application No. 92306038.8, which is the same as the assignee of the present invention. MPEG editing includes 3 different types of circles: In-System (" I ") (Intra), Prediction (" F ") and Bidirectional Interpolation (" B "). The B-circle image is based on predictions from two-circle images, which are achieved by past and future images, respectively. The I picture does not need to be further decoded by the Temporal Decoder, but it needs to be stored in one of the two picture buffers for later use in decoding P and B pictures. The order of the pictures is modified in the encoder so that I and p pictures can be decoded from the encoded material before the B picture needs to be decoded. The decoded P-circle image needs to form a prediction value from a previous P or I image. The decoded P circle image is stored in the circle image buffer for decoding p and B images. B-pictures require predictions from the circle buffer. The quasi-sphericity of the resolution of a p-ring image's half-pixel (pixel) motion vector requires on-chip interpolation of image information. b The image is not stored in the buffer. The paper size is applicable to the Chinese national standard (('NS) Λ4 specification (210X 297 male — TITI-iAT — — order — — T (锖 Please read the note on the back first) (Please fill in this page again for the matters)) Yin Ju -_ Α7 χ ~~ --- Β7 of the Ministry of Economic Affairs, Central Bureau of Standards and Societies Consumers Cooperatives V. Invention ~ ----Medium 'and it is only a transient image. In mpeg decoding, a time domain and a space allocation deblocker are basically provided. The space allocation decoder used in the present invention performs all required processing in a single image, which reduces redundant operations in an image. Time domain decoding The device reduces redundant operations between a destination image and a circle image that arrives before the destination image arrives, and an image that arrives after the destination circle image arrives. Figure 1 shows how an I image 2 is stored in the image. The buffer 4 is then rotated out. Figure 2 shows how to form a P image 6 from one image buffer 8, store it in a second image buffer 10, and then output it. Figure 3 illustrates How to get a picture I2 from the information structure in the two image buffers 14 and then output it without considering When decoding I and P images, usually these decoding circle images are not output from the time domain demapping device, but I and P images are written into one of the plurality of image buffers. And only It is read only when the next 1 or 1 > circle image arrives for decoupling. In other words, the time domain decoder relies on the next 1 > or I image to clear the previous circle image from the two image buffers. The space allocation scorpion remover can provide a dummy 1 or? Image at the end of the video sequence to clear the last P or I circle image. On the other hand, when the next video sequence starts, clear this dummy image When decoding a B image, a peak memory bandwidth load problem may occur. In this "most soiled" predetermined sample range, two prediction buffers can be applied to obtain all predictions to form a B frame. The watch industry listed the performance capital paper size using a representative dynamic random access memory (" DRAM ") for the Chinese national standard. (CNS > Λ4 specification (210X297 mm) 1 ^ --- τ -------- (Please read the notes on the back before filling this page)

A A7 B7 5. Description of the invention (3). Data pool's width (bits) Read or nest SX 8 squares formation prediction (half pixel accuracy) formation prediction (full pixel accuracy) 8 3657 ns 4907 ns 3963 ns 16 1880 ns 2907 ns 2185 ns 32 991 ns 1907 ns 1741 ns Table 1 V m I In el if n.- 1; (Please read the precautions on the back and fill in this page first.) The seal of the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs can be seen from the information in Table 1. The DRAM interface of the decoder for two accurate half-pixel accurate predictions (via a 32-bit wide interface) requires 381δ ns to read the data. The resolution that can be supported by the time domain decoder is determined by the number of predictions that can be performed in a single image time. In this example, the time-domain decoder can process 8,737 8 × 8 blocks in a single 33ms image period (for example, for 30Hz video). If the required video format is 704 X 480, each | 5 image includes 7920 8X 8 blocks (considering 4: 2: 0 color density sampling). You can see that the video format consumes about 91% of the available DRAM interface bandwidth (before other factors such as DRAM updates are considered). Therefore, the time domain resolver can support this video format. When using MPEG circle image reordering, the worst case scenario samples occur when the P circle image is resolved at the same time. At this time, there are three loads on the DRAM interface: (1) type prediction; (2) writing back the result; and (3) reading the previous P or I image. * ir Λ ... The paper size is suitable for China National Standard Pool. ((, NS) Λ4 size (210 x 297 mm) V. Invention Yiming (4) A7 B7 Printed by the Consumers' Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs Use the data from Table 1 • When a 32-bit wide interface is used, the time required for each task can be determined. The forecast cost is # 1907 ns / n, and the read and write operations are each It takes 991 ns, so it takes a total of 3889 ns. This allows the time-domain decoder to process 8485 8X8 blocks in a period of 33 ms. Therefore, processing 704 X 480 videos requires approximately available memory bandwidth ( Ignore the bandwidth required for re-updating) about 93% of the capacity. Figure 4 shows a block diagram of a conventional decoder system 16. A synchronous DRAM is now generally used as the DRAM 18 in the video formatter 20. »The space allocation decoder 22 and the time domain decoder 24 respectively use DRAM 26, 28. During MPEG decoding, up to 3 aspects can be stored in DRAM 18. DRAM interface 30 is particularly important in achieving acceptable characteristics. In the well-known American Electric According to the NTSC agreement, for the data of 12 million bits in total, 4 million bits per picture are required. For the phase alternate line (" pal ") agreement, the picture The size is about 5 million bits, so I5 million bits of memory are required in DRAM 18. The commercial decoder system is configured with DRAM IS as a 16 million bit random access memory card (" RAM ") The reason is to achieve the need for true effectiveness. However, in the worst case, only one million bits of RAM are kept in other processing functions of the video formatter 20, of course this capacity is not enough. Provide enough The amount of memory results in a "4/3 full save mode" operation ^ g it is necessary to provide another RAM (not shown in the circle) "usually 4 million bits in size can adapt to the video format The device has a capacity of 24.0 million digits, which is larger than the required capacity, but (please read the precautions on the back before filling this page) -9 This paper size is applicable to the Chinese standard (CNS) Λ4 specification (210 X 297 cm) ) Central Standards Bureau of the Ministry of Economic Affairs ______B7 V. Invention description (5) is still using this capacity memory, because when the 16 million bit RAM example, it is an unused component. A super-large integrated circuit (" visi ") In the implemented decoder, it is necessary to reduce the capacity of the memory boat under the general considerations of cost, power consumption and space requirements. The video formatter 20 processes the data from the space allocation decoder 22 and the time domain decoder 24. Process a digital video frame to form a grid of pixels, or pixels. The pixels are 8X8 cube groups, and the cubes are further integrated into 2X2 units, which are called macroblocks. Therefore, a macro block represents a group of 16 x 16 pixels or a group of 2 x 2 blocks. A PAL image is constructed by 45 X 36 macro blocks, and an NTSC image is constructed by 45 X 30 macro blocks. Now refer to Example 5. Each macro block 32 contains four luminance blocks 34 and two chroma blocks 36, and contains information for the original 16x group of pixels. The size of each of the four luminance squares 34 and the two chroma squares 36 is 8 × 8 pixels. The four brightness squares 34 include a mapping of 1 pixel to i pixels from the brightness (Υ) information of the original 1β X I6 group of pixels. One chroma box 36 contains a representation of the chroma level representing the blue color signal (Cu / b) and the other chroma box 36 contains a representation of the chroma level representing the red color signal (Cv / r). Each chroma level is a partial sample, so that each 8X8 chroma square 36 includes the chroma level of the color signal for the entire original 16x16 square pixels. Recently, it has been possible to compress one of the above three pictures (" B picture save ,, ") on Jijie. When this function is executed, it is said to operate the browner in the "2.5 picture storage mode". The reason is because in ((Nor)) 4 specifications (21〇 / 297 mm)! —: ---- XJ—— (Please read the precautions on the back before filling this page)

, 1T V. Description of the invention (6 A7 B7 Printed by the male workers' consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ dram 18 ^ i〇's Dexiong, but in the case of PAL, you need 125 credits worth of samples The important point in real rubber is the ability to decode the PAL circle image in a single 16 yuan memory. However, in the 25-picture storage mode, because the _ algorithm requires the video formatter 20 to process I , P, and the extended mixed sequence in the image, it becomes quite difficult to manage the records. Each type of circle image is individually processed. And if the processing operation to decode a continuous series of images is delayed, then multiple or existing images In this case, it is necessary to go further—the memory management of the stepper encoder. Therefore, the main purpose of the present invention is to improve the efficiency of memory management in a video formatter of an MpEG decoder. An object is to provide a memory manager for an MPEG de-scatterer, which allows fast and efficient operation in a 2.S picture storage mode. The present invention also has an object to enable , The size of the memory unit The cost and power consumption are minimized. In the present invention, the above and other objectives are achieved by providing an improved operation of the MPEG mouthpiece in the 2.5 image storage mode, and an effective memory gift is provided in the child mouthpiece. Management, this management allows to record and display a country image, especially the B-circle image, and at the same time use a part of the remaining memory of the screen. Processing this video is like a grid (" grid "), this The grid has 8 X 8 pixel square rows, hereinafter referred to as "slice" or "block rows". In the mutual coupling buffer, please read the back note & Note

I Side order I Λ This paper size applies to China National Standards (CNS) Λ4 specifications (210X297 mm) A7 B7 Printing by the Central Consumers Bureau of the Ministry of Economic Affairs of the Consumers ’Cooperatives V. Description of the invention (7) Operation of the slice, each color punch The device is configured as a first-in-first-out (FIFO) type * and is connected horizontally in a closed loop. Two operations are performed in a memory hip: (1) video reconstruction processing, which returns the data to the memory hip (...), and (2) a procedure for accessing memory and accessing the video The picture is written into another memory, which is a raster external memory. In the preferred embodiment, there are 3. mutual coupling FIFOs, one FIFO is used for write back operation, and the other two FIFOs are used to read the 2: 1 log back raster data. The two FIFOs for back-grid operation are allocated in the form of alternate lines of images. According to the present invention, a video decoder includes a space allocation solver, a time domain decoder, a video formatter, and a data memory for storing received data. The video formatter receives data from at least one of a time domain decoder and a space allocation decoder. A memory manager for a video formatter, which uses a write-back reference, a first back-gate memory, and a second back-gate memory, in which a finger pointing to the data memory is stored in the write-back memory . The number of positions in the write-back memory volume is less than the sum of the number of positions in the first and second cascade memory hips. A billion-body interface, which is coupled to the first cascade memory, the second cascade memory, the data source, the data memory, and the write-back memory. Provide a write-back control circuit to retrieve the index from the write-back memory. Preferably, the finger ladder is a virtual memory skull indicator, wherein the retrieved finger ladder is presented in the memory card interface, and the received data is stored by Retrieval means the location of the data memory specified by the ladder. The retrieved finger ladder is transferred to the cascade memory. Provide a back-grid control circuit to retrieve the transferred fingers from the back-grid memory boat (锖 Read the precautions on the back before filling this page) -Q.

, 1T. The size of the large paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm). Printed on the A7 B7 by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. The description of the invention (8). Interface, which reads and receives data from the data memory, and restores the retrieved finger ladder to point to the original nest memory | body. It is best to write back the memory «, the first back to the horror and the second Grid-backed memory is FIFO. In one embodiment, these can be configured in a statistical manner and can be implemented by a single RAM. According to another design concept of the present invention, a control circuit can be provided to dynamically form the yttrium. According to another design concept of the present invention, a write-back memory, a first back-gate memory, and a second back-gate memory can be realized as an addressable content memory. According to another design idea of the present invention, the nest can be realized. Memory back .. The skull, the first back-grid memory, and the second back-grid memory ship become a temporary register file. According to another design concept of the present invention, there is a plurality of rows of data memory. Design concept, the aforementioned nested back memory 馥, the first back grid memory 回 and the second back grid memory ship are used to store the finger ladder in the data 嬷 memory's mutual coupling FIFO memory skeleton. Each FIFO memory transmutation has a read The fetching ladder, a writing finger ladder and a status flag ladder, and a control circuit for initializing the FIFO memory «reading finger ladder, writing finger ladder and status flag ladder, of which in a closed system ¥, the The index is transferred between the fossa memory and the back-grid memory. According to one of the design concepts of the present invention, the present invention provides a control paper size that is applicable to the Chinese house standard rate ((: NS) M specification (2 丨 〇χ297). (Public order)-'— (vOrder Λ (please read the notes on the back before filling in this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (9) Road when decoding video block When the video formatter needs to revisit the instruction, the child circuit can determine a lock signal, so that the write fingers of the back-grid FIFO can maintain the state. The invention provides a method for managing a hundred million ships, and the memory is maintained. Decode video data for display. The method is implemented as follows: decoding the MPEG coded data in at least one of the space allocation decoder and the time domain decoder, wherein the decoded data represents an image shown on the cheek; stored in a data memory Decoded video data; store the finger in the position of the data memory in the write-back memory; retrieve the stored finger from the write-back memory; write the received video to the data memory specified by the retrieve finger The retrieved finger ladder is transferred to at least one back-grid memory, where the finger ladder stored in the first back-grid memory corresponds to the video data decoded in the first video display booth, and stored in The second back-grip memory ladder corresponds to the video data decoded in the second video display block; the data is read from the position in the data record Wei, which is specified by the transferred finger ladder; the output read The data is displayed for display; and the transfer finger is restored to the memory including the back grid. Perform the steps of retrieving the pointing ladder and writing the received video data, while transferring the retrieved indicators, reading the data, outputting the read data, and returning the retrieved pointing ladder. In order to allow the reader to further understand the above and other unexplained purposes of the present invention, the following examples explain the details of the actual examples. In the description of the study examples, reference must be made to the circle at the end of the text, where The drawings are as follows: This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) — ^ .- (¾Order ^ • -S Please read the notes on the back before filling out this page) Central Standards of the Ministry of Economic Affairs A7 B7_ printed by the Bureau Cooperative Consumer Cooperative. V. Description of the invention (: 10) Figure 1 is a mpeg " I " image of the decoder used to illustrate the decoder of the present invention; the second series is used to illustrate the decoding of the present invention. The storage of mpeg " P " artifacts of the device; circle three is used to explain the storage of MPEG " B " artifacts of the decoder of the present invention; Figure 4 is a block diagram of the MPEG decoder in the conventional technology; The fifth series shows the block structure of MPEG and JPEG macros in the conventional technology; Figure 6 shows the macro block diagram of the memory card manager in the video formatter of the MPEG decoder of the present invention; Figure 7 shows the memory card management of Figure 6 Circuit diagram of the device; In the memory 濮 manager shown in circle 7, the schematic circuit of the control circuit used to interface with an external memory is shown in Figure 9. Figure 9 shows the detailed circuit diagram of the memory controller in the control circuit shown in Figure 8. Circle 10 is a more detailed schematic circuit diagram of the read-back FIFO controller described by the circuit of circle 9; Figure 11 is a more detailed circuit diagram of the write-back FIFO controller described by the circuit of FIG. 9; The second is a schematic circuit of a further state circuit in the circuit of FIG. 'Now please refer to Figure 6. A video formatter 38 of a VLSI MPEG decoder can receive a given image on line 40 as two de-interlacers. Please read the notes on the back before filling this page) The paper size is applicable to the Chinese standard ((: NS) A * size (2) 0297 mm) A7 B7 V. Description of the invention (11) Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs I nnnnnn I IT n · (Please read the notes on the back before filling out this page) Bitmap images, or single i-side bright images as interlaced data. Please refer to PAL for the description of video formatter 38, because this is the latest image used today Size; however, this protocol can also operate with NTSC, and is suitable for other video protocols. It displays two video segments in two segments, or two fields, one upper stop and one lower Stop. A PAL image arrives at line 40 as a continuous series of macro blocks, and is stored in external memory 馑 42, where the circle image is organized in two square rows for each macro block row. The data can be An interlaced picture image format (ie 45 X 3 6 macro blocks), or arrive in the form of two consecutive de-interlaced blocking artifacts (ie, 2 X 45 X 18 macro blocks). A one-picture macro block includes data from each video viewing block, Data from the two boxes in the upper field and two boxes in the lower field. One field® like a macro box includes 4 blocks of data, all of which are generated by the same block. In order to effectively operate the outside Memory 馑 42, each block storage is divided into memory slices (corresponding to 8 x 8 square rows. Therefore, each slice is a 90 block. A row, each block is generated by the same video block. Now used The largest circle image size is 45 X 36 macro cubes, which corresponds to 90 X 72 cubes. Therefore, in the external memory, each of the stalls in 42 needs to store the data of 36 square rows of data. According to the present invention, three A horizontally coupled FIFO manages the external memory 42. The quick connection of the FIFO is shown in Figure 6. It should be noted that the external memory male 42 is preferably a virtual memory II, but it can also be a physical memory in specific applications. Paper size in Shizhou National Standard (C'NS) Λ4 Specification (2 丨 〇X 297 mm) A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives V. Description of the Invention (12) The external memory ceremony 42 includes two rows, which are the first 〇 bank 〇44 and the first two rows of memory rites can be accessed through the memory ritual interface. The data from the upper position is stored in row 0 to spit. In 44, the data from the lower stop is stored in the first Row bankl46. The first chip (cmchip) FIF0 and nest back FIF050 maintain the virtual finger ladder (hereinafter referred to as “•• finger ladder”) at the free position of the external memory hip 42. The free memory of the external memory 嬷 42 can therefore have video data written in it. The 0th bank addressed by the first indicator at position 52. The first square block row 54 of row 44 and the second square row 58 of the first row bankde addressed by the second finger at position 56 represent each of the 36-row macro blocks stored in external memory 42. Therefore, there are (36 χ 2) finger ladders, and therefore the depth of writing back FIF050 is shown as 72. It is necessary to use a row-shaped external memory boat 42 in combination with a memory interface 48 to maximize the bandwidth during the memory hip operation of the video formatter 38. It should be emphasized that the length of the write-back FIFO 50 is programmable under the control of the microprocessor 60, so that the operation of the memory can be reduced. The other two FIFOs are " back-grid FIFO " or " use memory Body FIFO · _, one of its FIFOs is used for each video block. The cascading FIFO 62 and the cascading FIFO 64 are respectively located in the upper video block and the lower video bit. The aforementioned FIFO maintains the finger ladder value for the hip 42 slices of external memory, and video data has been written in these slices. Each back-grid FIFO 62 and back-grid FIFO 64 maintains up to 54 finger ladders (1.5 x 36 square columns). The reason is to make the finger ladders more obvious. During the operation cycle and before accessing the external memory, start to nest 1 ^ — ^ ----- nm 丨-^ (Please read the precautions on the back before filling this page)

-1T The standard of the paper wave is the Chinese national standard ((: NS) Λ4 specification (210.X297 mm)-+ 3- Α7

V. Description of the invention (13) FIFO 50. Or load the finger ladder into the free slice of the external memory 42. If all 72 slices are used for image storage, write back

I FIFO 50 loads 72 finger ladders. The back-grid type 62 and 64 are cleared, and therefore there is no data in the back-grid FIFO, which means that no data is written for display. The nesting program 66, which is a state machine, starts by retrieving two finger ladders 68, 70 from the write-back fifo 50, and then makes a request to the memory interface "to reach the first two blocks of the sleepy image. There are external memories 42 in positions 72, 74, which are indicated by finger ladders 68 and 70. When two square columns have been stored, write back to program 66 to transfer the two finger beams 68 and 70 to the back grill One or two of the format FIFO62, 64, the procedure is as follows: Love Shen 1: The video data in positions 72, 74 is an interlaced picture image, and a square row includes the upper stop data, and the other square The column includes the bottom stop information. The write back program anvil moves the finger ladder 68 to the position M of the upper-position back-grid FIFO 62, and moves the finger ladder to the position 78 of the lower-position back-grid FIFO 64. Sentiment 2: The video data at positions 72 and 74 indicates a country image and two square rows indicate data for the same booth. If the booth is an upper stop, the two-finger ladders are at positions 76 and Position 80 is placed in the upper shelf back-grid FIFO 62. If the stop is the lower position, a similar process is performed. However, its access is in the lower column back-grid FIF 064. The program processed in parallel with the write-back program 6β is a back-grid program, and its application is similar to the implementation of a state machine. This program is based on the back-grid paper standard Applicable to China National Standard (CNS) Λ4 specification (210X297 mm) I: —Γ --- ίΛ.7 (Please read the note on the back ^ ¢. Before filling this page) Order J "r- Central Ministry of Economic Affairs Standard Printed by the Consumers Cooperative of the Bureau of Economic Affairs of the People ’s Republic of China, printed by the Central Bureau of the Ministry of Economy of the People ’s Republic of China. A7 B7 V. Description of Invention (14)-One of FIFO 62, 64 retrieves a finger ladder. Time is operated on the finger ladder corresponding to a video block, and the data block is continuously accessed until the entire rack is removed from the external memory 42. Assuming an upper rack is required during the show, the back-floor FIFO is used. A finger ladder is retrieved at position 84 in 62. This retrieved finger ladder is used to remove a square row from the external memory 42. After the square row is removed, the grid return program 82 removes the retrieved finger ladder from position 84 Move to position 86 where write-back to fifo 50. Then the back-flip program 82 from the back-flop FIFO 62 Set the next finger ladder at 88, and continue processing in a similar manner until the entire upper screen is taken from the external memory 42. The video data accessed through the memory interface 48 is output on line 90. Write back FIFO 50 and back-grid FIFO 62, 64 are mutually coupled, in which the output of one wheel is fed back into the input of the other as described above. The system is closed, in which the sum of all three FIFO finger ladders at any time It is the number of finger ladders written into the FIFO 50 at the beginning. The reason is that the finger ladders stored in the FIFO provide built-in rate control and anti-clash function. If the write-back FIFO so becomes blank, it is because all available memory / slices are used to hold data. Then, the nesting program 66 cannot retrieve any more data, and stops the operation until the ladder from writing back to the FIFO 50 becomes available. Similarly, when the back-to-back FIFO 62, 64 has taken out all the finger ladders, the back-to-gate program writes back 82 to stop the operation. It is possible to implement nested fIF050 in a single RAM based on a specific video protocol processed by the decoder or a combination of these protocols, and this paper size is the General Chinese National Standard (rNS) Λ4 Specification < 210X297 mm) I — I-: ----- οί ---- ΐτ ------ f (Please read the notes on the back before filling out this page) Printed by A7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs __B7_ V. Description of the invention (15) The back-grid FIFOs 62, 64 are configured in a statistical or dynamic manner. In the preferred embodiment, a total of 180 locations need to be provided in the write-back FIFO 50 and the back-grid FIFO 62, 64, and for convenience, a 192-position RAM can be used for implementation. Since the access to the external memory 42 requires a considerable period of time, such an architecture can obtain satisfactory results, thereby reducing the bandwidth required for writing back to the FIFO 50 and the gated-back FIFO 62 relatively. The dynamic configuration is performed by the control microprocessor 60. By adjusting the order of reading and writing indicators and reading without writing the flag ladder, the FIFO can be displayed as blank, and at the beginning of each B image sequence, write back to FIFO 50 and back to grid FIFO 62, 64 are started. When the B-picture arrives, it is loaded into the FIFO 50, 62, 64 and unloaded in an undecided or unloaded manner. When the B picture sequence is completed and the video formatter 38 moves to the processing of the P picture, the FIFO is frozen in its final state, and can be reloaded or unloaded when the next sequence of the B picture arrives. However, in the preferred embodiment, at the beginning of each B-picture sequence, re-initialization of the write-back FIFO 50 and the back-grid FIFOs 62, 64 is selected to provide more protection against unpredictable errors. It may be necessary to display a block multiple times, for example during a frame rate conversion from a 24Hz moving image film to a 30Hz NTSC (herein referred to as " 3: ' 2 down-frequency operation " (3: 2pulldownoperation)). The back-grid FIFOs 62 and 64 implement reading and writing of finger ladders, and store a copy of the FIFO reading finger ladder at the beginning of the stop reply. When taking out the entire stop from the external memory body 42, the stored reading finger ladder can be used to reset the FIFO reading finger ladder back to the beginning of the stop, thereby making the stop at 1 _ ^ --- ^丨 ----(Please read the notes on the back before filling in this page) The size of the paper is Shizhou China National Standard (CNS) Λ4 Specification (210X297 mm) Central Standards Bureau of the Ministry of Economic Affairs A7 ----------- B7 V. Description of the invention (16) The second access. The backtracking program 82 has to check that the virtual ladder has not been transferred from the backtracking FIFO 62, 64 to Under the condition of returning to FIFO 50, repeated indications will occur. Only when the last access block occurs, the finger ladder is transferred to write back to FIFO 50. Configure FIFO 62, 64 with at least 7 bits of data, The 7-bit data is the maximum number required for the coded 72-block column ladder. In a preferred embodiment, the present invention uses an 8-bit ram for convenience. If the video formatter 38 receives only a single picture Like a sequence of sequences or only a single sequence of stop images, each back-grid FIFO 62, 64 can implement each of 36 locations. Yes, in fact, the other half of the stall storage is used to prevent the memory overflow or overcapacity of the write-back program 66. This is because according to the MPEG protocol, the video formatter 38 must properly handle Regularly mixed picture circle images. In fact, the back-grid program 82 can stop or delay writing by storing the time required for a booth (half of the picture data), hereinafter referred to as " stop time ". Go back to program 66. The emotion that caused the maximum memory load is the next sequence of B images: the previous stop image and the current stop image. In this state, because writing back to program 66 has not been in the previous stop To complete its operation on the B-circle image, for one stop in one booth in the current circle image, storage space must be provided in each of the FIFOs 62 and 64. Assume that regardless of a frame circle image or a double-sided circle image: the entire The video image has been decoded and stored in the external memory 42 without having to acquire any data for display. In this state, the write back to the FIFO 50 is blank, and the paper size applies the Chinese National Standard (C: NS) Λ4 specification ( 210 X 29 " 7 mm) I: --- ^ ---- ^-(ΊI-^ ----- Order ------ Λ (Please read the precautions on the back before filling in this page ) 5. Description of the invention (17 A7 B7 Printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling out this page). Order each back-grid FIFO 62, 64 including 36 finger ladders. The system is still locked until the traverse program 82 is instructed to effectively display a circle of images. Once the program that effectively displays the image is started, the traverse program 82 and the finger ladder transferred to write back to the FIFO 50 are used to make The memory slices in the back-grid FIFOs 62, 64 are released. It is further assumed that the upper-block back-grid FIFO 62 is used, so that the back-block program 82 displays the upper block of the current block circle image, and the next image to be written is a frame circle image. Take out the data from the upper field of the current image, so that 36 squares can be released for writing back to the program 66 using "» Return program 66 and back to gate 82 to operate at about the same rate, so you can These two programs are effectively coupled together. Therefore, these two positions can be displayed when the entire image is stored. But because the field image is obtained in parallel to store a frame image ’, 18 blocks are required for the upper block of the next frame circle image, and 18 blocks are required for the lower block. Because the back-grid program FIFO 62 is left blank by the back-grip program 82, there is enough space for the write-back program 66 to be replaced with a finger ladder that is related to the block above the next screen image. Back-fencing FIF〇62 Medium ° But because the lower back-fencing FIF0 64 has not been accessed, and 36 finger ladders have been included for the bottom-stop of each of the current standing country images, it must be in the back-fencing FIF 〇64 provides enough space to store the 18 finger ladders, which will be under the control of writing back to the program 66 when they decode the next image. Otherwise, writing back to the program 66 will not work, and finally the entire MPEG decoder is loaded. Therefore, in order to provide all possible combinations of the worst sentiment, Fif〇62, 64 need the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Seal A7 -------- 67__ V. Description of Invention (18) " ~ Two: -— 54 finger ladders can be stored (54 = 36 + 18). At a step-up speed of 27 million Hz, a video timing generator (not shown in the circle) drives the backtracking program 82. The write-back program 66 operates at about the same rate and effectively couples itself with the back-gate program 82, so that the finger ladder writes to the write-back FIFO 50 and FIFO 62, 64 at the fastest rate that it can dictate. Providing a solution to the above-mentioned worst-case scenario implies that at any time, writing back FIF0 will not exceed 2/3. Please refer to Figs. 7, 8 and 9 for a schematic diagram of a preferred embodiment of the present invention, in which the present invention is implemented in an integrated circuit. Β is configured in the 192 × 8-bit RAM 94 with the above three mutually coupled printings. Block 96 includes control logic for accessing the RAM 94 and is shown in more detail in FIG. The memory controller 98 accesses the FIFO in the RAM 94 as described above. Blocks 100 and 102 are state machines for the above-mentioned separate nesting procedures and backtracking procedures. The structure of the memory controller 98 is further shown in FIG. The decoding logic network 104 receives its input from the state machines 100, 102, and further decodes the turn information. The circuit 106 includes two double-bit counters 108. This counter generates a four-state output 11 which is a state machine for the RAM controller and is used to determine the access requirements between the write-back and back-grid programs. Therefore, the memory controller 98 can execute the read and write operations by the write back program, and perform the read and write operations by the gate back program according to the state of the output 110. The actual memory accesses performed by the write-back or gate-back routine must therefore wait for the appropriate state of the output 110. For writing back to the FIFO, the FIFO controller 112 is in the same two circuits (for the above and this paper size, the Chinese National Standard (C'NS) A4 specification (2 丨 0'〆297mm) * νλ .- · 丨^; -----— (Please read the notes on the back before filling in this page) Order. Λ ... A7 B7, Seal of the Shellfish Consumption Society, Ministry of Economic Affairs, China V. Description of Invention (19) One "" one ~ next, the FIF controller U4 'lie) of the bit-backed FIFO provides an example of the address expression of three finger ladders for each FIF0. Because the controller needs to provide 72 addresses, a 7-bit bus is connected to the FIFO controller 112. In the example of the FIFO controllers 114 and 116, the bus 118 and the bus 120 connected to it each have 6 bits because the controller only needs to address 54 locations in the back-grid FIFO. The multiplexer circuit 122 decodes the state of the memory controller 98 and the type of memory access it is requesting. The associated fingers from one of the FIFO controllers 112, 114, and 116 are then used to access the RAM 94 (see circle 7). Figure 10 shows the structure of the readback FIFO controller II4, 116. Two 6-bit registers I24, I2β generate separate write and read pointers. The logic associated with the register I26 includes an incrementer 128, a counter 13 and a reverse gate 132, which are used to clear the register I26 when the reading finger reaches its last value. The encounters in the register 136 are similar to the aforementioned register and have the same functions, so for the sake of simplicity, the details are not described here. Use counters 134, 130 to configure the size and access control of one of the back-grid FIFOs 62, 64 (see Figure 6). In some cases, use an additional register 1 to retrieve and maintain the register. The value of 126 will be briefly explained below. Two comparators I38, U0 appear in the battery to compare the values held in the registers 124, 126, 136. The comparator 138 is used to compare the rotation values of the two counting registers I24 ,. The comparator 140 will apply the Chinese National Standard Soap (CNS) Λ4 specification (2〗 〇297 × 297 mm) on this paper scale (please read the precautions on the back before filling this page) I, ^ Order Λ m —I--... The value of the retrieved or maintained read finger ladder stored in the register 136 is compared with the output of the FIFO write finger ladder generated by the register I24. The output of the comparator I38 is shared with the read non-recessed flag ladder, and it is implemented as a single flip-flop 142. Using the gates 144 and U6, two status signals 148 and 15 are generated, indicating that the FIFO is full or blank. The logic network 14 uses these status signals to control the FIFO access mode, and prevents nesting operations when FIF0 is full, and prevents read operations when the FIFO is blank. The output of the comparator 14 is used to generate a " lock " signal NlOck 1S2. When a stop circle image is displayed repeatedly, use the signal n10 (: k152 to control access to the back-grid FIFO. This event occurs when the decoder is executed with a 3: 2 pull-down operation or frame rate conversion. At this time, it is necessary to effectively indicate the time by displaying an additional stop. It is also not necessary to display the two stops of the video image at a time, but to display and repeat the first stop after both stops have been displayed. Method. For example, the first upper block is displayed, then the lower block is displayed, and then the upper block is displayed again. In this case, it is necessary to retain the contents of the external memory hip to display multiple video blocks. In order to make the data in the external horror is not fixed, and once it is displayed, it will be over-written. The lock signal NLOCKI52 freezes the writing finger ladder of the grid FIF0, so that the writing finger ladder It can be reloaded when displayed. When the time in the first column is displayed again, the value captured in the f register I36 is loaded into the register I26. The function of this register is to reload the reading fingers. Set back to the beginning of the first niche so that it can be The second access is performed. The logical network 104 encodes the signal NL0CK 152 as an instruction, which indicates that it is retained in the temporary register I24, printed by A7, B7, and Consumer Cooperatives of the Central Bureau of Economic Affairs. V. Invention It is said that (21) the writing finger ladder is the same as the reading finger ladder retrieved in the register 1 offender, and if the stop will be displayed again, the additional FIFO nesting operation needs to be blocked to prevent the 'first The data booth has been nested. Therefore, the data of the first booth is retained in the external memory card until it is re-displayed for the second time. Now please refer to Figures 6, 8 and 9 in conjunction with the signal NL0CK 152 to operate the signal NWSINK154 »in 3: NWSINK 154 is actuated under 2 pull-down or surface rate conversion, and if the first stop is displayed again, the signal is determined during the first stop display. Signal NWSINK 154 prohibits writing to the write-back FIFO controller 112 The FIFO controller is issued from the backtracking program state device 102. Because when the first image is displayed, the data slice in the external memory must be fixed and returned to the backtracking FIFO 50, so This action is necessary. In the second-* During the display of the bit, or during the display of the first stop, the signal NWSINK 154 does not operate. Therefore, the state machine 102 is allowed to cause a nesting action on the nesting FIFO 50, so that the finger ladder pointing to the blank memory slice can be placed. Figure 11 illustrates the structure of the write-back FIFO controller 112, which is very similar to the read-back FIFO controller, except that the controller has no additional memory to grab the read finger ladder so that It is displayed on the field again. When the first F-type image of a sequence accesses the nested FIF0 first, the flip-flop 1S6 is controlled to simplify the write-back operation. The flip-flop 156 is set and a series of During the display of the first B image in each column B® image, the flip-flops of the flip-flops are activated. This forced state machine logic network 104 (see Figure 9) refers to the real address of the FIFO, instead of retaining it outside the address. IΊ JI — — IQ! ---- Order -----价-(Please read the precautions on the reverse side before filling out this page) This paper is based on the standard of China County ("ns") Λ4% * (2 297 mm) A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 5. Description of the invention (22) The contents of the memory card. The demon should be loaded with the external memory hip containing the image slice sequence in advance for the memory controller 98. The flip-flop 156 is set in the control signal 132. It is not necessary to use a state machine that can clear the external ram, and then load the initial virtual finger ladder into it for the image slice sequence. After the first B image is displayed, reset the flip-flop I56, And it can be set again only when a new B-circle image sequence and sequence is started. Another control flip-flop 158 develops a control signal RASENB 160, which is used by the write-back program to make the write-back program and return Grid program synchronization. Before the start of the B image sequence, the flip-flop 158 is set and written back to the FIFO 50 (see Figure 6). ) Reset the flip-flop when it is blank for the first time. The output of the flip-flop 158 and the control signal FIRSTB 162 indicate when the B artifact should be displayed. It determines when the back-to-back program needs to delay the write-back program. Bit time (or half screen storage). This delay is most suitable for speed state operation. Figure 12 shows the state machine 164 (see circle 7) that controls the access of RAM94. This state machine contains flip-flops 166, 168, 170 And 172, and related logic. Signals 174, 176, and 178 actuate read requests and nesting requests via the back-grip and write-back procedures. In the VLSI configuration used to manage finger ladders, as described above As mentioned above, the FIFO memory can operate in a very good way. However, it is possible to use other memory vessels to manage the configuration to achieve 3 mutually coupled memories. Such a design does not deviate from the spirit of the present invention. Using hash tables, memory / position quick-connect meters, cache memories, and other direct addressing types familiar to those skilled in the art, the fingers will be inserted into three I .—— rI — — IQ! (Please read the back first Please fill in the matters needing attention This page), ιτ This paper scale is applicable to China's national standard U: NS) Λ4 is present (210X297 mm) A7 B7 V. Description of the invention (23) In the mutually coupled memory 馑, retrieve data from it. The other measures are based on the fact that in the write-back program, the 1st order of the index retrieval program basically does not have to be the same as the order of the write-backup memory, as long as the closed system of the finger ladder is maintained can. Now please refer to circle six. From the perspective of circuit power, it is best to implement nested FIFO 50 and gate-backed FlF0 62 and fly 4 as a single port state RAM array, and because it requires a smaller silicon area β, it can also Using the register file, you can also use the content-addressable memory for the three FIFOs. Although the present invention has been described with preferred embodiments, those skilled in the art need to understand that the above embodiments can be modified and changed without departing from the spirit and perspective of the present invention. (Please read the notes on the back before filling out this page} —ο 衣 ---- .. 0 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, this paper is printed on a paper scale that is deducted from the Chinese national standard ((: NS) Λ4 specifications (2) 0X 297 mm)

Claims (1)

87105589 Α8 Β8 C8 D8 Printed by the Central Government Bureau of the Ministry of Economic Affairs of the Industrial and Commercial Cooperatives 6. Application for patent scope 1. A video decoder includes: a space allocation decoder connected to a coded video data source; a 2-domain decoding-; A video formatter that receives data from at least one of the time-domain decoding and space-allocation decoding, wherein the time-domain-free, space-free and space-based distribution decoder defines a data source; one for storing and receiving The data memory of data is characterized by: having a write-back memory, a first back-gate memory, and a second back-to-stone memory, wherein a finger ladder pointing to the data memory is stored in the write-back memory The first back-grid memory and the second back-grid memory; a memory that couples the aforementioned data source, data memory ship, write-back memory, first back-chain memory, and second back-chain memory Interface; a nest control circuit for retrieving the fingers one by one from the write-back memory, wherein the retrieved fingers are presented on the recorder #face, and the received data Stored in the designated In the position of the data memory hip, the previously retrieved finger ladder is transferred to the cascade memory; and, a cascade control circuit is used to retrieve the transferred finger ladder from the cascade memory again to present Give the Yiyi interface, in which the receiving data of the food store is read from the data memory hip, and the retrieving finger ladder is redirected to the nest memory β 2 ′ as described in item 1 of the scope of patent application Video decoder, which refers to <-«L.--'- II-^ w 装 —-, I (Please read the precautions on the back before filling this page) Alignment paper size uses Chinaa Furniture Standard (CNS) A4 Specification (210 > < 297 mm) Male Workers Consumer Cooperatives' Seal, Central Bureau of Economic Affairs, Ministry of Economic Affairs, A8 B8 C8 ___ D8-7T: __ V_ ;: + Electrical Request_Patent Range Building is Virtual Memory The body refers to the ladder. 3. The video decoder according to item 1 of the patent application form *, wherein the fossa memory, the first back-grip memory hip and the second back-grip memory are FIFOs. In the video decoder, the form of the FIFO is set by a statistical method. 5. The video decoder according to item 3 of the scope of patent application, further comprising a control circuit for dynamically configuring the aforementioned FIFO. 6. The video decoder according to item 1 of the scope of the patent application, wherein the number of positions in the nested memory volume is less than the sum of the positions of the second-cascaded memory and the f-three-cascaded memory. 7. A video decoder includes: a space allocation decoder connected to the encoded video data source; a time domain disc decoder; and a receiver that receives data from at least one of the time domain decoder and the space allocation decoder. A video formatter, in which the time-domain decoder and the space-allocation decoder define a data source; a data memory for storing the received data; its characteristics are: a closed memory system including a mutual coupling FIFO memory to The finger ladder stored in the data memory, the FIFO memory is a write-back memory, a first back-grid memory and a second back-grid memory, each of the aforementioned FIFO memory vessels has a read finger ladder, a Write the finger ladder and a state flag ladder; 26 This paper method scale uses China National Standard Liang (CNS) A4 (210X297 mm) ~ ~ < Please read the precautions on the back before filling in this page) Installation · K4 A8 B8 C8 D8 Printed by the Central Consumer Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives «. Used to initialize the FIFO memory, the read ladder, the write finger and the state flag ladder control circuit; The memory hip interface of the memorizer, the first back-grid memory and the second back-grid memory; a write-back control circuit for retrieving the finger ladder from the write-back memory, wherein the memory interface The returned finger ladder is presented, and the received data is stored in the position of the data memory designated by the aforementioned finger ladder, and the retrieved finger ladder is transferred to the child's back gate memory; and a back gate control circuit, For retrieving the transferred finger ladder from the back-memory hip to present to the memory interface, wherein the stored received data is read from the data memory bank, and the re-fetching finger ladder weight Back to the nest back to memory 馥. 8. The video decoder according to item 7 of the patent application, further comprising a first control circuit for dynamically storing at least one memory capacity in the aforementioned FIFO memory vessel. 9. The video decoder described in item 7 of the patent application park further includes a control unit. When a decoded video block needs to be displayed by the video and formatter, this second control circuit can A lock signal is determined, wherein the write fingers of the back-grid FIFO are maintained in a stable state to respond to the lock signal. 10. —A method for managing a memory in a video decoder system having a space allocation decoder, a time domain decoder, and a video formatter. The memory retains decoded video data for display, ( Please read the note on the back before filling this page) ▼ Packing_ U 27 This paper size is in accordance with China National Standard (CNS) A4 size (210X297 male sauce) Printed by A8 Consumers Cooperative of Central Escalation Bureau of Ministry of Economy and Trade B8 C8 I-_ D8 VI. Patent application scope This method includes the following steps: Decoding MFEG encoded video data in at least one of the space allocation decoder and the time-domain decoder, where the decoded data represents a Will display the circle image; provide a data memory for the decoded video data; store an indicator pointing to the location of the data memory in the write memory; retrieve the stored finger ladder from a nest of memory; The received video data is nested in the position of the data memory, and the position of the data memory of the child is designated by the retrieved finger ladder; the retrieved finger ladder is transferred to the first back gate memory boat and the second outline In at least one of the memorable bodies, the first time memory of the food exists in the "Finger ladder" corresponds to the scorpion video data in the first message display field, and the food exists in the second time memory finger ladder Decode the video data corresponding to the second video surveillance stop; read the data from the bit of the data memory presumed by the transfer finger; set the output of the read data to indicate the data; and make the transfer The finger ladder returned to the nest and recorded billions of bodies. (Please read the precautions on the back before filling out this page} h -Packing--Order-Thread-