經^‘部中决榡卑局MJ-消fr合作社印裝 3484twf.doc/008 A7 __B7_ 一 五、發明説明（丨） 本發明是有關於一種增加化學機械硏磨均勻度的方 法，且特別是有關於一種採用虛置圖案(Dummy Pattern)增 加化學機械硏磨均勻度的方法。 化學機械硏磨法（Chemical Mechanical Polishing，CMP) 是目前唯一能提供超大型積體電路（Very Large Scale Integration, VLSI)，甚至極大型積體電路（Ultra Large Scale Integration，ULSI)製程中，全面平坦化（Global Planarization) 的一種技術。因爲此項技術極可能成爲半導體業者在大幅 降低積體電路圖案尺寸(Feature Size)的競爭中，所必須仰 賴的平坦化製程，因此相關業者莫不傾全力開發此項技 術，以提高本身的競爭優勢。 當半導體製程技術進入線寬達〇.25ym或甚至0.18// m的深次微米(Deep Sub-Half Micron)技術時，使用化學機 械硏磨法作爲晶片表面平坦化的處理技術，尤其是在處理 淺溝渠表面氧化層的平坦時，已經是愈來愈重要。習知的 淺溝渠隔離製程無法在元件間距太大的區域達到全面平坦 化的要求，因爲習知利用化學機械硏磨法進行晶片表面平 坦化的過程中，如果在基底的圖案有元件間距超過l〇"m 以上，硏磨後會在此區域產生碟形凹陷，而無法達到全面 平坦化的要求。 第1A圖至第1D圖所示，爲傳統利用化學機械硏磨法 的淺溝渠隔離製程剖面圖。 請參照第1A圖，在一半導體基底1〇〇表面形成一墊 氧化層101，接著形成一介電層102覆蓋在墊氧化層101 3 本紙張尺度適甭中國國家標淨(_(〕NS ) Λ4規格（ 210X297公釐) '~~ ' (諳先閲讀背面之注意事項再填寫本頁) •η裝. 訂 怒溁部中决標率局貝T;消於合作社印來 3484twf.doc/008 A7 _ B7 * 五、發明説明（>) 上，比如是一氮化矽層，隨後上光阻並以光學微影和蝕刻 技術形成元件區103，再利用此元件區上的光阻（未顯示) 爲罩幕，在基底100上以非等向性蝕刻製程蝕刻一定的深 度而形成複數個溝渠。 請參照第1B圖，在該基底100表面利用化學氣相沈 積法（Chemical Vapor Deposition, CVD)沈積一氧化層 104，接著，利用化學機械硏磨法硏磨氧化層104並以第 一介電層102之表面爲硏磨終止層，而形成複數個溝渠隔 離區105，106，如第1C圖所75。 接著，請參照第1D圖，去掉元件區介電層的殘留部 份，而在基底100表面形成閘氧化層107及多晶矽層108， 完成淺溝渠隔離製程。 然而，並非每一個溝渠隔離區尺寸都相同，如第ic 圖所示，溝渠隔離區106就比溝渠隔離區105大，於是， 在化學機械硏磨製程中，多晶矽層108塡充於溝渠隔離區 105的部份就可得到相當平坦的表面，而塡充於溝渠隔離 區106的部份則呈現一平緩下凹的表面。 因此，在習知的淺溝渠隔離製程中，採用虛置圖案結 合化學機械硏磨法的製程，在尺寸較大的淺溝渠隔離區域 放置虛置圖案，作爲化學機械硏磨時的阻擋層，藉以避免 因溝渠隔離區面積大小差異而產生凹陷現象，增加硏磨時 的均勻度。 但是，由於同一晶片上各種電路區域的主動區域疏密 程度不一致，單純地在各主動區域尺寸較大的淺溝渠隔離 4 本紙張尺度14用中國國家標率((:NS ) Λ4規格（210X297公釐) ' (請先閲讀背面之注意事項再填寫本頁) ο裝. -政· 麪满部+决標绛局努·τ·消费合作社印聚 3484twf.doc/008 A7 B7 — 五、發明説明（$ ) 區域放置虛置圖案，只能略爲調整主動區域密度分佈的差 異，因主動區域可能有多種密度，因此以習知的方法，仍 無法有效地控制化學機械硏磨製程的均勻度，尤其是在記 憶體產品，如：SRAM、DRAM等產品上。 有鑑於此，本發明提供了一種依各電路區域的主動區 域密度與分佈比例放置虛置圖案的方法，採用平衡各電路 區域的主動區域密度及分佈比例的方式來放置虛置圖案， 使同一晶片上整體的主動區域密度及分佈一致，達到降低 化學機械硏磨製程之負載效應，提高均勻度的目的。 根據本發明的上述及其他目的，提出一種增加化學機 械硏磨均勻度的方法，在淺溝渠隔離製程中，利用程式分 析的方法，依不同的電路特性如記憶體電路或是週邊電 路，作各電路區域的主動區域密度及分佈比例計算，再以 密度最高的電路區域爲基準，分別在各電路區域上設計不 同密度的虛置圖案，以調整個主動區域的密度，使同一晶 片上整體的主動區域密度及分佈一致，達到降低化學機械 硏磨製程造成的負載效應，提高製程的均勻度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： ％ 第1A圖至第1D圖係習知形成淺溝渠隔離結構之製 造流程剖面圖；以及 第2A圖至第2E圖繪示爲本發明一較佳實施例，放置 5 本紙张尺度過用中國國家標爷（（、奶）六4規格（210\297公釐） 【 , --------------IT------d. J - (請先閱讀背面之注意事項再填寫本頁) 3484twf.doc/008 A7 B7 五、發明説明（仏） 虛置圖案之淺溝渠隔離結構之製造流程剖面圖。 圖式之標記說明： 1Q0, 200 :半導體基底 101，201 :墊氧化層 102, 202 :介電層 103, 203 :元件區 104, 207 :氧化層 204, 205, 205a，205b :溝渠 105, 106, 208, 209a，209b :溝渠隔離區 206 :虛置圖案 107, 210 :閘氧化層 108, 211 :多晶砍層 實施例 第2A圖至第2E圖所示，爲根據本發明一較佳實施例 之淺溝渠隔離結構製造方法流程剖面圖。 請參照第2A圖，在一半導體基底200表面形成一楚 氧化層201，接著形成一介電層202覆蓋在墊氧化層加1 之上，其材質比如是氮化矽，隨後上光阻’並以光學微影 和蝕刻技術定義介電層202，以形成元件區203，再利用 此元件區上的光阻(未顯示)爲罩幕，在基底200上以非等 向性蝕刻製程蝕刻一定的深度而形成複數個溝渠。該複數 個溝渠尺寸並不相同，如圖所示，溝渠205的尺寸比溝渠 204 大。 接著，請參照第2B圖，爲避免習知淺溝渠隔離製程 (铕先聞讀背面之注意事項再填寫本頁)The Ministry of Justice and the Ministry of Justice, MJ-Fr Cooperative, printed 3484twf.doc / 008 A7 __B7_ One, five, the description of the invention (丨) The present invention relates to a method to increase the uniformity of chemical mechanical honing, and in particular The invention relates to a method for increasing the uniformity of chemical mechanical honing by using a dummy pattern. Chemical Mechanical Polishing (CMP) is currently the only method that can provide very large integrated circuits (VLSI), or even Ultra Large Scale Integration (ULSI) processes. A technology of Global Planarization. Because this technology is likely to become a flattening process that semiconductor industry must rely on to significantly reduce the feature size of the integrated circuit, the relevant industry is committed to developing this technology to improve its own competitive advantage. . When semiconductor process technology enters deep sub-half micron technology with a line width of 0.25 μm or even 0.18 // m, chemical mechanical honing is used as a processing technology for wafer surface planarization, especially in processing When the oxide layer on the surface of a shallow trench is flat, it becomes more and more important. The conventional shallow trench isolation process cannot meet the requirement of comprehensive planarization in areas with a large element pitch, because during the process of planarizing a wafer surface by a conventional chemical mechanical honing method, if there is a component pitch in the pattern of the substrate exceeding l 〇 " m and above, after honing, dish-shaped depressions will be generated in this area, which cannot meet the requirements of overall planarization. Figures 1A to 1D are cross-sectional views of a conventional shallow trench isolation process using chemical mechanical honing. Referring to FIG. 1A, a pad oxide layer 101 is formed on the surface of a semiconductor substrate 100, and then a dielectric layer 102 is formed to cover the pad oxide layer 101. This paper is suitable for China National Standard (_ () NS) Λ4 specification (210X297mm) '~~' (谙 Please read the precautions on the back before filling this page) • η installed. Order the final bid rate in the Ministry of Commerce; disappeared in the cooperative printed 3484twf.doc / 008 A7 _ B7 * 5. In the description of the invention (>), for example, a silicon nitride layer, followed by photoresist and forming the element region 103 by optical lithography and etching technology, and then use the photoresist on this element region (not (Shown) is a mask, and a plurality of trenches are formed by etching a certain depth on the substrate 100 using an anisotropic etching process. Referring to FIG. 1B, a chemical vapor deposition method (Chemical Vapor Deposition, CVD) is formed on the surface of the substrate 100. ) An oxide layer 104 is deposited. Then, the oxide layer 104 is honed by a chemical mechanical honing method and the surface of the first dielectric layer 102 is used as a honing stop layer to form a plurality of trench isolation regions 105, 106, as shown in Section 1C Figure 75. Next, referring to Figure 1D, remove the dielectric layer in the device area. Residues, and a gate oxide layer 107 and a polycrystalline silicon layer 108 are formed on the surface of the substrate 100 to complete the shallow trench isolation process. However, not every trench isolation area is the same size. As shown in FIG. The trench isolation area 105 is large. Therefore, in the chemical mechanical honing process, a portion of the polycrystalline silicon layer 108 filled in the trench isolation area 105 can obtain a fairly flat surface, while a portion filled in the trench isolation area 106 appears. A gently concave surface. Therefore, in the conventional shallow trench isolation process, a dummy pattern combined with a chemical mechanical honing process is used to place a dummy pattern in a larger shallow trench isolation area as a chemical mechanical 硏The barrier layer during grinding, in order to avoid the depression caused by the difference in the area of the trench isolation area, increases the uniformity during honing. However, due to the inconsistency of the active area density of various circuit areas on the same wafer, the Shallow ditch isolation with larger area size 4 This paper size 14 uses the Chinese national standard ((: NS) Λ4 size (210X297 mm) '(Please read the back first (Please fill in this page before filling in this page) ο Install. -Policy, full face + final bids, bureau, τ · consumer cooperative print 3484twf.doc / 008 A7 B7 — V. Description of invention ($) The area is left blank The pattern can only slightly adjust the difference in the density distribution of the active area. Because the active area may have multiple densities, the uniformity of the chemical mechanical honing process cannot be effectively controlled by conventional methods, especially in memory products. Such as: SRAM, DRAM, etc. In view of this, the present invention provides a method for placing dummy patterns according to the active area density and distribution ratio of each circuit area, using a method of balancing the active area density and distribution ratio of each circuit area. The dummy pattern is placed to make the overall active area density and distribution on the same wafer uniform, so as to reduce the load effect of the chemical mechanical honing process and improve the uniformity. According to the above and other objects of the present invention, a method for increasing the uniformity of chemical mechanical honing is proposed. In the shallow trench isolation process, a program analysis method is used to make various changes according to different circuit characteristics such as a memory circuit or a peripheral circuit. Calculate the active area density and distribution ratio of the circuit area, and then use the circuit area with the highest density as the reference, and design dummy patterns with different densities on each circuit area to adjust the density of each active area to make the overall active on the same chip The area density and distribution are consistent, so as to reduce the load effect caused by the chemical mechanical honing process and improve the uniformity of the process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings:% 1A Figures 1 to 1D are cross-sectional views of a conventional manufacturing process for forming a shallow trench isolation structure; and Figures 2A to 2E show a preferred embodiment of the present invention. Five paper sizes are placed using the Chinese National Standard Master ( (, Milk) 6 4 specifications (210 \ 297 mm) [, -------------- IT ------ d. J-(Please read the precautions on the back before (Fill in this page) 3484twf.doc / 008 A7 B7 V. Description of the invention (仏) Cross-sectional view of the manufacturing process of the shallow trench isolation structure with a dummy pattern. Marking description of the drawings: 1Q0, 200: semiconductor substrate 101, 201: pad oxidation Layers 102, 202: dielectric layers 103, 203: element regions 104, 207: oxide layers 204, 205, 205a, 205b: trenches 105, 106, 208, 209a, 209b: trench isolation regions 206: dummy patterns 107, 210 : Gate oxide layers 108, 211: Polycrystalline cutting layer embodiment, as shown in FIGS. 2A to 2E, are shallow trench isolations according to a preferred embodiment of the present invention. A cross-sectional view of the structure manufacturing method process. Please refer to FIG. 2A, a oxide layer 201 is formed on the surface of a semiconductor substrate 200, and then a dielectric layer 202 is formed to cover the pad oxide layer plus 1. The material is, for example, silicon nitride. Then, a photoresist is applied, and the dielectric layer 202 is defined by optical lithography and etching techniques to form a device region 203. The photoresist (not shown) on this device region is used as a mask, and the substrate 200 is non-equal. The directional etching process etches a certain depth to form a plurality of trenches. The dimensions of the plurality of trenches are not the same. As shown in the figure, the size of the trench 205 is larger than the trench 204. Next, please refer to FIG. 2B. Ditch Isolation Process (Please read the notes on the back before filling this page)
鳑请-部中央梂準局iacJ.消費合竹社印^. 本紙張尺度读用中囷國家標肀（CNS ) A4規格（2丨〇><297公嫠） 3484twf.d〇c/008 A 7 __B7_____一 五、發明说明（f) 產生的凹陷現象，在尺寸較大的溝渠205放置虛置圖案 206，形成尺寸較小的溝渠205a，205b。因爲同一晶片上的 主動區域密度及分佈比例不一致，單純地在各主動區域尺 寸較大的淺溝渠區域放置虛置圖案，仍不易控制化學機械 硏磨製程的均勻度。因此，虛置圖案206的形成是由程式 分析得到的結果，使用電腦程式依照晶片上各種電路區域 不同的特性，如記憶體電路區域及周邊電路區域，計算各 種電路區域的主動區域密度及分佈比例，以密度最高的區 域爲基準，分別放置虛置圖案於密度較低的區域，使同一 晶片上的各電路區域的主動區域密度及分佈趨於一致。 接著，請參照第2C圖，在該基底200的表面形成一 氧化層207，其形成的方法包括化學氣相沈積法。接著， 利用化學機械硏磨法硏磨氧化層207，並以第一介電層202 之表面爲硏磨終止層，而形成複數個溝渠隔離區208, 209a 及209b，如第2D圖所示。 接著，請參照第2E圖，去掉元件區介電層203的殘 留部份，然後在基底200的表面依序形成閘氧化層210及 多晶矽層211，完成淺溝渠隔離製程。 經濟部十次標準灼貞J-消费合竹社印絮 (請先閲讀背面之注意事θ填寫本頁) ,Μ. 請同時參照第1D圖及第2E圖，第1D圖中的溝渠隔 離區106尺寸比溝渠隔離區105大，在化學機械硏磨製程 中，多晶矽層108塡充於溝渠隔離區1〇6的部份呈現一平 緩下凹的表面，塡充於溝渠隔離區1〇5 ^部份則可得到相 當平坦的表面。而第2E圖中，因爲使用虛置圖案，溝渠 隔離區208, 209a及209b的尺寸相近，多晶矽層211塡充 7 本紙張I度適h中國國家榡哗（（’NS ) Λ4規格Y210X297公梦) —' 3484twf.doc/008 A7 B7_____^ 五、發明説明（〈） 溝渠隔離區208, 209a及209b所得的平面相當平坦。 本發明除了應用於一記憶體電路區域及一周邊電路區 域之情形外，還可應用於兩個電路區域以上的情形’如一 記億體電路區域、一第一周邊電路區域及一第二周邊電路 區域。 本發明具有下列優點： 1. 利用虛置圖案放置於尺寸較大的溝渠，避免習知淺 溝渠隔離製程產生的凹陷現象。 2. 根據晶片上各種電路的不同特性，如記憶體電路及 周邊電路，使用程式分析的方法計算各種電路的主動區域 密度及分佈，以密度最高的電路區域爲基準，設計虛置圖 案調整密度較低的電路區域，可準確的使同一晶片上各主 動區域的疏密程度達到一致，達到降低化學機械硏磨製程 造成的負載效應，提高製程的均勻度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁)鳑 Please-Ministry of Standards and Technology Bureau iacJ. Printing by Consumption Co., Ltd. ^. This paper is read in Chinese National Standard (CNS) A4 Specification (2 丨 〇 > < 297 Gong) 3484twf.d〇c / 008 A 7 __B7_____15. Description of the invention (f) The pits generated by placing dummy patterns 206 in the trenches 205 with larger sizes to form trenches 205a and 205b with smaller sizes. Because the density and distribution ratio of active areas on the same wafer are inconsistent, it is still difficult to control the uniformity of the chemical mechanical honing process simply by placing dummy patterns in the shallow trench areas with larger active area sizes. Therefore, the formation of the dummy pattern 206 is a result of program analysis. A computer program is used to calculate the active area density and distribution ratio of various circuit areas according to different characteristics of various circuit areas on the chip, such as memory circuit areas and peripheral circuit areas. Based on the area with the highest density, the dummy patterns are placed in the areas with lower density, respectively, so that the density and distribution of the active areas of each circuit area on the same wafer tend to be consistent. Next, referring to FIG. 2C, an oxide layer 207 is formed on the surface of the substrate 200. A method for forming the oxide layer 207 includes a chemical vapor deposition method. Next, the oxide layer 207 is honed by a chemical mechanical honing method, and a plurality of trench isolation regions 208, 209a, and 209b are formed using the surface of the first dielectric layer 202 as a honing stop layer, as shown in FIG. 2D. Next, referring to FIG. 2E, the remaining portion of the dielectric layer 203 in the device region is removed, and then a gate oxide layer 210 and a polycrystalline silicon layer 211 are sequentially formed on the surface of the substrate 200 to complete the shallow trench isolation process. The tenth standard of the Ministry of Economic Affairs, J-Consumer Hezhu Club Printing (please read the notes on the back θ to complete this page), M. Please refer to Figure 1D and Figure 2E, and the ditch isolation area in Figure 1D at the same time. The size of 106 is larger than that of the trench isolation region 105. In the chemical mechanical honing process, the portion of the polycrystalline silicon layer 108 that fills the trench isolation region 106 presents a gently concave surface, which fills the trench isolation region 105. ^ Partially a fairly flat surface is obtained. In Figure 2E, due to the use of dummy patterns, the trench isolation areas 208, 209a, and 209b are similar in size, and the polycrystalline silicon layer 211 is filled with 7 sheets of paper. The degree of Chinese paper is suitable for China (('NS) Λ4 size Y210X297). ) — '3484twf.doc / 008 A7 B7 _____ ^ 5. Description of the invention (<) The planes obtained by the trench isolation areas 208, 209a and 209b are quite flat. In addition to the case of a memory circuit area and a peripheral circuit area, the present invention can also be applied to a situation of more than two circuit areas, such as a billion circuit area, a first peripheral circuit area, and a second peripheral circuit. region. The invention has the following advantages: 1. The dummy pattern is used to place the trench with a large size to avoid the depression phenomenon caused by the conventional shallow trench isolation process. 2. According to the different characteristics of various circuits on the chip, such as memory circuits and peripheral circuits, use program analysis to calculate the density and distribution of the active area of various circuits. Based on the highest density circuit area, design a dummy pattern to adjust the density. The low circuit area can accurately make the density of the active areas on the same wafer uniform, reduce the load effect caused by the chemical mechanical honing process, and improve the uniformity of the process. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
—1T -織. 經Μ部中决#準局ΚΧ-1·消於合竹社印絮 8 本紙張尺度適/<1中國医家標冷(（'奶>八4^(210><297公嫠>—1T -woven. Economical Department of the Ministry # 中 局 ΚΧ-1 · Xiao Yuhezhu Printing Co., Ltd. 8 This paper is of a suitable size / < 1 Chinese medical standard cold (('Milk > Eight 4 ^ (210 > <; 297 Gong >