TW385529B - Making process for forming self-alignment contact plug useful in an embedded random access memory - Google Patents

Abstract

This present invention is disclosed to a making process for forming self-alignment contact plug, which comprises the following steps: providing a base substrate formed with semiconductor component; forming an insulating layer onto the base substrate and defining a self-alignment contact window thereon; proceeding a dopant implanted process to have the dopant through self-alignment contact window be entered into the base substrate and be formed a diffusion region thereon; forming a high temperature doped polysilicon layer with suitability to be covered on the surface of insulating layer and the inner wall and bottom of self-alignment contact window; forming a low temperature doped polysilicon on the high temperature doped polysilicon and the self-alignment contact window is then filled ; and proceeding a planarization process, in sequence removing the redundant low temperature doped polysilicon and high temperature doped polysilicon up to the insulating layer, and forming a plug in the self-alignment contact window connected to semiconductor component.

Description

V. Description of the invention (i) The present invention relates to an automatic and in particular to a plug-in process of a quasi-contact type = quasi-contact window, and a quasi-contact window inspection process. The automatic pairing of dynamic random access memory is mainly in the half: dj :: d :, (sac Plus) process, its shadow technology is predetermined; ί into-conductive plugs, which can be automatically aligned with the contact opening, Be clear. Slot ". Chu can see 'will be described in detail in the _ ~ 1D drawing: please refer to Figure 18' provided-semiconductor substrate 100, its upper gates 110, 120, and insulation sidewalls L and source / liquid f Diodes 130a, UOb, and 13c are composed of transistors. and j 'Please refer to the figure' to form an insulating layer 14 on the soil shown in Figure u, 100 surface, and then use the lithography process and The etching technology defines an automatic alignment contact opening at a predetermined position. 5 〇 Then, 'Please refer to Figure 1C, at a temperature of about 540 ~ 600. (In the furnace', a polycrystalline silicon layer doped with impurities is formed.丨 60 is on the insulating layer 丨 4, and the groove is filled with the automatic alignment contact opening 丨 50. Among them, the impurity in the polycrystalline silicon layer 丨 60 may be N-type impurities such as phosphorus or arsenic, or p In addition, before forming the polycrystalline silicon layer 160, an impurity implantation treatment step may be applied so that the impurities can enter the substrate through the auto-aligned contact opening to form an impurity diffusion region (not shown). Adjust the concentration of impurities at the interface of the contact opening. The types of impurities used in it and the energy and dose when they are planted As needed to select.

C: \ ProgramFiles \ Patent \ 0503-4019-E.ptd page 5 'Instructions of the invention (2) Finally, please refer to circle 1D, and use the etch-back method to remove the excess polycrystalline silicon layer. Mechanical grinding, a plug is formed in the quasi-contact opening 15o: Γ80 · = electrode, or bit line. In addition, because of the Logic Dream of the dynamic random access memory, the devices are formed on different chips, and then they are set up. However, because they are formed in different names, The hidden device is set at high speed, so there is a kind of memory element; =; = ^ and I placed on the same chip, the hidden body is proposed, ^ gp. &Quot; ^ f-type memory, such as embedded Dynamic random access memory ("bedded andom Access Memory". Figures 2A to 2D show the benefits: the plug-in process described in Figures 1A to 1D, to control the borrowed memory access part First, please refer to FIG. 2A to provide a semiconductor substrate 200, which can be divided into a cell area ready to form a memory element and a peripheral circuit area containing a logic element. The 'cell area is formed by The gates 21 and 22, and the insulating sidewalls 225 'and the source / drain diffusion regions 23a, 23b, and 230c are composed of transistors; the peripheral circuit region is formed with a diffusion region 23d, And a shallow trench isolation (240) for isolation. Please refer to FIG. 2B, first form an insulating layer 140 on the substrate 200 surface of the cell area and peripheral circuit area shown in FIG. 2A, and then make a reservation in the cell area and peripheral circuit area by lithography and etching technology. The positions respectively define an automatic alignment contact opening 25 5 and 260. Next, please refer to FIG. 2C, at a temperature of about 5 40 ~ 600.

C: \ ProgramFiles \ Patent \ 0503-4019-E.ptd page 5 --- 5. Description of the invention (3) In the formation step, the impurities in the trench filling system can be outside, and the impurity-impurity diffusion step is formed. degree. Among them, it is necessary to select the final method to remove the extra alignment contact device as the cell bit line. However, the leakage of the contact and the interface has therefore developed a plug making process which is a process of the present invention. It is an insulation layer and an impurity is doped in the substrate. Filling in the characteristic steps is included in the foundation planting step and covers the bottom; the internal formation is not satisfactory and urgent. It is revealed that the bottom surface is provided so that an expanded insulating layer is formed to form a polycrystalline silicon layer 2 70 doped with impurities on the insulating layer 1 40 and aligned with the contact openings 2 5 5 and 2 60. The polycrystalline silicon layer 270 is an N-type impurity such as phosphorus or arsenic, or a P-type impurity such as boron. This polycrystalline stone layer can be applied with an impurity implantation treatment step before 160. It can enter the substrate by automatically aligning the contact opening, and form a region (not shown) for adjusting the concentration of impurities on the contact opening. The types of impurities, and the energy and dose during implantation can be seen. Please refer to Figure 2D, "Multi-crystalline silicon layer 1 60 using etch-back or chemical mechanical polishing" until the insulating layer 14, at the automatic ports 2 5 5 and 2 6 Do not form a plug 2 0 0 and 2 9 0 to pre-lower electrodes or the d-polycrystalline silicon layer in the peripheral circuit area. The contact resistance (Rc) of the sub-micron device is sufficient. A plug that forms a self-aligned contact window that provides low contact resistance and interface leakage forms a substrate on which a semiconductor element is formed; a self-aligned contact window is defined; impurities can enter through the self-aligned contact window Region; forming 1—high temperature doped polycrystalline spar surface and the low temperature doped polycrystalline silicon layer of the self-aligned contact window at the high temperature doped

V. Description of the invention (4) The hetero-polycrystalline silicon layer is trenched and sequentially removed, and the self-aligned contact window is sequentially removed; and the doping of the poly-crystalline silicon layer to the insulation is performed by temperature-temperature: silicon layer And the high internal formation-connect the semiconductor! ; = Bolt-aligned contact opening process; ☆: Plunger f: where the insulating layer can be a general semiconductor using chemical vapor phase method: oxygen: silicon layer; high temperature doped polycrystalline silicon layer impurity system Wall… doped at 120 ℃ atoms / cm3 in the doped polycrystalline stone layer at high temperature; formed in a γ furnace, the thickness of which is the impurity system 4 in the stone layer, its impurity concentration is -2, and in addition, " The material's energy is 5 X 10 at 0ms / cm2 in the implanting agent; and the planarization treatment can be completed by chemical mechanical polishing or etch-back. 'Another feature of the present invention is to disclose a plug-in system of an embedded movable auto-alignment contact window, the steps of which include a cell area and a peripheral circuit area on the substrate, and respectively In the cell area and the J side, a self-aligned contact window is generated; an impurity doping step is applied so that the self-aligned contact window in the cell area and the peripheral circuit area can not be entered into the substrate, And forming a diffusion region; forming a w-layer covering the surface of the insulating layer, and the inner wall and bottom of the counterpart; forming a low-temperature-doped polycrystalline silicon layer at the height =

V. Description of the invention (5) ~-Self-aligned contact windows doped on the Fuming silicon layer and filled with the cell area and the peripheral circuit area respectively; and a flattening process is performed to sequentially remove the excess low-temperature dopant. The hetero-multi-crystalline silicon layer and the high-temperature-doped poly-crystalline silicon layer to the insulating plug process as described above, wherein the insulating layer may be an oxide layer commonly used in semiconductor processes, such as a silicon oxide layer; Silicon layer system. It is formed by a chemical vapor deposition method, and the formation temperature is about 620 to 680 ° C, and the thickness is about 35 to 750 angstroms, and the I-based scales are mixed in a high-temperature-doped polycrystalline silicon layer. Among them, the impurity concentration in the second layer of the South temperature-changing complex crystal is about 100 ohms / cm3; the low-temperature-doped polycrystalline silicon layer is formed in a furnace with a temperature of about 54 to 600 C, and its thickness is about 35. 0 ~ 4500 angstroms. In addition, the impurity-based phosphorus in the polycrystalline silicon layer is doped at a low temperature, and the impurity concentration thereof is about 1020 atoms / cm3. In addition, in the impurity doping step, the implantation energy of the impurity is 40 keV ′ and the implantation dose thereof is 5 X 1 〇uat〇ms / cm2; and the planarization treatment system may use the chemical mechanical polishing method or the back-etching method carry out. In order to make the advantages and features of the present invention more clearly visible, the preferred embodiments of the present invention will be described in detail below with reference to the related drawings. Brief description of the drawings: Figures 1A ~ 1D show a kind of conventional automatic control and control you „τ + Reminder of the contact opening Figure 2A ～ 2D show a kind of conventional funnel type dynamic random memory The process of automatically aligning the contact opening with the plug. Figures 3A to 3D of the auto-aligning contact opening show the self-plugging process according to the present invention.

C: \ Program Files \ patent \ 〇5〇3-4019-E.ptd page 8

Figures 4A to 4D show the automatic alignment of the contact openings based on the fetching of memory. Example 1: The embedded dynamic random storage of the present invention: the manufacturing process. Please refer to FIG. 38 to provide a semiconductor substrate 300, 1 formed with gate electrodes 310, 32, insulating sidewalls and upper electrode diffusion regions 34a, 340b, and 340c.乂 and source / and, please refer to FIG. 3B, forming an insulating layer 35 on the substrate 300: two: the insulating layer 3 50 can be, for example, an oxidation layer 35 commonly used in general semiconductor processes: Evening. Then use the lithography process and etching technology to define the insulation ^ 35 0, and define a standard that exposes the source / non-diffused region 3 働 at the place where the capacitor or bit line or the plug for connecting the interconnect is intended to be formed. Contact opening 360. After that, an implantation treatment step is applied so that the impurities can enter the substrate 30 0 ′ through the automatic contact opening 360 and an impurity diffusion region 365 is formed in the source / electrode diffusion region 3 to adjust the contact opening. Junction impurities. Among them, the types of impurities used to adjust the concentration of impurities at the interface of the contact opening 360, and the energy and dose at the time of blending can be selected as needed. Next, please refer to FIG. 3C. Using chemical vapor deposition, a polycrystalline silicon with a thickness of about 3 5 0 to 7 50 angstroms and mixed with impurities is opened in the reaction chamber at a temperature of about 6 2 0 to 6 8 0 C. The layer 37 covers the inner wall and the bottom of the insulating layer 360 and the self-aligned contact opening 360 in a compliant manner. The impurity in the polycrystalline silicon layer 370 may be selected from N-type impurities such as arsenic and phosphorus: or P-type impurities such as boron, and its doping concentration is about 1 020 atoms / era3. Furthermore, the temperature is 540 to 60 °. (: In the furnace, another-blended with

V. Description of the invention (7) The polycrystalline silicon layer 380 of the impurity is on the polycrystalline silicon layer 3 70, and the trench fills the self-aligning contact opening 360, and the thickness is about 3 50 0 to 45 00 angstroms. The impurity in the polycrystalite layer 380 may be selected from N-type impurities such as kun and phosphorus, or p-type hetero stones such as boron, and has a doping concentration of about 102 Qatoms / cin3. 'Then, referring to FIG. 3D, use the etch-back method or chemical mechanical polishing to' remove the excess polycrystalline silicon layer 38 0 and 370 to the insulating layer 35 0 in sequence 'and within the self-aligned contact opening 36 0 A plug 390 consisting of a compound crystal layer 302 and 370 is formed. This plug 3 9 0 has excellent step coverage and trench filling characteristics. In addition to overcoming the shortcomings of the poor plug filling characteristics of current plug materials, this plug 390 can also provide lower contact resistance (rc). And leakage characteristics to improve the shortcomings of the current sub-micron or deep sub-micron semiconductor plug manufacturing process. Embodiment Two: This embodiment applies the plug process described above to the embedded dynamic random access memory process. In the following, FIG. 4A to FIG. 4D will be described. FIG. 4A to FIG. 4D ^ The process of automatically aligning the contact opening of the embedded dynamic random access memory according to the present invention. First, referring to FIG. 4A, a semiconductor substrate 400 is provided, which can be divided into a cell area ready to form a memory and a peripheral circuit area connected to the cell areas. Among them, the cell region is formed with a transistor composed of gates 4 0, 42 0 and insulating sidewalls 425, and a source / drain diffusion region 43 0a, 430b, 43 0c; and a peripheral circuit region is formed The diffusion region 430d, and a shallow low trench isolation region (shal low trench isolation :) 440 for isolation. Next ’Please refer to FIG. 4B, first form an insulating layer 45. In FIG. 4A

C: \ ProgramFiles \ Patent \ 0503-4019-E_ptd page 1〇

The surface of the substrate 400 of the cell region and the peripheral circuit region shown, wherein the insulating layer can be, for example, an oxide layer commonly used in general semiconductor processes, such as an oxide layer. Then, the lithography program and etching technology are used to define the insulating layer 45. An automatic alignment contact °° 455 and 460 are defined at the predetermined positions of the cell 0 area and the peripheral circuit area, respectively. # Then, a step of implanting is applied so that impurities can enter the substrate 40 through the automatic alignment contact openings 455 and 460, and an impurity diffusion region is formed in the source / drain diffusion regions 43b and 430 (1, respectively. 465 & and 46513, which are used to adjust the concentration of impurities at the interface of the contact opening. Among them, the type of impurities used to adjust the degree of impurity distribution at the interface of the contact opening, and the energy and dose during planting can be selected as needed. In this embodiment, The impurity used for planting is phosphorus, and the energy during planting is 40kev, and the planting dose is 5 Xl014atoms / cm2. Then 'please refer to Figure 4C', first use the chemical vapor deposition method at a temperature of about 6 2 0 ~ 68 0 ° C A polycrystalline spar layer 470 with a thickness of about 350 ~ 7500 angstroms and mixed with impurities is formed to cover the inner wall and bottom of the insulating layer 450 and the self-aligned contact openings 455 and 460 smoothly. The impurities in the polycrystalline hair layer 470 may be selected from N-type impurities such as arsenic and phosphorus or p-type impurities such as boron. The impurity used in this embodiment is phosphorus, and its doped concentration is about 10Qatoms / cin 3 〇 Then, in the stove, at a temperature of 540 ~ 600 ° c Another polycrystalline silicon layer 480 doped with impurities is formed on the polycrystalline silicon layer 470, and trench filling self-aligned contact openings 455 and 460 are formed, and the thickness thereof is about 3500 to 4500 angstroms. The impurities in the silicon layer 480 may be selected from N-type impurities such as arsenic and phosphorus or P-type impurities such as boron. The impurity used in this embodiment is phosphorus and its doped concentration

Description of the invention (9) is about 102 Datoms / cm3. , ≫ Then, referring to FIG. 4D, using the etch-back method or chemical mechanical polishing ', the excess polycrystalline silicon layers 480 and 470 to the insulating layer 490 are sequentially removed, and they are self-aligned. The quasi-contact openings 455 and 460 are in the shape of: 5 shi 〇] 8: = 4 20 plugs composed of 490 and 50,000. Among them, the plug has 49,000 cups, has excellent step coverage ability and trench filling characteristics, in addition to being divided into: "except the shortcomings of poor filling characteristics of the material" plugs 490 and 5000 and can be value jc) ϊ ii i Random access memory preparation of capacitor lower electrodes and potential contacts with lower contact resistance (Rc) and leakage characteristics

Disadvantages of sub-micron or deep sub-micron semiconductor plug process. ， ”目 目 W Although the present invention has been disclosed in the preferred embodiment, if the present invention is not limited, # 何 熟习 此 技术 = not used and within the scope, all changes and the spirit defined by the entire body shall prevail Scope of patent application attached

C: \ ProgramFiles \ Patent \ 0503-4019-E.ptd page 12

Claims (1)

6. The scope of the patent application includes: 1. A plug process for forming an auto-aligned contact window. The steps include forming a contactless window; forming a substrate with a semiconductor element; an edge layer on the substrate, and defining a I aim to apply an impurity into the surface, shape, and apply the layer and quasi-contact 2. For oxidation 3. For oxidation 4. Heteropolycrystal 5. Heteropolycrystal 6. Heteropolycrystal substrate becomes a high And the self-contained low and trench fill a flat inside the South temperature opening as an application layer. Such as applying Shi Xi layer. If the Shixi layer is applied, such as the dream layer, the silicon layer is applied, wherein the high temperature is mixed therein, the high temperature is mixed therein, and the high temperature is implanted, so that impurities can pass through the self-aligned contact window and form a diffusion region; The spar layer covers the surface of the insulating layer and is aligned with the inner wall and the bottom of the contact window; / The doped polycrystalline silicon layer is doped with the self-aligned contact window at the high temperature; and / / day after day Silicon layer = Processing 'sequentially remove the excess of the low, mixed heterocrystalline silicon layer to the insulating layer. The polycrystalline silicon forms a process connecting the conductive element to the automatic pair of patents described in item 1. . The process described in item 2 of the insulating layer patent range, and the process described in item 1 of the insulating layer patent range is formed using a chemical vapor deposition method. The process described in item 4 of the patent has a formation temperature of about 62 0 to 6800 t :. The impurity in the process described in item 5 of the patent scope is phosphorus. C: \ Program Files \ Patent \ 0503-4019-E.ptd page 13 6. Scope of patent application _ 7. If the scope of the patent application scope of the complex polycrystalline silicon layer, the process described in the & Wherein the high temperature doping 8. If the scope of patent application is 10 atoms / cm. The thickness of the hetero-multicrystalline silicon layer is about the process described in the item, wherein the high temperature is doped, the low temperature is doped, the low temperature is doped, and the low temperature is 9. For example, the scope of application for patent is J: 7500 Angstroms. The heteromulticrystalline silicon layer is a process described in the item for forming a furnace, and the complex is 1 °. The process temperature of the complex raft of the process described in item 9 of the Ershenyili range of item 11 is as described above. Ma 540 ~ 60 0 C. The doping process of the method described in item 10 of the Λ dry circuit " doped with impurities in the silicon layer is phosphorus. The process described in item 11 of the doping patent range, wherein the impurity concentration in the low-temperature / doped silicon layer is about 10 ^ toms / cm3. The process according to item 2 of the patent application scope, wherein the thickness of the low-temperature-doped polycrystalline silicon layer is about 350,000 to 4500 Angstroms. Wherein the impurity cloth wherein the impurity 14. The process described in item 1 of the scope of patent application, the impurity used in the plant treatment step is phosphorus. 15. The process points as described in item 14 of the scope of patent application,-chemical planting: 40 keV, and the implantation dose is 5xl014atoms / cm 16. The process as described in item 1 of the scope of patent application 'Wherein the planarization treatment is performed by a chemical mechanical polishing method. 17. The process according to item 1 of the scope of the patent application, wherein the planarization process is an etch-back method. 1 8. —A process of plugging the automatic alignment contact window of the embedded dynamic random access memory, the steps include: C: \ ProgramFiles \ Patent \ 0503-40l9-E.ptd page 14 The bottom provides a cell area and a peripheral circuit area The edge avoidance circuit area is fixed! On the substrate, 1 and 1 are respectively applied to the self-aligned contact window; the peripheral lightning & a > plant step, so that the impurities can be self-aligned and contacted separately. The window enters the basal plane, and the thermally-transmuted polycrystalline spar layer of I 崎 is covered on the inner wall and the bottom of the self-aligned contact window; the upper and lower low-temperature mixed polyspar layer Replace the complex at the high temperature, fill the self-walls of the cell area and the peripheral circuit area with the knife, and the semiconductor-based sprint area and the fine blister area and the formation of the marginal surface crystalline silicon layer. The alignment layer and the 15 2 treatment 'sequence are used to remove the excess low temperature doped polycrystalline silicon Mn / plate-doped polycrystalline silicon layer to the insulating layer. The layer is [the process described in item 18 of the patent application scope of the layer ', wherein the insulating drawer is 20. The process as described in the item application scope of the patent application, and the absolute local silicon oxide layer. 21. The process as described in claim 18 in the scope of the patent application, wherein the high-temperature heterocrystalline silicon layer is formed by a chemical vapor deposition method. 2 2. The process described in item 2 of the scope of patent application, wherein the formation temperature of the high-temperature-doped polycrystalline silicon layer is about 62 ° 68 (TC. 23. The process described in item 22 of the scope of patent application 'Where the high temperature doped impurity in the polycrystalline silicon layer is phosphorus. C: \ Program Files \ Patent \ 0503-4019-E_ptd 6. Scope of patent application 24. The process described in item 23 of the scope of patent application, wherein the impurity concentration in the high-temperature doped polycrystalline silicon layer is about 102 flatoms / cm3. 25. The process according to item 24 of the scope of the patent application, wherein the thickness of the high-temperature doped polycrystalline silicon layer is about 350 to 750 angstroms. 26. The process according to item 8 of the scope of the patent application, wherein the low-temperature doped polycrystalline silicon layer is formed in a furnace. 27. The process according to item 26 of the scope of the patent application, wherein the formation temperature of the low-temperature-doped polycrystalline silicon layer is about 540 to 600 ° C. 28. The process according to item 27 of the scope of patent application, wherein the impurities in the high-temperature doped polyspar layer are filled. 29. The process as described in item 28 of the scope of patent application, wherein the impurity concentration in the high-temperature-doped polycrystalline silicon layer is about 102, 1: 〇1113 / (: 1113. 30. As the scope of patent application, paragraph 2 The process according to item 9, wherein the thickness of the low-temperature-doped polycrystalline silicon layer is about 3500 to 4500 angstroms. 31. The process according to item 18 of the scope of application for patent, wherein the impurity implantation treatment step is The impurity used is phosphorus. '32. The process as described in item 31 of the scope of patent application ', wherein the implantation energy of the impurity is 40 keV, and the implantation dose thereof is 5 X 1014 atoms / cm2. The process described in item 8 of the patent scope 'wherein the planarization process is completed by chemical mechanical polishing method. 3 4. The process described in item 8 of the patent scope' where the planarization process is performed by etch back method . C: \ Program Files \ Patent \ 0503-4019-E.ptd page 16