A7 B7 經漪部中央標準局员工消费合作社印製 五、發明説明（） 發明41域.： I 本發明係與一種半導體之元件結構及其製程有關，特 別是有關於一種自行對準冠狀電容之結構及形成自行對準 冠狀電容（crown-shaped capacitor)的製程方法，可進一步應 用兩密度動態隨機存取記憶禮的元件及製程之中。 發_明背景： 在電子工業中，記憶體裝置於電腦、通訊、及消費性 電子產品等系統中具有極重要的應用價值，在電子設備之 中’記憶體裝置大多應用於工作資料或資訊的交換及儲 存。在不同的系統需求下’這些資料可以暫時性或是永久 性的方式儲存於不同種類的記憶體裝置之中。 在眾多的記憶體種類中’動態隨機存取記憶體（dynamic random access memory; DRAM)是暫時性資料儲存及交換應 用中最重要的記憶裝置之一’在過去十年來，動態隨機存 取記憶體由於其快速度、高可靠度的特性，已成為半導體 產業的指標性產品般而言，一個動態隨機存取記憶胞 (DRAM cell)是由一個電晶體及一個電容所組成，最常見的 應用是使用金氧半場效電晶體（metal oxide semiconductor field effect transistor; MOSFET )來控制資料的寫入及讀 取，而電容則以儲存電荷及電位的方式來代表資料的狀 態，藉由此一設計，可使動態隨機存取記憶胞以較快的速 (請先聞讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（〇阳）人4規格（210乂 297公楚) 五、發明説明（） A7 B7 經濟部中央標準局資工消費合作社印？木 度及可靠度進行密集的讀寫操作。 為t降低動態隨機存取記憶體製程的成本及產品的競 爭力，必須增加單位晶片面積上所能使用的記憶胞數量， 單一晶片上動態隨機存取記憶胞的數目，已由早期的千百 個迅速增加到16M (百萬個）至64M，而256M及更高容量 的產品已公認是廿世紀前最具競爭力的產品之—。在高密 度的需求之下’由一個電晶趙及一個電容所組成的單一動 態隨機存取記憶胞’其所占用的面積必需在維持功能及操 作特性不變的前提之下，加以縮減數倍以提昇晶片的密 度。 然而’以電容結構的特性而言，其儲存電荷的能力會 與電極板的表面積成正比，因此，為了能在更小的面積下 提供相同的容量’必需改變傳統平板式電容的結構，以提 供更高的電容量。在電容結構的改良方面，已提出許多的 結構設計。例如M. Sakao等人於其著作“ACapacitoΓ-0 ve r - B i t - L i n e (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs”（in IEDM Tech. Dig.，p. 6 5 5, 199 0)中，提出形成電容於位元線上的結構，他們亦說 明在未來的動態隨機存取記憶體中，必須使用三次元的立 體結構，例如堆疊型電容、或是.溝渠電容等，以於較小的 面積中提供足夠的電容量。在堆疊型的電容結構中，可使 用增加電容高度的方式來增加其電容量，但此種方式也提 高了微影及圖案化製程的困難度，而使製程的挑戰性大為 增加。 (請先閲讀背面之注意事項再填耗本頁) "<· -3A7 B7 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention () Field 41 of the invention: I This invention is related to a semiconductor device structure and its manufacturing process, especially a self-aligned crown capacitor The structure and the manufacturing method of forming a self-aligned crown-shaped capacitor can further be applied to the two-density dynamic random access memory device and the manufacturing process. Development background: In the electronics industry, memory devices have extremely important application values in systems such as computers, communications, and consumer electronics. Among electronic devices, 'memory devices are mostly used for work data or information. Exchange and storage. Depending on the system requirements, these data can be stored temporarily or permanently in different types of memory devices. Among the many types of memory, 'dynamic random access memory (DRAM) is one of the most important memory devices in temporary data storage and exchange applications'. In the past decade, dynamic random access memory Due to its fast and high reliability characteristics, it has become an index product of the semiconductor industry. Generally speaking, a dynamic random access memory (DRAM cell) is composed of a transistor and a capacitor. The most common application is A metal oxide semiconductor field effect transistor (MOSFET) is used to control the writing and reading of data, while the capacitor represents the state of the data by storing charge and potential. With this design, it is possible to Make the dynamic random access memory cells faster (please read the notes on the back before filling this page) The paper size of the book applies to the Chinese national standard (〇 阳) person 4 specifications (210 乂 297) Description of invention () A7 B7 Printed by the Central Standards Bureau, Ministry of Economic Affairs, Industrial and Consumer Cooperatives? Woodness and reliability perform intensive read and write operations. In order to reduce the cost of the dynamic random access memory system and the competitiveness of the product, the number of memory cells that can be used per unit chip area must be increased. The number of dynamic random access memory cells on a single chip has been changed from the early hundreds. The number has rapidly increased to 16M (million) to 64M, and 256M and higher capacity products have been recognized as one of the most competitive products of the 20th century. Under the requirement of high density, the area occupied by a single dynamic random access memory cell consisting of a transistor and a capacitor must be reduced several times while maintaining the same functional and operating characteristics. To increase the density of the wafer. However, in terms of the characteristics of the capacitor structure, its ability to store charges will be directly proportional to the surface area of the electrode plate. Therefore, in order to provide the same capacity in a smaller area, the structure of the traditional flat capacitor must be changed to provide Higher capacitance. In the improvement of the capacitor structure, many structural designs have been proposed. For example, M. Sakao and others in his book "ACapacitoΓ-0 ve r-B it-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs" (in IEDM Tech. Dig., P. 6 5 5 In 199 0), a structure for forming a capacitor on a bit line is proposed. They also explained that in the future dynamic random access memory, a three-dimensional three-dimensional structure must be used, such as a stacked capacitor or a trench capacitor. In order to provide sufficient capacitance in a small area. In a stacked capacitor structure, the capacitance can be increased by increasing the height of the capacitor, but this method also increases the difficulty of the lithography and patterning process, making the process more challenging. (Please read the precautions on the back before filling this page) " < · -3
C 本紙張尺度適用中國國家摞準（CNS ) A4規格（21 〇 X 297公楚） 五、發明説明（） A7 B7 經漪部中央標潭局貝工消费合作社印裝 H. Wantanabe 等人於作品 “A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) f〇r 256 Mb DRAMs”（in IEDM Tech· Dig.，p.259，1992)中揭露了圓 柱形的電容結構，使用一種利用低壓氫氟酸以達成高選擇 率的新蝕刻技術，並全面性的形成半球形晶粒矽於已換雜 磷離子的圓柱形矽t極之上，來提供較高的電容值。 然而’習知的堆疊電容結構在形成立體型的電容時， 仍有無法解決的電極強度問題’一般而言，大部分的立體 電容結構是由多層分別形成及定義的矽層組合而成，在單 一結構上即有許多接合的界面，因此容易因界面處結合力 較弱而造成如斷裂等的缺陷問題，使製程的良率大為降 低。除此之外’在發展未來的動態隨機存取記憶體上，目 前的電容結構並無法提供足夠的電容量》 因此’目前需要提供改良的電容結構及方法，來提供 較高的電容值，並避免傳統電容結構及製程中如斷裂等的 缺陷問題，以增加製程的良率。 發明目的及概述： 本發明的目的為提供一種電容結構，以提供較高的電 容值。 本發明的另一目的為提供一種自行對準冠狀電容之結 構及形成自行對準冠狀電容的製程方法。 本發明的再一目的為提供一種冠狀電容之結構及其形 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 經濟部中央標準局員工消费合作社印製 A7 B7 I I五、發明説明（） 成的製程方法，可進一步應用高密度動態随機存取記憶體 的元件友製程之中。 本發明的再一目的為提供一種冠狀電容之結構及其形 成方法，以避免傳統電容結構及製程中如斷裂等的缺陷問 題，增加製程的良率。 本發明中形成電容於半導體基材上之方法可包含以下 步驟··首先形成第一氧化層於基材上；並形成一氮化層於 第一氧化層上；再形成第二氧化層於氮化層上；接著形成 第一矽層於第二氧化層上；之後定義一電極開口於第一矽 層、第二氧化層、及氮化層内，電極開口延伸至第一氧化 層上方；然後形成側壁結構於電極開口之兩側；再定義一 接觸開口於第一氧化層内，接觸開口位於電極開口下方未 被側壁结構覆蓋處；並去除側壁結構及靠近電極開口部分 之氮化層，以於第二氧化層下方形成底切結構；接著形成 一第二矽層均勻性的覆蓋於接觸開口内、底切結構内、電 極開口内、以及第一矽層上；之後形成一填平層於第二矽 層上；再對基材進行一平坦化步驟，平坦化至第二氧化層 之表面處；接著去除填平層及第二氧化層；並去除氮化層； 之後形成一介電層均勻性的覆蓋於第二矽層之上；最後形 成一導電層於介電層上。 本發明中之電容結構可包含：第一電極，第一電極由 第一導電材組成，第一電極並包含：一底部區；一由底部 向上延伸之冠狀區；一侧向延伸之邊緣區，邊緣區由底部 (請先閱讀背面之注意事項再填寫本頁)C This paper size applies to China National Standards (CNS) A4 specifications (21 × 297 Gongchu) V. Description of invention () A7 B7 Printed by H. Wantanabe et al. "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) f0r 256 Mb DRAMs" (in IEDM Tech. Dig., P. 259, 1992) discloses a cylindrical capacitor structure using a low-pressure hydrogen fluoride The acid uses a new etching technology to achieve a high selectivity, and comprehensively forms hemispherical grain silicon on top of the cylindrical silicon t pole of the doped phosphorus ion to provide a higher capacitance value. However, 'the conventional stacked capacitor structure still has unsolvable electrode strength problems when forming three-dimensional capacitors'. In general, most three-dimensional capacitor structures are composed of multiple layers of silicon layers that are separately formed and defined. There are many bonded interfaces on a single structure, so it is easy to cause defects such as fracture due to weak bonding at the interface, which greatly reduces the yield of the process. In addition, 'in the development of future dynamic random access memory, the current capacitor structure cannot provide sufficient capacitance.' Therefore, 'improved capacitor structures and methods are currently needed to provide higher capacitance values, and Defects such as breakage in traditional capacitor structures and processes are avoided to increase the yield of the process. Object and summary of the invention: The object of the present invention is to provide a capacitor structure to provide a higher capacitance value. Another object of the present invention is to provide a structure for self-aligning a crown capacitor and a manufacturing method for forming the self-aligning crown capacitor. Another object of the present invention is to provide a structure and shape of a crown capacitor (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) Central Ministry of Economic Affairs Standard Bureau employee consumer cooperative printed A7 B7 II V. Description of the invention () The process method can be further applied to the high-density dynamic random access memory component friend process. Another object of the present invention is to provide a structure of a crown capacitor and a method for forming the same, so as to avoid defects such as breakage and the like in the conventional capacitor structure and the manufacturing process, and increase the yield of the manufacturing process. The method for forming a capacitor on a semiconductor substrate in the present invention may include the following steps: firstly forming a first oxide layer on the substrate; and forming a nitride layer on the first oxide layer; and then forming a second oxide layer on the nitrogen Forming a first silicon layer on the second oxide layer; then defining an electrode opening in the first silicon layer, the second oxide layer, and the nitride layer, and the electrode opening extends above the first oxide layer; and Form a sidewall structure on both sides of the electrode opening; define a contact opening in the first oxide layer, the contact opening is located under the electrode opening and not covered by the sidewall structure; and remove the sidewall structure and the nitride layer near the electrode opening to An undercut structure is formed under the second oxide layer; then a second silicon layer is uniformly formed to cover the contact opening, the undercut structure, the electrode opening, and the first silicon layer; and then a fill layer is formed on On the second silicon layer; performing a planarization step on the substrate to planarize the surface of the second oxide layer; then removing the filling layer and the second oxide layer; and removing the nitride layer; Uniformity of the dielectric layer overlying the second silicon layer; finally forming a conductive layer on the dielectric layer. The capacitor structure in the present invention may include: a first electrode, the first electrode is composed of a first conductive material, and the first electrode includes: a bottom region; a crown region extending upward from the bottom; an edge region extending laterally, The margin area is from the bottom (please read the notes on the back before filling this page)
、^T 本紙張尺度適用中國國家榇準（CNS ) Λ4規格（210X 297公釐） 經濟部中央標準局Μ工消费合作社印製 A7 B7五、發明説明（） 區側向向外延伸；以及一接觸區由底部向下延伸至基材 處；電容結構並包含一介電層於第一電極上；以及一第二 電極於介電層上，第二電極則由第二導電材組成。 圖式簡箪說明： 第一圖顯示本發明中形成第一氧化層、氮化層、第 二氧化層、以及第一矽層於基材上之截面示 意圖。 第二圖 顯示本發明中定義一電極開口於第一矽 .層、第二氧化層、及氣化層内之截面示意 圖。 第三圖 顯示本發明中形成侧壁結構於電極開口之 兩側的截面示意圖.。 第四圖 顯示本發明，中定義一接觸開口於第一氧化 層内·_的截面示意圖， 第五圖 顯示本發明中去除側壁結構及靠近電極P4 口部分之氮化層，以於第二氧化層下方形成 底切結構的截;面示意圖，。 第六圖 顯示本發明中形成一第二矽層均勻性的覆 蓋於接觸開口内、底切結構内、電極開口 内、以及第一矽層上的截面示意圖。 第七圖 顯示本發明中形成一填平層於第二矽層上 的截面示意圖。 (請先閱讀背面之注意事項再填寫本頁) 訂 Ί絲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） A7 B7 五·、發明説明（ 第八圖 第九圖 第十圖 第十一圖 第十二圖 顯示.本發明中對基材進行一平*旦化步驟後 的截面意圖。 顯示本發明中去除填平，層及第二氧.化層的 _ 截面示意圖—°- 顯示本發明中去除氮化層的截面示意圖。 顯示本發明中形成一介電層均勻性的覆蓋 於第二矽層之上的截面示意圖。 顯示本發明中形成一導電層於介電層，以完 成電容結構的截面示意圖。 發明詳細説明 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消贽合作社印$i 本 形成自 力，並 進一步 之中， 參 製造動 成如電 電容的 一般的 首 而言 發明的目的為提供一種自行對準冠狀電容之結構及 行對準冠狀電容的製程’可增加電容的電荷儲存能 避免傳統電容結構及製程中如斷裂等的缺陷問題’ 可應用於高密度動態隨機存取記憶體的元件及製程 增加產品的特性及製程的良率。 ^第〆圖所示，首先提供一半導體基材10，以一般 態隨機存取記憶體等元件的製程而言，基材會先形 ΐ曰體等的主要元件，為了詳細的介紹本發明中形成 製程，圖中並未顯示電晶體’而直接以基材10代表 基材或是已形成電晶體於其上的基材。 ^形成第一氧化層12於基材10上’以較佳實施例 第一氧化層12可為一由化學氣相沈積（chemical •V3 線 本紙張尺度適用中國國家標绛（CNS) Λ4規格（2丨0X 297公釐） 經濟部中央標準局员工消费合作社印裝 A7 B7 [五、發明説明（） vapor deposition; CVD)形成之二氧化梦層；接著形成一氛 化層1 41於第一氧化層1 2上，氮化層1 4同樣可使用化學氣 相沈積法沈積氮化矽而形成；並於氮化層14上，同樣使用 化學氣相沈積方式形成第二氧化層1 6 ,•之後形成第一矽層 18於第二氧化層16，第二氧化層16於本例中可為一由習 知之沈積方式所形成之多晶矽層，而形成如圖中所示之多 層堆疊結構。 參見第二圖所示，定義一電極開口 20於第一矽層18、 第二氧化層16、及氮化層14之内，電極開口 20用以定義 所需形成之電極的外部形狀，電極開口 20定義的位置延伸 至第一氧化層12的上方，電極開口 20的定義方式，可使 用習知微影製程及圖案化製程，利用一光阻層22的形成， 來定義電極開口 20的區域，再配合如乾蝕刻等的製程，即 可陸續其定義區域下方的第一矽層18、第二氧化層16、及 氮化層14，而形成電極開口 20，本例中之電極開口可為一 圓柱形開口 ，以定義成以圓形的冠狀電容。 接著形成側壁結構24於電極開口 22之兩側，如第三 圖中所示，本例中之側壁結構24可使用氮化矽間隙壁的結 構，氮化矽間隙壁的形成，可先沈積一氮化矽層、再加以 回蝕後即可形成，側壁結構24用以定義需形成接觸洞或接 觸開口的位置。 參見第四圖所示，接著以側壁結構24為罩幕，可利用 乾蝕刻的方式，定義一接觸開口 26於第一氧化層12之内， I--,---------- 裝------訂-----^--幼 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 五、發明説明（ 接觸開口 26位於電極開口 2〇下方未被側 處，利角側壁結構24為罩幕來 、構24覆基 (諳先閲讀背面之注意事項再填寫本頁) 用複雜的微影製程，而以自行對準的方式準確的：：免使 開口 26，一般而言，接觸開口 26會 義接每 :接面區，以達成電晶趙與電容器連接來構成記 參見第五圖所示，之後去除側壁結構以及 口 20部分之氮化層14，以 電極保 .^ 罘一氧化層16的下方形盍该 :結構28,本例中去除側壁結構24及部分之氣化二= 夹:，可利用-溼蚀刻製程，使用㈣酸⑻p〜）為蚀刻齋 來加以進行。接著形成-第二石夕層3〇於基材、〇的上方， 如第六圓所示，第二…。係以均勾性的沈積方式，以均 句的厚度覆蓋於接觸開口 26内、底切結構28内、電極開 口 20内、以及第一石夕層18之上，第二梦層3〇可為一換雜 之多晶矽’並可以習知的沈積方式形成，本例中係使用一 換雜η型雜質的多晶矽，以提供較佳的導電性。 經濟部中央標準局员工消费合作社印製 參見第七圖所示，接著形成一填平層32於第二矽層3( 之上填平層32用以填平基材丨〇表面上凹陷之區域，以 提供較佳的表面平坦度，以使後續進行的平坦化製程具有 更好的平坦化效果，本例中填平層32係使用一旋塗玻璃層 (spin-on-glass; SOG) ’以形成良好的填平效果。 參見第八圖所示，即是對基材10進行一平坦化步鄉， 以將基材10進行平坦化至第二氧化層16之表面處，以較 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 五、發明説明（） Α7 Β7 經濟部中央標準局—工消費合作社印^ 佳實施例而言’平坦化製程可應用一化學機械研磨 (chemidal mechanical polishing; CMP)製程，以研磨基材 10 的表面至一均勻的高度。 接著去除填平層32及第二氧化層16,如第九圖所示， 可利用氫氟酸（HF)溶液以溼蝕刻方式將同為氧化矽材質的 填平層32及第二氧化層16去除，在進行溼蝕刻時，氮化 屠14及第二梦層34可做為一良好的钮刻中止層，而防止 其下方的第一氧化層12受到蝕刻的影響，之後去除氮化層 14 ’本例中可以利用一溼姑刻製程.，使用熱填酸（h3p〇4)為 蚀刻劑來加以進行’而得到以第二矽層34做為第一電極的 λ整形狀’藉由本發明中的電容結構’可使垂直冠狀區34b 能由邊緣區3 4c的良好支撐而有良好的強度，且由於本發 明中的第一電極係由單一的矽材質一次沈積而成，可避免 傳統方法中電極由多層矽層組合而導致接面處強度欠佳的 缺點。 參見第Η 圖所示’形成一介電層36均勻性的覆蓋於 第二梦層34之上’介電層36可使用如氮化矽-氧化矽層 (〇-Ν)、氧化矽-氮化矽-氧化矽層（0-Ν-Ο)、ΡΖΤ層、BST層、 及氧化纽層等的材料。最後形成一導電層38於介電層36 上，如第十二圖所示，以做為電容的第二電極，一般而言， 導電層38可使用如摻雜之矽層或金屬層等的材料，並可視 材料的不同而可以沈積或濺鍍的方式加以形成。 同樣參見第十二圖，本發明中形成於基材1〇上方的電 (請先閱讀背面之注意事項再填寫本頁) 訂 本纸張尺度適财DU家縣（CNS ) A4規格（2丨㈣97公廣） A7 B7 五、發明説明（ 容結構可包含第一電極34、形成於第一電極34上的介電 36、以友形成於介電層36上並由第二導電枒所組成的第二 電極38;第一電極34由第一導電材組成’可包含一底部Z 34a、一由底部向上延伸之冠狀區3仆、一側向延伸之邊緣 區34c、以及一接觸區34d，邊緣區34c係由底部區34a側 向向外延伸，而接觸區34d則由底部區34a向下延伸至基 材10處；第二電極38位於介電層上，可由第二導電材組 成。第一電極34的下方並可包含做為下方介電層的第一氧 化層12，位於第一電極34與基材1 〇之間。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者，於領悟本發明之精神後’在不脫離本發明之精 神範圍内’當可作些許更動潤飾及等同之變化替換，其專 利保護範圍當視後附之申請專利範圍及其等同領域而定。 (諳先閱讀背面之注意事項再填寫本頁) 訂, ^ T This paper size is applicable to China National Standards (CNS) Λ4 specifications (210X 297 mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs M Industrial Consumer Cooperative A7 B7 V. Description of the invention () The area extends laterally outwards; and The contact area extends from the bottom to the substrate; the capacitor structure includes a dielectric layer on the first electrode; and a second electrode on the dielectric layer, and the second electrode is composed of a second conductive material. Brief description of the drawings: The first figure shows a schematic cross-sectional view of a first oxide layer, a nitride layer, a second oxide layer, and a first silicon layer formed on a substrate in the present invention. The second figure shows a schematic cross-sectional view of an electrode opening defined in the first silicon layer, the second oxide layer, and the vaporization layer in the present invention. The third figure is a schematic cross-sectional view of a sidewall structure formed on both sides of the electrode opening in the present invention. The fourth figure shows the present invention, which defines a cross-sectional schematic diagram of a contact opening in the first oxide layer. The fifth figure shows the removal of the sidewall structure and the nitride layer near the electrode P4 port in the present invention for the second oxidation. A section of the undercut structure is formed below the layer; FIG. 6 is a schematic cross-sectional view showing the formation of a second silicon layer uniformly covering the contact opening, the undercut structure, the electrode opening, and the first silicon layer in the present invention. FIG. 7 is a schematic cross-sectional view of a fill layer formed on the second silicon layer in the present invention. (Please read the notes on the back before filling this page.) The size of this paper is applicable to the Chinese National Standard (CNS) A4 size (210 X 297 mm) A7 B7 V. Description of the invention (eighth figure ninth figure no. The tenth figure, the eleventh figure, and the twelfth figure show the cross-sectional view of the substrate after a flattening step in the present invention. It shows the cross-section schematic diagram of the present invention to remove the filling level, the layer and the second oxygen. °-Shows a schematic cross-sectional view of removing the nitride layer in the present invention. Shows a cross-sectional schematic view of forming a conductive layer uniformly overlying the second silicon layer in the present invention. Shows forming a conductive layer on the dielectric layer in the present invention In order to complete the cross-sectional schematic diagram of the capacitor structure. Detailed description of the invention (please read the precautions on the back before filling out this page) The staff of the Central Standards Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives, printed $ i to become independent, and further, The general purpose of the invention, such as capacitors, is to provide a structure for self-aligning crown capacitors and a process for row-aligning crown capacitors. It can increase the charge storage of capacitors and avoid the traditional Defects such as cracks in the capacitive structure and process' can be applied to high-density dynamic random access memory components and processes to increase product characteristics and process yield. ^ As shown in the figure below, a semiconductor substrate is first provided 10. In terms of the manufacturing process of the general random access memory and other components, the substrate will first form the main components such as the body. In order to introduce the forming process in the present invention in detail, the transistor is not shown in the figure and directly The substrate 10 represents the substrate or the substrate on which the transistor has been formed. ^ Forming the first oxide layer 12 on the substrate 10 'In a preferred embodiment, the first oxide layer 12 may be a chemical vapor phase. Deposition (chemical • V3 line paper size applies to Chinese National Standard (CNS) Λ4 specification (2 丨 0X 297 mm)) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs [V. Description of the invention () vapor deposition; CVD ) Forming a dream dioxide layer; then forming an atmosphere layer 1 41 on the first oxide layer 12, and the nitride layer 14 can also be formed by depositing silicon nitride using chemical vapor deposition; and on the nitride layer 14 on the same use of chemistry A second oxide layer 16 is formed by phase deposition, and then a first silicon layer 18 and a second oxide layer 16 are formed. The second oxide layer 16 in this example may be a polycrystalline silicon layer formed by a conventional deposition method, and A multilayer stack structure is formed as shown in the figure. Referring to the second figure, an electrode opening 20 is defined in the first silicon layer 18, the second oxide layer 16, and the nitride layer 14, and the electrode opening 20 is used to define The external shape of the electrode to be formed, the position defined by the electrode opening 20 extends above the first oxide layer 12, and the definition method of the electrode opening 20 can use a conventional lithography process and a patterning process, using a photoresist layer 22 The formation of the electrode opening 20 defines the area of the electrode opening 20, and then cooperates with processes such as dry etching to successively form the first silicon layer 18, the second oxide layer 16, and the nitride layer 14 below the defined area to form the electrode opening. 20, the electrode opening in this example may be a cylindrical opening, which is defined as a circular crown-shaped capacitor. Next, a sidewall structure 24 is formed on both sides of the electrode opening 22. As shown in the third figure, the sidewall structure 24 in this example may use a structure of a silicon nitride spacer. For the formation of a silicon nitride spacer, a silicon nitride spacer may be deposited first. The silicon nitride layer can be formed after being etched back. The sidewall structure 24 is used to define a position where a contact hole or a contact opening needs to be formed. Referring to the fourth figure, the side wall structure 24 is used as a mask, and a contact opening 26 can be defined in the first oxide layer 12 by dry etching. I-, --------- -Packing ------ Order ----- ^-Young (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 5 、 Explanation of the invention (The contact opening 26 is located below the electrode opening 20 and is not on the side. The sharp-corner side wall structure 24 is used as a curtain and the structure is covered with a base (谙 Please read the precautions on the back before filling this page). The process is accurate by self-alignment :: avoid opening 26, in general, contact opening 26 will be connected to each other: the interface area, to achieve the connection between the transistor and the capacitor, see Figure 5 After that, the sidewall structure and the nitride layer 14 of the port 20 portion are removed to protect the electrode. ^ The lower square of the oxide layer 16 should be: Structure 28, in this example, the sidewall structure 24 and the gasification of the portion are removed. :, Can be carried out using a -wet etching process, using acetic acid (p ~) for etching. Next, a second stone evening layer 30 is formed on the substrate and 0, as shown in the sixth circle, the second ... The uniform deposition method covers the inside of the contact opening 26, the undercut structure 28, the electrode opening 20, and the first stone layer 18 with a uniform thickness. The second dream layer 30 may be A doped polycrystalline silicon can be formed by a conventional deposition method. In this example, a polycrystalline silicon doped with n-type impurities is used to provide better conductivity. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, as shown in Figure 7, and then forming a filling layer 32 on the second silicon layer 3 (on top of the filling layer 32 is used to fill the recessed area on the surface of the substrate In order to provide better surface flatness, so that the subsequent planarization process has a better planarization effect, the filling layer 32 in this example uses a spin-on-glass (SOG) layer. In order to form a good filling effect, as shown in FIG. 8, a flattening step is performed on the substrate 10 to planarize the substrate 10 to the surface of the second oxide layer 16 to compare with the paper. The scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 5. Description of the invention () Α7 Β7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives chemidal mechanical polishing (CMP) process to polish the surface of the substrate 10 to a uniform height. Next, the filling layer 32 and the second oxide layer 16 are removed. As shown in the ninth figure, a hydrofluoric acid (HF) solution can be used Silicon oxide The quality filling layer 32 and the second oxide layer 16 are removed. When performing wet etching, the nitriding layer 14 and the second dream layer 34 can be used as a good button stop layer to prevent the first oxide layer below it. 12 is affected by etching, and then the nitride layer is removed. 14 'A wet etching process can be used in this example. Hot filling acid (h3p〇4) is used as an etchant to obtain the second silicon layer 34. Shape the lambda of the first electrode 'by the capacitor structure in the present invention, the vertical crown region 34b can be well supported by the edge region 34c and have good strength, and because the first electrode system in the present invention is composed of a single electrode The silicon material is deposited at one time, which can avoid the disadvantage of poor strength at the joint caused by the combination of multiple layers of silicon electrodes in the traditional method. See Figure '' Forming a dielectric layer 36 uniformly covering the second The dielectric layer 36 on the dream layer 34 may be, for example, a silicon nitride-silicon oxide layer (0-N), a silicon oxide-silicon nitride-silicon oxide layer (0-N-0), a PTZ layer, a BST layer, And oxide button layers, etc. Finally, a conductive layer 38 is formed on the dielectric layer 36, as shown in FIG. As the second electrode of the capacitor, in general, the conductive layer 38 can be formed of a material such as a doped silicon layer or a metal layer, and can be formed by deposition or sputtering depending on the material. See also Twelfth figure, the electricity formed on the substrate 10 in the present invention (please read the precautions on the back before filling this page). The size of the paper is suitable for Ducai County (CNS) A4 specification (2 丨 ㈣97) A7 B7 V. Description of the invention (The capacitor structure may include a first electrode 34, a dielectric 36 formed on the first electrode 34, and a second electrode formed on the dielectric layer 36 and formed of a second conductive ytterbium. Electrode 38; the first electrode 34 is composed of a first conductive material, and may include a bottom Z 34a, a crown region 3 extending upward from the bottom, an edge region 34c extending laterally, and a contact region 34d and an edge region 34c The bottom region 34a extends laterally outward, and the contact region 34d extends from the bottom region 34a down to the substrate 10. The second electrode 38 is located on the dielectric layer and may be composed of a second conductive material. Below the first electrode 34 may include a first oxide layer 12 as a lower dielectric layer, which is located between the first electrode 34 and the substrate 100. The present invention is described above with a preferred embodiment, which is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention. Those skilled in the art will appreciate the spirit of the present invention without departing from the present invention. Within the scope of the spirit of the invention, when some modifications and equivalent changes can be made, the scope of patent protection depends on the scope of the patent application and its equivalent fields. (谙 Please read the notes on the back before filling this page)
''Λ,, J 經濟部中央標隼局®:工消费合作社印製 11 本紙張尺度適用中國國家標準（CNS )八4規格（2丨0><297公釐）'' Λ ,, J Central Bureau of Standards, Ministry of Economic Affairs®: Printed by the Industrial and Consumer Cooperatives 11 This paper size applies to China National Standard (CNS) 8-4 specifications (2 丨 0 > < 297 mm)