TW383454B - Manufacturing method for buried contact - Google Patents

Abstract

The invention relates to a kind of manufacturing method for buried contact which removes the high junction resistance caused by trenches during buried contact processing. The formed polycide spacer in the trench will not cut or block current path of source/drain junction caused by trench forming so as to reduce the resistance at trench junction.

Description

^ 348twf.d〇c / 008

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (丨) The present invention relates to a semiconductor process, and in particular, to a buried contact manufacturing method, which can be used for buried contact Elimination of high junction resistance caused by trenches during the manufacturing process. The conventional buried contact process is prone to contact with the substrate through the N + junction (source / drain region). Therefore, the junction may be cut off or high junction resistance 値 may occur. The following is a description of a conventional buried contact manufacturing method with reference to FIGS. 1A to 1F. First, refer to Figure 1A. A shallow trench isolation (STI) 102 is formed on a semiconductor substrate 100. Thereafter, a gate oxide layer 1.04 and a polycrystalline silicon layer 106 defined by etching are sequentially formed on the substrate 100. Then, N + ion implantation is performed to form an N + junction 108 on the substrate 100. After that, please refer to FIG. 1B. A polycrystalline silicon layer 110 and a metal silicide layer 112 are formed over the substrate 100. Then 'Please refer to FIG. 1C. The etching defines the metal silicide layer 112, the polycrystalline silicon layer 110, and the polycrystalline silicon layer 106 to form a buried contact 116 of a gate electrode II4 and an electrical connection N + interface 108. However, it is usually easy to form a trench 118 at this time, which penetrates the N + junction 108 and enters the substrate 100. Again, please refer to Figure 1D. N · ion implantation is performed to form an N · contact surface 120 on the substrate 100; at the same time, because the trench 118 penetrates the N + interface 108, an N_ interface 122 is also formed on the substrate 100 below the trench 118 . Next, 'please refer to FIG. 1E. A spacer 12 is formed on the substrate 100. Due to the existence of the trench 118, the partition wall 124 will also be shaped. 3 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X29 # 7 公 董> ------------ (please first (Read the notes on Goumen and fill out this page)

1T 3348twf, doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. The invention description (>) is completed in the trench 118. After that, please refer to Figure 1F. N + ion implantation is performed to form an N + interface 126 on the substrate 100. The N + interface 26 is located between the N + interface 08 and the N- interface 12. The structure formed by this process method will form a partition wall I24 in the trench U8, so that the N + junction 108 will be cut off, causing the barrel junction resistance 値. The conventional buried contact process is prone to the situation where the trenches eat through the N + junction (source / drain region) and contact with the substrate and the junction is cut off; Zone) and cause high junction resistance 値. Therefore, the main object of the present invention is to provide a new method for manufacturing a buried contact process, which can eliminate the high junction resistance caused by trenches caused by the buried contact process. According to the main purpose of the present invention, a method for manufacturing a buried contact is proposed, which is to use polycrystalline silicon spacers to penetrate into the trench, thereby reducing the junction resistance. This process method includes: (a) providing a substrate on which a shallow trench isolation has been formed; (b) sequentially forming a gate oxide layer and a first conductive layer defined by etching on the substrate; First N + ion implantation is performed to form a first N + junction on the substrate; (d) a second conductive layer and a metal silicide layer are formed over the substrate; (f) etching defines the metal silicide layer, and the second The conductive layer and the first conductive layer 'form a buried contact between the gate electrode and the first N + junction electrically connected; (g) performing N · ion implantation to form a first N · junction on the substrate; (H) forming a polycrystalline silicon spacer on the substrate; performing second N + ion implantation to form a second N + junction on the substrate and doping the polycrystalline silicon spacer; and etching back the polycrystalline silicon. The gap wall to the substrate surface. (Please read and read the notes »before filling out this page)

3348twf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (3) In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following is particularly preferred. The embodiments and the accompanying drawings are described in detail as follows: Brief description of the drawings: Figures 1A to 1F show schematic cross-sectional views of the manufacturing process of a conventional buried contact; and Figures 2A to 2G show a first embodiment of the present invention. A cross-sectional view of a manufacturing process of a buried contact in a preferred embodiment. Explanation of the marks of the drawings: 100, 200: substrate 102, 202: shallow trench isolation 104, 204: gate oxide layer 106, 110, 206, 210: polycrystalline silicon layer 108, 126, 208, 226: N + junction 112, 212: metal silicide layer 114, 214: gate 116, 216: buried contact 118, 218: trench 120, 122, 220, 222: N-junction 124: spacer wall 224: polycrystalline silicon gap Wall Embodiment A method for manufacturing an embedded contact according to a preferred embodiment of the present invention will be described below with reference to FIGS. 2A to 2G. Please read

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The paper size of the X-book is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 3348twf.doc / 008 Printed A7 B7 by the Consumers ’Cooperative Work of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the Invention (ll) First, please refer to Figure 2A. A shallow trench isolation 202 is formed on a semiconductor substrate 200. Thereafter, a gate oxide layer 204 defined by etching and a conductive layer (such as a polycrystalline silicon layer) 206 are sequentially formed on the substrate 200. Then, N + ion implantation is performed to form an N + interface 208 on the substrate 200. F 戋, please refer to Figure 2B. A conductive layer (such as a polycrystalline silicon layer) 210 and a metal silicide layer 212 are formed over the substrate 200. Then, refer to Figure 2C. The etching defines the metal silicide layer 212, the conductive layer 210, and the conductive layer 206 to form a buried contact 216 between the gate electrode 214 and the N + interface 208 which is electrically connected. However, it is usually easy to form a trench 218 at this time, which penetrates the N + junction 208 and enters the substrate 200. Again, please refer to Figure 2D. 1ST ion implantation is performed to form an N · contact surface 220 on the substrate 200; at the same time, because the trench 218 penetrates the N + interface 208, an N · contact surface 222 is also formed on the substrate 200 below the trench 218. Next, refer to Figure 2E. A polysilicon spacer 224 is formed on the substrate 200. The partition wall 224 will be formed in the trench 218 at this time. After that, please refer to Figure 2F. N + ion implantation is performed to form an N + junction 226 on the substrate 200. The N + junction 226 is between the N + junction 208 and the N_ junction 22. At the same time, the N + ion implantation step is also doped with the polycrystalline silicon spacer 2M, which can reduce the resistance 値 of the polycrystalline silicon spacer 224. Next, refer to Figure 2G. Etch back the polycrystalline silicon spacer wall 224 to the surface of the substrate 2000; thus, the polycrystalline silicon spacer wall 224a is left back in the trench 218. The structure formed by the process of the present invention will form in the trench 218 ______ 6 This paper size is applicable to China National Standards (CNS) A4 ^^ (2IGx297 mm) (Fill in this page)

3348twf.doc / 008 A7 B7 V. Description of the Invention (y) The polycrystalline silicon spacer 2 2 4 a will prevent the N + junction 208 from being cut off due to the formation of the trench 218. Therefore, when the N + junction (source / drain region) may generate a trench (whether it is eaten through or not eaten through), the buried contact process proposed by the present invention can recrystallize the silicon spacer wall to reduce the junction resistance 値. Therefore, the embedded contact process is a secure process of static random access memory (SRAM), which can ensure product reliability. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. For example, various N-type ion implants can be replaced with P-type ion implants to form P-type elements (such as PMOS). Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China for consumer cooperation and printing, good w GM China National Standard (CNS> A4 Specification (210 > < 297 mm)

Claims (1)

Printed by the Employees 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A8 3348twf.doc / 008 B8 C8' D8 VI. Scope of Patent Application 1. A process method for embedded contact, including: providing a substrate, / a shallow channel has been formed thereon Trench isolation; sequentially forming a gate oxide layer and an s first conductive layer defined by etching on the substrate; performing first N + ion implantation to form a first N + junction on the substrate; on the substrate A second conductive layer and a metal silicide layer are formed above; the metal silicide layer, the second conductive layer, and the first conductive layer are defined by etching to form a gate and a gate electrically connected to the first N + junction. Buried contact; N · ion implantation is performed to form a first N_ junction on the substrate; a polycrystalline silicon spacer is formed on the substrate; second N + ion implantation is performed to form the substrate A second N + junction and doping the polycrystalline silicon spacer; and etching back the polycrystalline silicon spacer to the surface of the substrate. 2. The process method as described in item 1 of the patent application scope, wherein the first conductive layer includes a polycrystalline sand layer. 3. The process method described in item 1 of the patent application scope, wherein the second conductive layer includes a polycrystalline silicon layer. 4. The process method as described in item 1 of the scope of patent application, wherein the etching method is a specific contact time, and the metal silicide layer is used as an etching mask to etch the polysilicon spacer to the substrate. surface. 5. The process method described in item 1 of the scope of patent application, wherein, when the gate and the buried contact are formed, the first N + junction is etched and penetrated into shape 8 (Please read the precautions on the back before reading) (Fill this page) Packing. This paper size applies to Chinese National Standards (CNS) A4 (210X297 mm) Printed by the Employees 'Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A8 3348twf.doc / 008 B8 C8' D8 VI. The scope of patent application becomes a canal ditch. 6. The process method described in item 5 of the scope of patent application, wherein performing N · ion implantation will form a second junction on the substrate below the trench. 7. The process method as described in item 6 of the patent application scope, wherein the polycrystalline silicon spacer wall is inserted into the trench. 8. The method of making a rod as described in item 1 of Shen Xiao's Patent Scope, "which is that the second, N + junction is between the first N + junction and the first N_ junction. 9. A method of manufacturing a buried contact, comprising: providing a substrate on which a shallow trench isolation has been formed; and sequentially forming a gate oxide layer and a first conductive layer defined by etching on the substrate Performing a first P + ion implantation to form a first P + junction on the substrate; forming a second conductive layer and a metal silicide layer above the substrate; etching to define the metal silicide layer and the second conductive Layer and the first conductive layer to form a buried contact between the gate electrode and the first P + junction; electrically implanted; forming a first P_ junction on the substrate; on the substrate Forming a polycrystalline silicon spacer; performing a second P + ion implantation, forming a second P + junction on the substrate, and doping the polycrystalline silicon spacer; and etching back the polycrystalline silicon spacer to the Substrate surface. 10. The process method described in item 9 of the scope of patent application, wherein the 9 paper sizes are applicable to the national standard (CNS) A4 specification (210X297 mm) '" (Please read the precautions on the back before filling (This page). Binding * Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed 3348twf.doc / 008 gg C8 · D8 6. The patent application Fanyuan first conductive layer includes a complex crystal sand layer. Π. The process method as described in item 9 of the patent application scope, wherein the second conductive layer includes a polycrystalline silicon layer. 12. The process method as described in item 9 of the scope of patent application, wherein the method is to etch at a specific uranium etching time, and the metal silicide layer is used as an etching mask to etch the polycrystalline silicon spacer to the substrate. surface. 13. The process method as described in item 9 of the scope of patent application, wherein when the gate is formed in contact with the buried type, uranium cuts through the first P + junction to form a trench. 14. The process method according to item 13 of the scope of patent application, wherein performing P · ion implantation will form a second P-junction on the substrate below the trench. 15. The process method as described in item 14 of the scope of application for a patent, wherein the polycrystalline silicon spacer wall is inserted into the trench. 16. The process method according to item 9 of the scope of patent application, wherein the second P + junction is between the first P + junction and the first junction. (Please read the precautions on the back before filling in this purchase) Packing · Binding-Silk 丨 10 paper sizes are in Chinese National Standard (CNS) A4 size (210X297)