五、發明說明（1) ' 本發明是有關於一種印刷電路板’且特別是有關於— 種用於晶粒故障分析的印刷電路板，其可以節省因晶粒封 裝（Package)及電路板上開關（Switch)、插座（s〇cket)等 元件及其繞線所衍生出來的成本及時間。 第1圖係習知晶粒故障分析用的印刷電路板的電路示 意圖。 在第1圖中’欲進行故障分析的晶粒（圖中未示）首先 經由標準封裝製程（如IHP或QFP封裝）包裝，藉以得到一封 裝好的1C 20。然後，在印刷電路板丨〇上設置一輸入電路 16(Inpnt circuit)、一開關電路 u(Switch)及一插座 12(S〇cket)。輸入電路16主要係連接故障分析用的測試電 壓，如圖中所不的Vi、vz、VGND。開關電路丨4主要係由輸入 電路1 6得到測試電壓Vi、y2、v⑽’並將測試電壓選擇性地 施加於插座1 2各接腳。而插座1 2則用以設置封裝好的I匸 20 ’用以將開關電路14所得到的測試電壓Vi、V2、v_分別 傳遞至封裝好的IC 20的各接腳。另外，封裝好的IC 2〇的 各接腳在前述封裝製程時已預先指定為欲進行故障分析的 晶粒的各接觸端，因此，測試電壓Vi、&、v_便可自輸入 電路16、經開關電路14及插座12傳送至封裝在封裝好的1(： 2 0内的晶粒，進而完成晶粒故障分析。 - 不過，這種印刷電路板必須事先封裝欲進行故障分析 的晶粒，並在印刷電路板上另外設置插座、開關電路等元 件及其衍生出來的繞線，因此所需時間及成本極高。 另外，各種封裝對應的插座不同，因此印刷電路板必V. Description of the invention (1) 'The present invention relates to a printed circuit board' and, in particular, to a printed circuit board for die failure analysis, which can save the package due to die and the circuit board Costs and time derived from components such as switches, sockets and their windings. Fig. 1 is a schematic circuit diagram of a printed circuit board for conventional grain failure analysis. In Figure 1, the die (not shown) for failure analysis is first packaged through a standard packaging process (such as IHP or QFP packaging) to obtain a packed 1C 20. Then, an input circuit 16 (Inpnt circuit), a switch circuit u (Switch), and a socket 12 (Socket) are provided on the printed circuit board. The input circuit 16 is mainly connected to the test voltage for fault analysis, such as Vi, vz, and VGND as shown in the figure. The switching circuit 4 mainly obtains the test voltages Vi, y2, and v⑽ ′ from the input circuit 16 and selectively applies the test voltages to the respective pins of the socket 12. The socket 12 is used to set the package I 匸 20 ′ to transmit the test voltages Vi, V2 and v_ obtained by the switching circuit 14 to the pins of the packaged IC 20 respectively. In addition, the pins of the packaged IC 20 have been designated in advance as contact points of the die to be analyzed for failure during the aforementioned packaging process. Therefore, the test voltages Vi, & 、 Transfer to switch package 14 and socket 12 to die packaged in package 1 (: 20, and complete die failure analysis.-However, this printed circuit board must package the die for failure analysis in advance In addition, sockets, switch circuits and other components and their derived windings are additionally provided on the printed circuit board, so the time and cost are extremely high. In addition, the sockets corresponding to various packages are different, so the printed circuit board must be
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須針對各種封裴分別設計，複雜度亦高。 再者，欲進行故障分析的晶粒封裂 亦無法達到。 ue fa) 有鑑於此’本發明的主要目的便是提供一種印刷 ，且特別5有關於一種用於晶粒故障分析的印刷電 ’其=以郎省因晶粒封裝（Package)及電路板上開關 (本\ltch)、插座（s〇cket)等元件及其繞線所衍生出來的成 板 低 另外，本發明的另一個目的就是提供一種印刷電 其可以適用於各種尺寸的晶粒，故設計複雜度可降 另外，本發明的再一個目的就是提供一種印刷電 板，其可以達到晶粒的背侧故障分析（Back side Μ)。 為達上述及其他目的，本發明乃提供一種用於晶 $分析的印刷電路板’可節省因晶粒封裝及電路板上 (、fwltch)、插座（Socket)等元件及其繞線所衍生的成^關 ，種電路板上具有一晶粒設置區，用以設置一晶粒。晶 設置區的四周則環繞有印刷佈線，其分別具有—端延=至 電路板的側邊並形成連接墊。另外，金屬連線則將晶粒的 接觸端選擇性地連接至印刷佈線，使故障分析用的測試電 壓可利用鱷魚夾、經由這些連接墊及印刷佈線傳送至晶粒 的接觸端。再者，為進行晶粒背側故障分析（Back side FA) ’晶粒設置區亦可以漏空形成一開口 ，使晶背外露以It must be designed separately for each type of seal, and the complexity is also high. Furthermore, grain cracking for failure analysis cannot be achieved. ue fa) In view of this, 'the main purpose of the present invention is to provide a printing, and in particular 5 relates to a printed circuit used for die failure analysis', which = a package and a circuit board in the province of Lang Components such as switches (slots), sockets (sockets), and their windings are low in board formation. In addition, another object of the present invention is to provide a printed circuit that can be applied to dies of various sizes. Design complexity can be reduced In addition, another object of the present invention is to provide a printed electrical board that can achieve back side failure analysis of the die. In order to achieve the above and other objectives, the present invention provides a printed circuit board for crystal analysis, which can save components derived from die packaging and circuit board (, fwltch), socket (Socket) and their windings. As a result, the seed circuit board has a die setting area for setting a die. A printed wiring is surrounded on the periphery of the crystal setting area, which has -end extension = to the side of the circuit board and forms a connection pad. In addition, the metal wiring selectively connects the contact end of the die to the printed wiring, so that the test voltage for failure analysis can be transmitted to the contact end of the die through the alligator clips through these connection pads and the printed wiring. Furthermore, for the back side FA analysis of the grain, the grain setting area may be left empty to form an opening, so that the crystal back is exposed.
五、發明說明（3) 便由晶粒背側進行故障分析。 為讓本發明之上述和豆 顯易懂，下文特舉一較佳^施、:寺徵、和優點能更明 細說明如下： 並配合所附圖式，作詳 圖式說明 側視圖 第一實施例 為郎省因晶粒封 及其繞線所衍生出來 目的，本實施例中欲 封裝。因_此印刷電路 置封裝後的晶粒。另 障分析的晶粒的各接 析用的測試電壓，因 關電路以切換測試電 伸至印刷電路板一側 的測試電壓可利用鱷 (S 1 〇 t )，輸入印刷電 第2A及2B圖分別 圖，·第1圖係習知用於晶粒故障分析的印刷電路板的示意 俯視=係本發明可用於晶粒故障分析的印刷電路板的 :2B圖係本發明可用於晶粒故障分析的印刷電路板的 裝及印刷 的成本， 進行故障 板中不需 外，經由 觸端可輕 此印刷電 壓。再者 邊並形成 魚夾（C 1 amp )直接 路板。 為本發明可用於晶 電路板上 並達成晶 分析的晶 要額外安 特殊的印 易地經由 路板中亦 ’印刷佈 一連接墊 開關、插座等元件 粒背側故障分析的 粒並不需事先加以 排對應的插座以設 刷佈線，欲進行故 打線連接至故障分 不需要額外安排開 線分別具有一端延 ’因此故障分析用 ’或經由插槽 粒故障分析的印刷5. Description of the invention (3) The failure analysis will be performed from the back side of the die. In order to make the above-mentioned Japanese bean of the present invention easy to understand, a better example, the temple sign, and the advantages can be explained in more detail as follows: In conjunction with the accompanying drawings, a detailed diagram will be given to explain the side view of the first implementation. For example, the purpose of Lang province is derived from the die sealing and its winding. In this embodiment, packaging is intended. Because of this, the printed circuit die is packaged. The test voltage for each analysis of the grains analyzed by the obstacle analysis can be switched to the printed circuit board by switching off the test voltage. The test voltage can be input to the printed circuit diagrams 2A and 2B. Separate diagrams. · The first diagram is a schematic plan view of a conventional printed circuit board used for die failure analysis. = A printed circuit board of the present invention that can be used for die failure analysis: 2B picture shows that the present invention can be used for die failure analysis. The cost of mounting and printing of the printed circuit board does not need to be carried out in the fault board, and the printing voltage can be lightened through the contact. Furthermore, a fish clamp (C 1 amp) is directly formed along the side. The crystals that can be used on a crystal circuit board and achieve crystal analysis according to the present invention need to be additionally installed with special printed materials via a printed circuit board, such as a pad, a connection pad, a switch, a socket, and other components. Failure analysis is not required in advance. Arrange the corresponding sockets to set the brush wiring. If you want to make a wire connection to the fault point, you don't need to arrange additional lines. The wires have one end extension 'for fault analysis' or printing through slot fault analysis.
C:\ProgramFiles\Patent\0503-3880-E.ptd第 6 頁 五 發明說明⑷1 '—~~ ------- 電路板的俯視圖及側視圖。 在第2 A圖中，用於晶粒故障分 -晶粒設置區，用以設置欲進行故障八J 電路板上具有 設置區四周環繞有複數條印刷佈線，：：工“立’該晶粒 該電路板-側邊並形成一連接墊端延伸至 性地連接該晶粒的接觸端至該些印刷=金屬連線則選擇 接觸端。 布線傳达至該晶粒的 晶位實施例中，#先在印刷電路板30表面定義一個 ?以設置欲進行故障分析的晶粒40。與習 ，不同的疋’晶粒4〇並不需要事先進行封穿， 接黏著在印刷電路3 〇上。另外， ^ 、 疋直 有數條印刷佈線42，如圖中所示乂周則圍繞 J立條印刷佈線。五铬 $、是以方形向晶粒設置區Α外侧依序排列1互不相 速接2別具有—端延伸至印刷電路板3 〇 一側邊並形成一 ^接=4，用以連接五個故障分析用的測試電壓 戶=〉、v2、v3、v4、Vgnd。而晶粒4〇各接觸端則利：中 線方式（金屬連線46)選擇性地連接至五條印刷佈線。 這種印刷佈線4 2的優點說明如下。 =一，晶粒40中欲進行故障分析的接觸端位置在各個 中不盡相同，因此將所有印刷佈線分別環繞於晶粒俨 置區A四周的結構可增加晶粒40中各接觸端連接各 壓的彈性。 、〇八电C: \ ProgramFiles \ Patent \ 0503-3880-E.ptd page 6 5 Description of the invention ⑷1 '-~~ ------- Top view and side view of the circuit board. In Fig. 2A, it is used for the die failure point-die setting area, which is used to set the eight J circuit board to be failed. There are multiple printed wirings around the setting area. The circuit board-side and forms a connection pad end extending to connect the contact end of the die to the printed = metal wires, then the contact end is selected. The wiring is transmitted to the crystal bit embodiment of the die. # First define a? On the surface of the printed circuit board 30 to set the die 40 to be analyzed for failure. Unlike Xi, the die 40 does not need to be sealed in advance, and is adhered to the printed circuit 30. In addition, there are several printed wirings ^ and 疋, as shown in the figure, and the printed wiring is around J. The five chromium $, is arranged in a square to the outside of the grain setting area A in sequence 1 at a speed. The connection 2 has a terminal that extends to one side of the printed circuit board 3 and a connection = 4 is used to connect five test voltages for failure analysis =>, v2, v3, v4, and Vgnd. 40. Each contact is advantageous: the center line method (metal connection 46) is selectively connected to five prints. The advantages of this printed wiring 4 2 are described below. = First, the positions of the contact terminals for failure analysis in the die 40 are different in each, so all the printed wirings are surrounded around the die placement area A, respectively. The structure can increase the elasticity of each contact end of the die 40 connected to each pressure.
五、發明說明（5) :ί 1 °式電[連接’因此印刷電路板不再需要另外安排開 關電路以切換各測試電壓至晶粒4〇中各接觸端。 第一，五條印刷佈線4 2各具有一端延伸至印刷電路板 W ^並形成—連接塾44，目此測言式電壓可利用經魚夹 50直接，或經由設置在電路板3〇側邊、用以扣住各連接墊 44的插槽（S1〇t)，輪入至印刷電路板30 ,如第2B圖所示。 第二實施例 Ί ξΜτ_㈣调 曰，外，為進行晶粒40的背側故障分析（如^职 曰曰粒40的背面必須露出來。這在習知技術中ϋ法*鍊的 =:因為欲進行故障分析的晶粒都已事先經過g裝，而本^又 貫施例則是在晶粒故障分析用的印刷電路板3〇上一曰 粒=置開口 A’（將第一實施例的晶粒設置區A鑽空）及其四曰曰 周環繞的印刷佈線42。與第一實施例相同，這些印刷佈 亦分別具有一端延伸至印刷電路板30 —側邊並形成—連接 墊44。晶粒40則安裝在晶粒設置開ϋΑ，上方（如第圖所 示），其接觸端經由打線選擇性地連接至印刷佈線4 2。 此，故障分析用的測試電壓可利用一鱷魚夾5〇、經 墊44及印刷佈線42傳送至晶粒4〇的接觸端。當然，£ 線42亦可與第一實施例相肖，以方形向外環繞 ：：： 開口 A，的四周。 ·日日校攻置 接著，說明如何將晶粒4〇架空在晶粒設置開 種方法。 Λ的— 首先，在印刷電路板30表面定義，如鑽空 open) —晶粒設置開口A，。並利用一薄膜（圖中未示）覆蓋V. Description of the invention (5): 1 ° electric [connection ', so the printed circuit board no longer needs to arrange an additional switching circuit to switch each test voltage to each contact terminal in the die 40. First, the five printed wirings 4 2 each have one end extending to the printed circuit board W ^ and form a connection 塾 44. For this purpose, the voltage can be measured directly through the fish clamp 50 or through the side of the circuit board 30, The slot (S10t) for holding each connection pad 44 is rotated into the printed circuit board 30, as shown in FIG. 2B. In the second embodiment, ξMτ_ is used to perform a backside failure analysis of the die 40 (for example, the back of the die 40 must be exposed. This is known in the conventional technology. The grains for failure analysis have been installed in advance, and this embodiment is described on the printed circuit board 3 for grain failure analysis. The grain = the opening A '(the first embodiment The die setting area A is drilled out) and the printed wirings 42 surrounded by the four circles. As in the first embodiment, these printed cloths also have one end extending to the side of the printed circuit board 30 and forming a connection pad 44. The die 40 is installed above the die set opening A, as shown in the figure, and its contact end is selectively connected to the printed wiring 4 2 through a wire. Therefore, the test voltage for failure analysis can use a crocodile clip 5 〇, transferred to the contact end of the die 40 via the pad 44 and the printed wiring 42. Of course, the line 42 can also be compared with the first embodiment, and surrounds in a square shape outward: :: around the opening A, Day school attack Next, explain how to set the grain 40 overhead in the grain to set the seed Λ-First, define on the surface of the printed circuit board 30, such as drilling open)-the die set the opening A ,. And covered with a film (not shown)
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五、發明說明（6) 在印刷電路板30背面之晶粒設置開口 Α’ 。待欲進行故障分 析的晶粒4 0黏在薄膜上、並以打線方式（金屬連線4 6 )連接 其中接觸點與各印刷佈線42後，再由印刷電路板30背面將 先前覆蓋的薄膜去除。如此，晶粒4 〇可以架空在印刷電路 板30的晶粒設置開口 a，。 另外’本實施例的其他部分則與第一實施例相同， 不再重述。 綜上所述，本發明的印刷電路板可以節省因晶粒 (Package)及電路板上開關（Switch)、插座（s 衮 件及其繞線所衍生出來的成本及時間。並且： 故障分析亦可以輕易完成。 〃的貪侧 露如上，然其並非用以 在不脫離本發明之精神 此本發明之保護範圍春 準。 ' 雖然本發明已以較佳實施例揭 限定本發明，任何熟習此技藝者， 和範圍内，當可做更動與潤飾，因 視後附之申請專利範圍所界定者為5. Description of the invention (6) An opening A 'is provided in a die on the backside of the printed circuit board 30. After the die 40 to be analyzed for failure is adhered to the film, and the contact points and the printed wirings 42 are connected by wire bonding (metal wiring 4 6), the previously covered film is removed from the back of the printed circuit board 30 . In this way, the die 40 can be suspended in the die openings a on the printed circuit board 30. In addition, the other parts of this embodiment are the same as those of the first embodiment and will not be described again. In summary, the printed circuit board of the present invention can save the cost and time derived from the package (Package) and the switches (switches), sockets (s) and their windings on the circuit board. And: Failure analysis also It can be done easily. The gluttonous side exposure is as above, but it is not intended to prevent the scope of the present invention from departing from the spirit of the present invention. 'Although the present invention has been limited to the present invention with preferred embodiments, anyone familiar with this Artists, and within the scope, can be modified and retouched, as the scope of the attached patent application is defined as