TW369697B - Shallow trench isolation technique with automatic alignment and good planarity - Google Patents

Abstract

This invention discloses an improved shallow trench isolation technique. First form pad oxide, nitride and polysilicon (or amorphous silicon) layers on the silicon semiconductor substrate, then subject the substrate to thermal oxidation process to form a thermal oxide on the substrate surface, and use lithography and plasma etching technique to form trenches on the substrate, and subject the substrate to thermal oxidation process again to form a thermal oxide layer on the trench surface, or to turn the polysilicon into poly-oxide and form a layer of thermal oxide on trench surface. Then use nitrogen plasma to undergo surface treatment or use plasma enhanced chemical vapor deposition, or form a thin low ozone tetraethylorthosilicate (low O3 TEOS) to remove the sensitivity of pattern density on base surface. Then undergo 1st CMP (chemical mechanical polishing) to remove part of the poly oxide, and use SACVD to form O3TEOS to fill out the trenches. Finally undergo 2nd CMP to remove excess O3TEOS and poly oxide to obtain shallow trench isolation with good planarity.