TW367555B - Post-processing method for plasma etching - Google Patents

Post-processing method for plasma etching

Info

Publication number
TW367555B
TW367555B TW087102641A TW87102641A TW367555B TW 367555 B TW367555 B TW 367555B TW 087102641 A TW087102641 A TW 087102641A TW 87102641 A TW87102641 A TW 87102641A TW 367555 B TW367555 B TW 367555B
Authority
TW
Taiwan
Prior art keywords
post
plasma etching
processing method
processing
semiconductor substrate
Prior art date
Application number
TW087102641A
Other languages
Chinese (zh)
Inventor
Kazue Takahashi
Ryoji Fukuyama
Tadamitsu Kanekiyo
Tsuyoshi Yoshida
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW367555B publication Critical patent/TW367555B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A kind of post-processing method for semiconductor substrate after plasma etching using gas containing chloride for the semiconductor substrate with aluminum wiring. In the post-processing, the gas used for polishing contains hydrogen and fluorine and the mixing ratio of the two is limited under 2%, but better 1%. Therefore, it can increase the polishing speed of the anti-erosive object and for better anti-erosion and superior ablation property so that the time of post-processing can be shortened and improve the treatment on sidewall ablation which can increase the productivity and yield rate.
TW087102641A 1997-03-05 1998-02-24 Post-processing method for plasma etching TW367555B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5034397 1997-03-05

Publications (1)

Publication Number Publication Date
TW367555B true TW367555B (en) 1999-08-21

Family

ID=12856283

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087102641A TW367555B (en) 1997-03-05 1998-02-24 Post-processing method for plasma etching

Country Status (2)

Country Link
TW (1) TW367555B (en)
WO (1) WO1998039799A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5358366B2 (en) * 2009-09-14 2013-12-04 東京エレクトロン株式会社 Substrate processing apparatus and method
KR101311277B1 (en) * 2011-12-16 2013-09-25 주식회사 테스 Substrate processing system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590223A (en) * 1991-01-22 1993-04-09 Toshiba Corp Manufacture of semiconductor device and semiconductor manufacturing device
JP3412173B2 (en) * 1991-10-21 2003-06-03 セイコーエプソン株式会社 Method for manufacturing semiconductor device
JPH08180698A (en) * 1994-12-22 1996-07-12 Toshiba Corp Semiconductor memory

Also Published As

Publication number Publication date
WO1998039799A1 (en) 1998-09-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees